diff --git a/crates/applications/stacked_cores/src/main.rs b/crates/applications/stacked_cores/src/main.rs
index 0f21cf1..cb27218 100644
--- a/crates/applications/stacked_cores/src/main.rs
+++ b/crates/applications/stacked_cores/src/main.rs
@@ -1074,6 +1074,28 @@ fn drive_map_3stack_with_init_43(amp0: f32) -> [[ClockState; 3]; 5] {
     ]
 }
 
+#[allow(unused)]
+fn drive_map_3stack_with_init_44(amp0: f32) -> [[ClockState; 3]; 7] {
+    use ClockState as C;
+    // amplitudes are inverted from what you would expect.
+    // hold(-1) puts the core into a positive M
+    [
+        // init S0; charge S1 positive, S2 *negative*
+        [C::hold(-amp0),    C::hold_low(),    C::hold_high()],
+        // let the cores settle; open S1 for receive
+        [C::release(-amp0), C::release_low(), C::hold_high()],
+        // write S0 -> S1.
+        [C::hold_high(),    C::float(),       C::hold_high()],
+        // prepare S2 for receive
+        [C::hold_high(),    C::float(),       C::release_high()],
+        // TODO: want to reset SLOWLY
+        [C::hold_high(),    C::float(),       C::hold_low()],
+        [C::hold_high(),    C::float(),       C::release_low()],
+        // write S1 -> S2
+        [C::hold_high(),    C::hold_high(),   C::float()],
+    ]
+}
+
 #[allow(unused)]
 fn drive_map_4stack_with_init4(amp0: f32, amp1: f32, amp2: f32, amp3: f32) -> [[ClockState; 4]; 3] {
     use ClockState as C;
@@ -4501,7 +4523,7 @@ fn main() {
         }
     }
 
-    if true {
+    if false {
         let p43xx = params_v2
             .with_clock_phase_duration(ps(1000))
             .with_clock_decay(ps(50))
@@ -4615,6 +4637,67 @@ fn main() {
             }
         }
     }
+    if true {
+        let p44xx = params_v2
+            .with_clock_phase_duration(ps(1000))
+            .with_clock_decay(ps(50))
+            .with_ctl_conductivity(5e2)
+            .with_coupling_conductivity(5e3)
+        ;
+        for init_set in [
+            &[
+                // establish the domain/range
+                 1.00,
+            ][..],
+            &[
+                -1.00,
+            ][..],
+            &[
+                 0.00,
+                 0.20,
+                -0.20,
+                 0.10,
+                -0.10,
+                 0.35,
+                -0.35,
+            ][..],
+        ] {
+            for (coupling_loops, s0_loops, s_major, cur_flt) in [
+                (5,  1, um(400),  3e9),   // M0: 16200, M1 -> 10000
+                (5,  1, um(400),  5e9),   // M0: 16700, M1 ->  7500
+                (5,  1, um(400),  8e9),   // M0: 16800, M1 ->  4100
+                (5,  1, um(400),  1e10),  // M0: 16800, M1 ->  3000
+                (5,  1, um(400),  2e10),  // M0: 16800, M1 ->   670
+                (5,  1, um(400),  4e10),  // M0: 16900, M1 ->  -500
+                (5,  1, um(400),  2e9),   // M0:  7500, M1 ->  7100  (too low init)
+            ] {
+                for &init_flt in init_set {
+                    // coupling loops (M0 -> M1) + (M1 -> M2) + control slots
+                    let slots_per_asym = 2*s0_loops;
+                    let net_slots = 2*slots_per_asym + 1;
+                    let mut params = p44xx
+                        .with_s_major(s_major)
+                        .with_coupling_loops(coupling_loops)
+                        .with_input_magnitude(cur_flt)
+                        // control loops
+                        .with_coupling(0, 0, 0, net_slots, CouplingMethod::Control)
+                        .with_coupling(1, 1, 0, net_slots, CouplingMethod::Control)
+                        .with_coupling(2, 2, 0, net_slots, CouplingMethod::Control)
+                    ;
+
+                    params = couple_asymmetric_inverter(&params, 0 /* sender core */, s0_loops, 1 /* slot offset */, net_slots);
+                    params = couple_asymmetric_inverter(&params, 1 /* sender core */, s0_loops, 1 + slots_per_asym /* slot offset */, net_slots);
+
+                    let name = asymmetric_inverter_name(&params, "44", 2*s0_loops + 1, init_flt);
+                    run_sim(
+                        &name,
+                        drive_map_3stack_with_init_44(init_flt),
+                        params,
+                    );
+                }
+            }
+        }
+    }
 }