diff --git a/crates/applications/stacked_cores/src/main.rs b/crates/applications/stacked_cores/src/main.rs index 3408a94..dd511c5 100644 --- a/crates/applications/stacked_cores/src/main.rs +++ b/crates/applications/stacked_cores/src/main.rs @@ -239,6 +239,26 @@ fn drive_map_3stack() -> [[ClockState; 3]; 6] { ] } +#[allow(unused)] +fn drive_map_3stack_and_rev() -> [[ClockState; 3]; 6] { + use ClockState::*; + [ + // charge S1 to '1', S0/S2 to '0' + [HoldLow, HoldHigh, HoldLow ], + // let the cores settle + [ReleaseLow, ReleaseHigh,ReleaseLow], + // write S1 -> S0/S2. S0/S2 should be copied to 1 + [Float, HoldLow, Float ], + + // open S1 for write + [Float, ReleaseLow, Float ], + // write {S0,S2} -> S1 + [HoldLow, Float, HoldLow ], + // let settle + [ReleaseLow, Float, ReleaseLow ], + ] +} + #[allow(unused)] fn drive_map_3stack_one_sided() -> [[ClockState; 3]; 6] { use ClockState::*; @@ -299,6 +319,42 @@ fn drive_map_5stack_one_sided_inv() -> [[ClockState; 5]; 6] { ] } +#[allow(unused)] +fn drive_map_nstack_one_sided_inv() -> [[ClockState; C]; 6] { + use ClockState::*; + + let mut clocks = [[Float; C]; 6]; + clocks[0][0] = HoldHigh; // charge S0 high + clocks[1][0] = ReleaseHigh; // let settle + clocks[2][0] = HoldLow; // write S0 -> S1, {S2, ...} + clocks[3][0] = HoldLow; // charge S0 low + clocks[4][0] = ReleaseLow; // let settle + clocks[5][0] = HoldLow; // write S0 -> S1, {S2, ...} + + for c in 1..C { + clocks[0][c] = match c % 2 { // charge to base state + 1 => HoldLow, + _ => ReleaseLow, + }; + clocks[1][c] = match c % 2 { // let settle + 1 => ReleaseLow, + _ => ReleaseHigh, + }; + clocks[2][c] = Float; // accept the active transfer + clocks[3][c] = match c % 2 { // charge to base state + 1 => HoldLow, + _ => HoldHigh, + }; + clocks[4][c] = match c % 2 { // let settle + 1 => ReleaseLow, + _ => ReleaseHigh, + }; + clocks[5][c] = Float; // accept the noop transfer + } + + clocks +} + fn main() { coremem::init_logging(); // coremem::init_debug(); @@ -580,7 +636,7 @@ fn main() { p6xx.with_coupling_loops(20), ); } - if true { + if false { let p7xx = params .with_clock_phase_duration(ps(1000)) .with_clock_decay(ps(50)) @@ -635,6 +691,127 @@ fn main() { p7xx.with_coupling_loops(20), ); } + if false { + let p8xx = params + .with_clock_phase_duration(ps(1000)) + .with_clock_decay(ps(50)) + .with_input_magnitude(8e10) + .with_ctl_conductivity(5e2) + .with_coupling_conductivity(5e3) + .with_s_major(um(400)) + .with_coupling_loops(16) + ; + run_sim( + "803-3core", + drive_map_nstack_one_sided_inv::<3>(), + p8xx, + ); + run_sim( + "805-5core", + drive_map_nstack_one_sided_inv::<5>(), + p8xx, + ); + run_sim( + "807-7core", + drive_map_nstack_one_sided_inv::<7>(), + p8xx, + ); + run_sim( + "809-9core", + drive_map_nstack_one_sided_inv::<9>(), + p8xx, + ); + run_sim( + "811-11core", + drive_map_nstack_one_sided_inv::<11>(), + p8xx, + ); + run_sim( + "813-13core", + drive_map_nstack_one_sided_inv::<13>(), + p8xx, + ); + run_sim( + "815-15core", + drive_map_nstack_one_sided_inv::<15>(), + p8xx, + ); + run_sim( + "817-17core", + drive_map_nstack_one_sided_inv::<17>(), + p8xx, + ); + run_sim( + "819-19core", + drive_map_nstack_one_sided_inv::<19>(), + p8xx, + ); + run_sim( + "820-20core", + drive_map_nstack_one_sided_inv::<20>(), + p8xx, + ); + run_sim( + "821-21core", + drive_map_nstack_one_sided_inv::<21>(), + p8xx, + ); + } + if true { + let p9xx = params + .with_clock_phase_duration(ps(1000)) + .with_clock_decay(ps(50)) + .with_input_magnitude(8e10) + .with_ctl_conductivity(5e2) + .with_coupling_conductivity(5e3) + .with_s_major(um(400)) + ; + run_sim( + "912-12loops", + drive_map_3stack_and_rev(), + p9xx.with_coupling_loops(12), + ); + run_sim( + "916-16loops", + drive_map_3stack_and_rev(), + p9xx.with_coupling_loops(16), + ); + run_sim( + "908-8loops", + drive_map_3stack_and_rev(), + p9xx.with_coupling_loops(8), + ); + run_sim( + "910-10loops", + drive_map_3stack_and_rev(), + p9xx.with_coupling_loops(10), + ); + run_sim( + "920-20loops", + drive_map_3stack_and_rev(), + p9xx.with_coupling_loops(20), + ); + run_sim( + "906-6loops", + drive_map_3stack_and_rev(), + p9xx.with_coupling_loops(6), + ); + run_sim( + "901-1loops", + drive_map_3stack_and_rev(), + p9xx.with_coupling_loops(1), + ); + run_sim( + "902-2loops", + drive_map_3stack_and_rev(), + p9xx.with_coupling_loops(2), + ); + run_sim( + "904-4loops", + drive_map_3stack_and_rev(), + p9xx.with_coupling_loops(4), + ); + } // run_sim( // "76-2ns-100ps-1e10A-1e3pctl-1e4pcpl-4loops", // drive_map_isolated_inv(), @@ -770,7 +947,7 @@ fn run_sim( let prefix = format!("out/applications/stacked_cores/{}/", name); let _ = std::fs::create_dir_all(&prefix); driver.add_state_file(&*format!("{}state.bc", prefix), 25600); - driver.add_serializer_renderer(&*format!("{}frame-", prefix), 6400, Some(12800)); + // driver.add_serializer_renderer(&*format!("{}frame-", prefix), 6400, Some(12800)); // driver.add_csv_renderer(&*format!("{}meas-detailed.csv", prefix), 100, None); driver.add_csv_renderer(&*format!("{}meas.csv", prefix), 1600, None); driver.add_csv_renderer(&*format!("{}meas-sparse.csv", prefix), 12800, None); diff --git a/crates/post/scripts/stacked_cores_9xx.py b/crates/post/scripts/stacked_cores_9xx.py new file mode 100755 index 0000000..f913e63 --- /dev/null +++ b/crates/post/scripts/stacked_cores_9xx.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +""" +invoke with the path to a meas.csv file for the stacked_core 8xx demos +to extract higher-level info from them. +""" +import sys + +from stacked_cores import load_csv, labeled_rows, last_row_before_t, extract_m + +def extract_9xx(path: str): + header, raw_rows = load_csv(path) + rows = labeled_rows(header, raw_rows) + + tx_start = last_row_before_t(rows, 2e-9) + tx_end = last_row_before_t(rows, 4e-9) + rev_start = last_row_before_t(rows, 4e-9) + rev_end = last_row_before_t(rows, 6e-9) + + m_tx_start = extract_m(tx_start) + m_tx_end = extract_m(tx_end) + m_rev_start = extract_m(rev_start) + m_rev_end = extract_m(rev_end) + + m1_switch = abs(m_tx_end[1] - m_tx_start[1]) + m1_rev_switch = abs(m_rev_end[1] - m_rev_start[1]) + + m_tx_switch_arr = [round(abs(m_tx_end[i] - m_tx_start[i])) for i in [0, 2]] + m_tx_switch = sum(m_tx_switch_arr) + m_rev_switch_arr = [round(abs(m_rev_end[i] - m_rev_start[i])) for i in [0, 2]] + m_rev_switch = sum(m_rev_switch_arr) + + ratio_tx_switch = m_tx_switch / m1_switch + ratio_roundtrip = m1_rev_switch / m1_switch + + print(f'm1 tx: {m1_switch} ({m_tx_start[1]} -> {m_tx_end[1]})') + print(f'm1 rev: {m1_rev_switch} ({m_rev_start[1]} -> {m_rev_end[1]})') + print('') + print(f'm(tx): {m_tx_start}') + print(f' -> {m_tx_end}') + print('') + print(f'm(rev): {m_rev_start}') + print(f' -> {m_rev_end}') + print('') + print(f'tx/m1: {ratio_tx_switch:.3}') + print(f'rev/m1: {ratio_roundtrip:.3}') + +if __name__ == '__main__': + extract_9xx(sys.argv[1])