df57721f9a
Convert IBT selftest to asm to fix objtool warning -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEV76QKkVc4xCGURexaDWVMHDJkrAFAmTv1QQACgkQaDWVMHDJ krAUwhAAn6TOwHJK8BSkHeiQhON1nrlP3c5cv0AyZ2NP8RYDrZrSZvhpYBJ6wgKC Cx5CGq5nn9twYsYS3KsktLKDfR3lRdsQ7K9qtyFtYiaeaVKo+7gEKl/K+klwai8/ gninQWHk0zmSCja8Vi77q52WOMkQKapT8+vaON9EVDO8dVEi+CvhAIfPwMafuiwO Rk4X86SzoZu9FP79LcCg9XyGC/XbM2OG9eNUTSCKT40qTTKm5y4gix687NvAlaHR ko5MTsdl0Wfp6Qk0ohT74LnoA2c1g/FluvZIM33ci/2rFpkf9Hw7ip3lUXqn6CPx rKiZ+pVRc0xikVWkraMfIGMJfUd2rhelp8OyoozD7DB7UZw40Q4RW4N5tgq9Fhe9 MQs3p1v9N8xHdRKl365UcOczUxNAmv4u0nV5gY/4FMC6VjldCl2V9fmqYXyzFS4/ Ogg4FSd7c2JyGFKPs+5uXyi+RY2qOX4+nzHOoKD7SY616IYqtgKoz5usxETLwZ6s VtJOmJL0h//z0A7tBliB0zd+SQ5UQQBDC2XouQH2fNX2isJMn0UDmWJGjaHgK6Hh 8jVp6LNqf+CEQS387UxckOyj7fu438hDky1Ggaw4YqowEOhQeqLVO4++x+HITrbp AupXfbJw9h9cMN63Yc0gVxXQ9IMZ+M7UxLtZ3Cd8/PVztNy/clA= =3UUm -----END PGP SIGNATURE----- Merge tag 'x86_shstk_for_6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 shadow stack support from Dave Hansen: "This is the long awaited x86 shadow stack support, part of Intel's Control-flow Enforcement Technology (CET). CET consists of two related security features: shadow stacks and indirect branch tracking. This series implements just the shadow stack part of this feature, and just for userspace. The main use case for shadow stack is providing protection against return oriented programming attacks. It works by maintaining a secondary (shadow) stack using a special memory type that has protections against modification. When executing a CALL instruction, the processor pushes the return address to both the normal stack and to the special permission shadow stack. Upon RET, the processor pops the shadow stack copy and compares it to the normal stack copy. For more information, refer to the links below for the earlier versions of this patch set" Link: https://lore.kernel.org/lkml/20220130211838.8382-1-rick.p.edgecombe@intel.com/ Link: https://lore.kernel.org/lkml/20230613001108.3040476-1-rick.p.edgecombe@intel.com/ * tag 'x86_shstk_for_6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (47 commits) x86/shstk: Change order of __user in type x86/ibt: Convert IBT selftest to asm x86/shstk: Don't retry vm_munmap() on -EINTR x86/kbuild: Fix Documentation/ reference x86/shstk: Move arch detail comment out of core mm x86/shstk: Add ARCH_SHSTK_STATUS x86/shstk: Add ARCH_SHSTK_UNLOCK x86: Add PTRACE interface for shadow stack selftests/x86: Add shadow stack test x86/cpufeatures: Enable CET CR4 bit for shadow stack x86/shstk: Wire in shadow stack interface x86: Expose thread features in /proc/$PID/status x86/shstk: Support WRSS for userspace x86/shstk: Introduce map_shadow_stack syscall x86/shstk: Check that signal frame is shadow stack mem x86/shstk: Check that SSP is aligned on sigreturn x86/shstk: Handle signals for shadow stack x86/shstk: Introduce routines modifying shstk x86/shstk: Handle thread shadow stack x86/shstk: Add user-mode shadow stack support ...
519 lines
17 KiB
C
519 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _PARISC_PGTABLE_H
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#define _PARISC_PGTABLE_H
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#include <asm/page.h>
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#if CONFIG_PGTABLE_LEVELS == 3
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#include <asm-generic/pgtable-nopud.h>
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#elif CONFIG_PGTABLE_LEVELS == 2
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#include <asm-generic/pgtable-nopmd.h>
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#endif
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#include <asm/fixmap.h>
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#ifndef __ASSEMBLY__
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/*
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* we simulate an x86-style page table for the linux mm code
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*/
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#include <linux/bitops.h>
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#include <linux/spinlock.h>
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#include <linux/mm_types.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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/* This is for the serialization of PxTLB broadcasts. At least on the N class
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* systems, only one PxTLB inter processor broadcast can be active at any one
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* time on the Merced bus. */
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extern spinlock_t pa_tlb_flush_lock;
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#if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
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extern int pa_serialize_tlb_flushes;
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#else
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#define pa_serialize_tlb_flushes (0)
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#endif
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#define purge_tlb_start(flags) do { \
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if (pa_serialize_tlb_flushes) \
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spin_lock_irqsave(&pa_tlb_flush_lock, flags); \
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else \
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local_irq_save(flags); \
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} while (0)
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#define purge_tlb_end(flags) do { \
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if (pa_serialize_tlb_flushes) \
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spin_unlock_irqrestore(&pa_tlb_flush_lock, flags); \
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else \
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local_irq_restore(flags); \
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} while (0)
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/* Purge data and instruction TLB entries. The TLB purge instructions
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* are slow on SMP machines since the purge must be broadcast to all CPUs.
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*/
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static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr)
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{
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unsigned long flags;
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purge_tlb_start(flags);
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mtsp(mm->context.space_id, SR_TEMP1);
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pdtlb(SR_TEMP1, addr);
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pitlb(SR_TEMP1, addr);
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purge_tlb_end(flags);
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}
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extern void __update_cache(pte_t pte);
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/* Certain architectures need to do special things when PTEs
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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#define set_pte(pteptr, pteval) \
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do { \
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*(pteptr) = (pteval); \
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mb(); \
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} while(0)
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#endif /* !__ASSEMBLY__ */
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
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#if CONFIG_PGTABLE_LEVELS == 3
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e))
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#endif
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e))
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/* This is the size of the initially mapped kernel memory */
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#if defined(CONFIG_64BIT)
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#define KERNEL_INITIAL_ORDER 26 /* 1<<26 = 64MB */
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#else
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#define KERNEL_INITIAL_ORDER 25 /* 1<<25 = 32MB */
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#endif
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#define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
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#if CONFIG_PGTABLE_LEVELS == 3
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#define PMD_TABLE_ORDER 1
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#define PGD_TABLE_ORDER 0
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#else
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#define PGD_TABLE_ORDER 1
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#endif
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/* Definitions for 3rd level (we use PLD here for Page Lower directory
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* because PTE_SHIFT is used lower down to mean shift that has to be
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* done to get usable bits out of the PTE) */
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#define PLD_SHIFT PAGE_SHIFT
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#define PLD_SIZE PAGE_SIZE
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#define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY)
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#define PTRS_PER_PTE (1UL << BITS_PER_PTE)
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/* Definitions for 2nd level */
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#if CONFIG_PGTABLE_LEVELS == 3
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#define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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#define BITS_PER_PMD (PAGE_SHIFT + PMD_TABLE_ORDER - BITS_PER_PMD_ENTRY)
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#define PTRS_PER_PMD (1UL << BITS_PER_PMD)
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#else
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#define BITS_PER_PMD 0
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#endif
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/* Definitions for 1st level */
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#define PGDIR_SHIFT (PLD_SHIFT + BITS_PER_PTE + BITS_PER_PMD)
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#if (PGDIR_SHIFT + PAGE_SHIFT + PGD_TABLE_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG
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#define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT)
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#else
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#define BITS_PER_PGD (PAGE_SHIFT + PGD_TABLE_ORDER - BITS_PER_PGD_ENTRY)
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#endif
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define PTRS_PER_PGD (1UL << BITS_PER_PGD)
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#define USER_PTRS_PER_PGD PTRS_PER_PGD
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#ifdef CONFIG_64BIT
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#define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
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#define MAX_ADDRESS (1UL << MAX_ADDRBITS)
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#define SPACEID_SHIFT (MAX_ADDRBITS - 32)
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#else
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#define MAX_ADDRBITS (BITS_PER_LONG)
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#define MAX_ADDRESS (1ULL << MAX_ADDRBITS)
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#define SPACEID_SHIFT 0
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#endif
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/* This calculates the number of initial pages we need for the initial
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* page tables */
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#if (KERNEL_INITIAL_ORDER) >= (PLD_SHIFT + BITS_PER_PTE)
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# define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PLD_SHIFT - BITS_PER_PTE))
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#else
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# define PT_INITIAL (1) /* all initial PTEs fit into one page */
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#endif
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/*
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* pgd entries used up by user/kernel:
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*/
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/* NB: The tlb miss handlers make certain assumptions about the order */
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/* of the following bits, so be careful (One example, bits 25-31 */
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/* are moved together in one instruction). */
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#define _PAGE_READ_BIT 31 /* (0x001) read access allowed */
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#define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */
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#define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */
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#define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */
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#define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */
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#define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */
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#define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */
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#define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */
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#define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */
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#define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */
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#define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */
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#define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */
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#ifdef CONFIG_HUGETLB_PAGE
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#define _PAGE_SPECIAL_BIT _PAGE_DMB_BIT /* DMB feature is currently unused */
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#else
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#define _PAGE_SPECIAL_BIT _PAGE_HPAGE_BIT /* use unused HUGE PAGE bit */
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#endif
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/* N.B. The bits are defined in terms of a 32 bit word above, so the */
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/* following macro is ok for both 32 and 64 bit. */
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#define xlate_pabit(x) (31 - x)
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/* this defines the shift to the usable bits in the PTE it is set so
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* that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set
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* to zero */
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#define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
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/* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
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#define PFN_PTE_SHIFT 12
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#define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT))
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#define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT))
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#define _PAGE_RW (_PAGE_READ | _PAGE_WRITE)
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#define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT))
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#define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT))
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#define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT))
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#define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT))
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#define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT))
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#define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT))
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#define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT))
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#define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT))
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#define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT))
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#define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT))
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#define _PAGE_SPECIAL (1 << xlate_pabit(_PAGE_SPECIAL_BIT))
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#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_SPECIAL)
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#define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)
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#define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC)
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#define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE)
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#define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE)
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/* We borrow bit 23 to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE _PAGE_ACCESSED
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/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
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* are page-aligned, we don't care about the PAGE_OFFSET bits, except
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* for a few meta-information bits, so we shift the address to be
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* able to effectively address 40/42/44-bits of physical address space
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* depending on 4k/16k/64k PAGE_SIZE */
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#define _PxD_PRESENT_BIT 31
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#define _PxD_VALID_BIT 30
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#define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT))
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#define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
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#define PxD_FLAG_MASK (0xf)
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#define PxD_FLAG_SHIFT (4)
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#define PxD_VALUE_SHIFT (PFN_PTE_SHIFT-PxD_FLAG_SHIFT)
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#ifndef __ASSEMBLY__
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#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER)
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE)
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/* Others seem to make this executable, I don't know if that's correct
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or not. The stack is mapped this way though so this is necessary
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in the short term - dhd@linuxcare.com, 2000-08-08 */
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ)
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#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE)
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#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC)
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#define PAGE_COPY PAGE_EXECREAD
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#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
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#define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC)
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#define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX)
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#define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO)
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#define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
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#define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_GATEWAY| _PAGE_READ)
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/*
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* We could have an execute only page using "gateway - promote to priv
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* level 3", but that is kind of silly. So, the way things are defined
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* now, we must always have read permission for pages with execute
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* permission. For the fun of it we'll go ahead and support write only
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* pages.
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*/
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/*xwr*/
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extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
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/* initial page tables for 0-8MB for kernel */
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extern pte_t pg0[];
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/* zero page used for uninitialized stuff */
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extern unsigned long *empty_zero_page;
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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#define pte_none(x) (pte_val(x) == 0)
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#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
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#define pte_user(x) (pte_val(x) & _PAGE_USER)
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#define pte_clear(mm, addr, xp) set_pte(xp, __pte(0))
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#define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK)
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#define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
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#define pud_flag(x) (pud_val(x) & PxD_FLAG_MASK)
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#define pud_address(x) ((unsigned long)(pud_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
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#define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
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#define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
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#define pmd_none(x) (!pmd_val(x))
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#define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
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#define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
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static inline void pmd_clear(pmd_t *pmd) {
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set_pmd(pmd, __pmd(0));
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}
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#if CONFIG_PGTABLE_LEVELS == 3
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#define pud_pgtable(pud) ((pmd_t *) __va(pud_address(pud)))
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#define pud_page(pud) virt_to_page((void *)pud_pgtable(pud))
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/* For 64 bit we have three level tables */
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#define pud_none(x) (!pud_val(x))
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#define pud_bad(x) (!(pud_flag(x) & PxD_FLAG_VALID))
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#define pud_present(x) (pud_flag(x) & PxD_FLAG_PRESENT)
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static inline void pud_clear(pud_t *pud) {
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set_pud(pud, __pud(0));
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}
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#endif
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
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static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
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static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
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static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
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static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; }
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static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkwrite_novma(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; }
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static inline pte_t pte_mkspecial(pte_t pte) { pte_val(pte) |= _PAGE_SPECIAL; return pte; }
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/*
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* Huge pte definitions.
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*/
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#ifdef CONFIG_HUGETLB_PAGE
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#define pte_huge(pte) (pte_val(pte) & _PAGE_HUGE)
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#define pte_mkhuge(pte) (__pte(pte_val(pte) | \
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(parisc_requires_coherency() ? 0 : _PAGE_HUGE)))
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#else
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#define pte_huge(pte) (0)
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#define pte_mkhuge(pte) (pte)
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#endif
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define __mk_pte(addr,pgprot) \
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({ \
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pte_t __pte; \
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\
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pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
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\
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__pte; \
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})
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
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{
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pte_t pte;
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pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
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return pte;
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}
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
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/* Permanent address of a page. On parisc we don't have highmem. */
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#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
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#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
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static inline unsigned long pmd_page_vaddr(pmd_t pmd)
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{
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return ((unsigned long) __va(pmd_address(pmd)));
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}
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#define pmd_pfn(pmd) (pmd_address(pmd) >> PAGE_SHIFT)
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#define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd)))
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#define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
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/* Find an entry in the second-level page table.. */
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extern void paging_init (void);
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|
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static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, unsigned int nr)
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|
{
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if (pte_present(pte) && pte_user(pte))
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__update_cache(pte);
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for (;;) {
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*ptep = pte;
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purge_tlb_entries(mm, addr);
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if (--nr == 0)
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break;
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ptep++;
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pte_val(pte) += 1 << PFN_PTE_SHIFT;
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addr += PAGE_SIZE;
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|
}
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|
}
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|
#define set_ptes set_ptes
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|
|
|
/* Used for deferring calls to flush_dcache_page() */
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|
|
|
#define PG_dcache_dirty PG_arch_1
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|
|
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#define update_mmu_cache_range(vmf, vma, addr, ptep, nr) __update_cache(*ptep)
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#define update_mmu_cache(vma, addr, ptep) __update_cache(*ptep)
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|
|
|
/*
|
|
* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
|
|
* are !pte_none() && !pte_present().
|
|
*
|
|
* Format of swap PTEs (32bit):
|
|
*
|
|
* 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
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|
* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
|
|
* <---------------- offset -----------------> P E <ofs> < type ->
|
|
*
|
|
* E is the exclusive marker that is not stored in swap entries.
|
|
* _PAGE_PRESENT (P) must be 0.
|
|
*
|
|
* For the 64bit version, the offset is extended by 32bit.
|
|
*/
|
|
#define __swp_type(x) ((x).val & 0x1f)
|
|
#define __swp_offset(x) ( (((x).val >> 5) & 0x7) | \
|
|
(((x).val >> 10) << 3) )
|
|
#define __swp_entry(type, offset) ((swp_entry_t) { \
|
|
((type) & 0x1f) | \
|
|
((offset & 0x7) << 5) | \
|
|
((offset >> 3) << 10) })
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
|
|
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
|
|
|
|
static inline int pte_swp_exclusive(pte_t pte)
|
|
{
|
|
return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
|
|
}
|
|
|
|
static inline pte_t pte_swp_mkexclusive(pte_t pte)
|
|
{
|
|
pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
|
|
return pte;
|
|
}
|
|
|
|
static inline pte_t pte_swp_clear_exclusive(pte_t pte)
|
|
{
|
|
pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
|
|
return pte;
|
|
}
|
|
|
|
static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
|
|
{
|
|
pte_t pte;
|
|
|
|
if (!pte_young(*ptep))
|
|
return 0;
|
|
|
|
pte = *ptep;
|
|
if (!pte_young(pte)) {
|
|
return 0;
|
|
}
|
|
set_pte(ptep, pte_mkold(pte));
|
|
return 1;
|
|
}
|
|
|
|
struct mm_struct;
|
|
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
|
{
|
|
pte_t old_pte;
|
|
|
|
old_pte = *ptep;
|
|
set_pte(ptep, __pte(0));
|
|
|
|
return old_pte;
|
|
}
|
|
|
|
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
|
|
{
|
|
set_pte(ptep, pte_wrprotect(*ptep));
|
|
}
|
|
|
|
#define pte_same(A,B) (pte_val(A) == pte_val(B))
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
|
|
/* TLB page size encoding - see table 3-1 in parisc20.pdf */
|
|
#define _PAGE_SIZE_ENCODING_4K 0
|
|
#define _PAGE_SIZE_ENCODING_16K 1
|
|
#define _PAGE_SIZE_ENCODING_64K 2
|
|
#define _PAGE_SIZE_ENCODING_256K 3
|
|
#define _PAGE_SIZE_ENCODING_1M 4
|
|
#define _PAGE_SIZE_ENCODING_4M 5
|
|
#define _PAGE_SIZE_ENCODING_16M 6
|
|
#define _PAGE_SIZE_ENCODING_64M 7
|
|
|
|
#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
|
|
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
|
|
#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
|
|
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
|
|
#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
|
|
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
|
|
#endif
|
|
|
|
|
|
#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
|
|
|
|
/* We provide our own get_unmapped_area to provide cache coherency */
|
|
|
|
#define HAVE_ARCH_UNMAPPED_AREA
|
|
#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
|
|
|
|
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
|
|
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
|
|
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
|
|
#define __HAVE_ARCH_PTE_SAME
|
|
|
|
#endif /* _PARISC_PGTABLE_H */
|