From 9e6e16cb8b6d164502100bde200ef15054868ad5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
Date: Tue, 10 Mar 2020 06:04:32 +0100
Subject: [PATCH 135/463] clk: sunxi-ng: Don't use CPU PLL gating and CPUX
 reparenting to HOSC

It's not necessary when not using dividers on CPU PLL, and it's
causing cntvct jump backs on H3.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 21 ---------------------
 1 file changed, 21 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 23440072319e2..eed11bb2d6313 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -1029,20 +1029,6 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
 	.num_resets	= ARRAY_SIZE(sun50i_h5_ccu_resets),
 };
 
-static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
-	.common	= &pll_cpux_clk.common,
-	/* copy from pll_cpux_clk */
-	.enable	= BIT(31),
-	.lock	= BIT(28),
-};
-
-static struct ccu_mux_nb sun8i_h3_cpu_nb = {
-	.common		= &cpux_clk.common,
-	.cm		= &cpux_clk.mux,
-	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
-	.bypass_index	= 1, /* index of 24 MHz oscillator */
-};
-
 static int sun8i_h3_ccu_probe(struct platform_device *pdev)
 {
 	const struct sunxi_ccu_desc *desc;
@@ -1067,13 +1053,6 @@ static int sun8i_h3_ccu_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	/* Gate then ungate PLL CPU after any rate changes */
-	ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
-
-	/* Reparent CPU during PLL CPU rate changes */
-	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
-				  &sun8i_h3_cpu_nb);
-
 	return 0;
 }
 
-- 
2.46.0

