From 28a6c90922dc3b242f69806d284984cd0ba904b9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
Date: Tue, 20 Aug 2019 14:31:38 +0200
Subject: [PATCH 142/463] net: stmmac: sun8i: Add support for enabling a
 regulator for PHY I/O pins

Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
to the phy datasheet, both regulators need to be enabled at the same time.

Add support for the second optional regulator, "phy-io", to the glue
driver.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
 .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 20 ++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 49704e017a48b..08eeaf8d14bf0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -61,6 +61,8 @@ struct emac_variant {
 /* struct sunxi_priv_data - hold all sunxi private data
  * @ephy_clk:	reference to the optional EPHY clock for the internal PHY
  * @regulator_phy: reference to the optional regulator
+ * @regulator_phy_io: reference to the optional regulator for
+ *		PHY I/O pins
  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
  * @variant:	reference to the current board variant
  * @regmap:	regmap for using the syscon
@@ -71,6 +73,7 @@ struct emac_variant {
 struct sunxi_priv_data {
 	struct clk *ephy_clk;
 	struct regulator *regulator_phy;
+	struct regulator *regulator_phy_io;
 	struct reset_control *rst_ephy;
 	const struct emac_variant *variant;
 	struct regmap_field *regmap_field;
@@ -588,10 +591,16 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
 	struct sunxi_priv_data *gmac = priv;
 	int ret;
 
+	ret = regulator_enable(gmac->regulator_phy_io);
+	if (ret) {
+		dev_err(&pdev->dev, "Fail to enable PHY I/O regulator\n");
+		return ret;
+	}
+
 	ret = regulator_enable(gmac->regulator_phy);
 	if (ret) {
 		dev_err(&pdev->dev, "Fail to enable PHY regulator\n");
-		return ret;
+		goto err_disable_regulator_phy_io;
 	}
 
 	if (gmac->use_internal_phy) {
@@ -604,6 +613,8 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
 
 err_disable_regulator:
 	regulator_disable(gmac->regulator_phy);
+err_disable_regulator_phy_io:
+	regulator_disable(gmac->regulator_phy_io);
 
 	return ret;
 }
@@ -1051,6 +1062,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
 		sun8i_dwmac_unpower_internal_phy(gmac);
 
 	regulator_disable(gmac->regulator_phy);
+	regulator_disable(gmac->regulator_phy_io);
 }
 
 static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
@@ -1179,6 +1191,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
 		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy),
 				     "Failed to get PHY regulator\n");
 
+	/* Optional regulator for PHY I/O pins */
+	gmac->regulator_phy_io = devm_regulator_get(dev, "phy-io");
+	if (IS_ERR(gmac->regulator_phy_io))
+		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy_io),
+				     "Failed to get PHY I/O regulator\n");
+
 	/* The "GMAC clock control" register might be located in the
 	 * CCU address range (on the R40), or the system control address
 	 * range (on most other sun8i and later SoCs).
-- 
2.46.0

