From 82c0212dd87dec52a9f6098671283cdab381e5f4 Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megi@xff.cz>
Date: Mon, 29 Apr 2024 13:58:39 +0200
Subject: [PATCH 096/463] arm: xilinx: ebaz4205: Add test config for various PL
 peripherals

Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
 arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts | 74 ++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts
index aa47b907895ec..dd8faf272143c 100644
--- a/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts
+++ b/arch/arm/boot/dts/xilinx/zynq-ebaz4205.dts
@@ -26,6 +26,80 @@ chosen {
 	};
 };
 
+&amba {
+	// GIC interrupts 29-32
+	// cells: 0=spi/1=ppi    intno    1=low-to-high edge triggered  4=active high level-sensitive
+
+	serial@42c00000 {
+		compatible = "xlnx,xps-uartlite-1.00.a";
+		reg = <0x42c00000 0x10000>;
+		clocks = <&clkc CLK_FCLK0>;
+		clock-names = "s_axi_aclk";
+		interrupt-parent = <&intc>;
+		interrupts = <0 30 1>;
+		port-number = <0>;
+		current-speed = <115200>;
+		xlnx,data-bits = <8>;
+		xlnx,use-parity = <0>;
+	};
+
+	serial@42c10000 {
+		compatible = "xlnx,xps-uartlite-1.00.a";
+		reg = <0x42c10000 0x10000>;
+		clocks = <&clkc CLK_FCLK0>;
+		clock-names = "s_axi_aclk";
+		interrupt-parent = <&intc>;
+		interrupts = <0 32 1>;
+		port-number = <1>;
+		current-speed = <115200>;
+		xlnx,data-bits = <8>;
+		xlnx,use-parity = <0>;
+	};
+
+	i2c@41600000 {
+		compatible = "xlnx,axi-iic-2.1";
+		clocks = <&clkc CLK_FCLK0>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 29 4>;
+		reg = <0x41600000 0x10000>;
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		sensor@40 {
+			reg = <0x40>;
+			compatible = "meas,htu21";
+		};
+
+		sensor@77 {
+			reg = <0x77>;
+			compatible = "bosch,bmp180";
+		};
+	};
+
+	i2c@41610000 {
+		compatible = "xlnx,xps-iic-2.00.a";
+		clocks = <&clkc CLK_FCLK0>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 31 4>;
+		reg = <0x41610000 0x10000>;
+		#size-cells = <0>;
+		#address-cells = <1>;
+	};
+
+	gpio@41200000 {
+		compatible = "xlnx,xps-gpio-1.00.a";
+		reg = <0x41200000 0x10000>;
+		clocks = <&clkc CLK_FCLK0>;
+		#gpio-cells = <2>;
+		gpio-controller;
+		xlnx,all-inputs = <0x0>;
+		xlnx,all-outputs = <0x0>;
+		xlnx,dout-default = <0x0>;
+		xlnx,gpio-width = <4>;
+		xlnx,tri-default = <0xFFFFFFFF>;
+	};
+};
+
 &clkc {
 	ps-clk-frequency = <33333333>;
 	fclk-enable = <8>;
-- 
2.46.0

