From e704a1bc611918c68b1d5c4a334f61c879d8c728 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
Date: Mon, 14 Aug 2023 07:28:11 +0200
Subject: [PATCH 273/463] clk: sunxi-ng: sun50i-a64: Switch parent of MIPI-DSI
 to periph0(1x)

This makes video0(1x) clock less constrained, and improves compatibility
with external monitors on Pinephone when using both internal display
and HDMI output at once.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
 drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index b1e411f4ad577..1880dbcc39a7d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -942,6 +942,8 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
 	.bypass_index	= 1, /* index of 24 MHz oscillator */
 };
 
+#define CCU_MIPI_DSI_CLK 0x168
+
 static int sun50i_a64_ccu_probe(struct platform_device *pdev)
 {
 	void __iomem *reg;
@@ -958,9 +960,15 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
 	writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
 
 	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
-	if (ret)
+	if (ret) {
 		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
 
+		/* Set MIPI-DSI clock parent to periph0(1x), so that video0(1x) is free to change. */
+		val = readl(reg + CCU_MIPI_DSI_CLK);
+		val &= 0x30f;
+		val |= (2 << 8) | ((4 - 1) << 0); /* M-1 */
+		writel(val, reg + CCU_MIPI_DSI_CLK);
+	}
 	/* Set PLL MIPI as parent for TCON0 */
 	val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
 	val &= ~GENMASK(26, 24);
-- 
2.46.0

