From 541b664e6de65bdf068f2211203dabfdc1fb963e Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 28 May 2022 18:01:42 -0500
Subject: [PATCH 218/463] clk: sunxi-ng: Mark TWD clocks as critical

Secure world firmware depends on this clock, so it cannot be disabled.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 2 +-
 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c   | 2 +-
 drivers/clk/sunxi-ng/ccu-sun8i-r.c       | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
index 2c791761a6467..bc59191e82912 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
@@ -91,7 +91,7 @@ static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,
 			   0x11c, BIT(0), 0);
 
 static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,
-			   0x12c, BIT(0), 0);
+			   0x12c, BIT(0), CLK_IS_CRITICAL);
 
 static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k",
 						       "iosc" };
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index c728158411116..2a8b998cf09cd 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -85,7 +85,7 @@ static struct ccu_div r_apb2_clk = {
 static SUNXI_CCU_GATE(r_apb1_timer_clk,	"r-apb1-timer",	"r-apb1",
 		      0x11c, BIT(0), 0);
 static SUNXI_CCU_GATE(r_apb1_twd_clk,	"r-apb1-twd",	"r-apb1",
-		      0x12c, BIT(0), 0);
+		      0x12c, BIT(0), CLK_IS_CRITICAL);
 static SUNXI_CCU_GATE(r_apb1_pwm_clk,	"r-apb1-pwm",	"r-apb1",
 		      0x13c, BIT(0), 0);
 static SUNXI_CCU_GATE(r_apb2_uart_clk,	"r-apb2-uart",	"r-apb2",
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
index da6569334d68b..4edb2c8c57bcd 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -73,7 +73,7 @@ static SUNXI_CCU_GATE_HWS(apb0_uart_clk,	"apb0-uart",
 static SUNXI_CCU_GATE_HWS(apb0_i2c_clk,		"apb0-i2c",
 			  apb0_gate_parent, 0x28, BIT(6), 0);
 static SUNXI_CCU_GATE_HWS(apb0_twd_clk,		"apb0-twd",
-			  apb0_gate_parent, 0x28, BIT(7), 0);
+			  apb0_gate_parent, 0x28, BIT(7), CLK_IS_CRITICAL);
 
 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
-- 
2.46.0

