From 251447310bba294b53f2feef9a2c0187611977da Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megi@xff.cz>
Date: Thu, 18 Jul 2024 17:38:33 +0200
Subject: [PATCH 452/463] ARM: dts: rockchip: Add Rockchip RV1106 SoC support

This is a slightly modified version of RV1103 with more RAM and GPIO/RTC.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
 arch/arm/boot/dts/rockchip/rv1106.dtsi | 92 ++++++++++++++++++++++++++
 1 file changed, 92 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/rv1106.dtsi

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
new file mode 100644
index 0000000000000..2b1165940f4bd
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rv1103.dtsi"
+
+/ {
+	compatible = "rockchip,rv1106";
+};
+
+&cpu0_opp_table {
+	opp-1200000000 {
+		opp-hz = /bits/ 64 <1200000000>;
+		opp-microvolt = <850000 850000 1000000>;
+		clock-latency-ns = <40000>;
+	};
+	opp-1296000000 {
+		opp-hz = /bits/ 64 <1296000000>;
+		opp-microvolt = <875000 850000 1000000>;
+		clock-latency-ns = <40000>;
+	};
+/*
+	opp-1416000000 {
+		opp-hz = /bits/ 64 <1416000000>;
+		opp-microvolt = <925000 850000 1000000>;
+		clock-latency-ns = <40000>;
+	};
+	opp-1512000000 {
+		opp-hz = /bits/ 64 <1512000000>;
+		opp-microvolt = <975000 850000 1000000>;
+		clock-latency-ns = <40000>;
+	};
+	opp-1608000000 {
+		opp-hz = /bits/ 64 <1608000000>;
+		opp-microvolt = <1000000 850000 1000000>;
+		clock-latency-ns = <40000>;
+	};
+*/
+};
+
+&cru {
+	assigned-clocks =
+		<&cru PLL_GPLL>, <&cru PLL_CPLL>,
+		<&cru ARMCLK>,
+		<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
+		<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
+		<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
+		<&cru HCLK_PMU_ROOT>;
+	assigned-clock-rates =
+		<1188000000>, <1000000000>,
+		<1104000000>,
+		<400000000>, <200000000>,
+		<100000000>, <300000000>,
+		<100000000>, <100000000>,
+		<200000000>;
+};
+
+&pinctrl {
+	gpio2: gpio@ff540000 {
+		compatible = "rockchip,gpio-bank";
+		reg = <0xff540000 0x100>;
+		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-ranges = <&pinctrl 0 64 32>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+};
+
+&u2phy_otg {
+	/delete-property/ rockchip,vbus-always-on;
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3m0_xfer>;
+};
+
+&i2c4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3m0_xfer>;
+};
+
+/*
+&acodec {
+	compatible = "rockchip,rv1106-codec";
+};
+*/
-- 
2.46.0

