From e373fd4c94ad119d6d75400524f1f10fbaf745ee Mon Sep 17 00:00:00 2001
From: Ondrej Jirman <megi@xff.cz>
Date: Fri, 21 Jun 2024 01:38:50 +0200
Subject: [PATCH 450/463] ARM: dts: rockchip: rv1103: Add Rockchip RV1103 SoC
 support

This SoC features 1 Cortex A53 core and a few video processing oriented
peripherals.

Signed-off-by: Ondrej Jirman <megi@xff.cz>
---
 arch/arm/boot/dts/rockchip/rv1103.dtsi | 2526 ++++++++++++++++++++++++
 1 file changed, 2526 insertions(+)
 create mode 100644 arch/arm/boot/dts/rockchip/rv1103.dtsi

diff --git a/arch/arm/boot/dts/rockchip/rv1103.dtsi b/arch/arm/boot/dts/rockchip/rv1103.dtsi
new file mode 100644
index 0000000000000..03b25e50b82c2
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip/rv1103.dtsi
@@ -0,0 +1,2526 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/rv1106-cru.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	compatible = "rockchip,rv1103";
+
+	interrupt-parent = <&gic>;
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		mmc0 = &emmc;
+		mmc1 = &sdmmc;
+		mmc2 = &sdio;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+		serial5 = &uart5;
+		spi0 = &spi0;
+		spi1 = &spi1;
+		spi2 = &sfc;
+	};
+
+	xin24m: oscillator {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "xin24m";
+		#clock-cells = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a7";
+			reg = <0x0>;
+			clock-latency = <40000>;
+			clocks = <&cru ARMCLK>;
+			#cooling-cells = <2>; /* min followed by max */
+			operating-points-v2 = <&cpu0_opp_table>;
+		};
+	};
+
+	cpu0_opp_table: cpu0-opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		/*XXX
+		nvmem-cells = <&cpu_leakage>;
+		nvmem-cell-names = "leakage";
+		rockchip,grf = <&grf>;
+		*/
+
+		opp-408000000 {
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <850000 850000 1000000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <850000 850000 1000000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <850000 850000 1000000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
+		};
+		opp-1104000000 {
+			opp-hz = /bits/ 64 <1104000000>;
+			opp-microvolt = <850000 850000 1000000>;
+			clock-latency-ns = <40000>;
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>;
+	};
+
+/*
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+*/
+
+	thermal_zones: thermal-zones {
+		soc_thermal: soc-thermal {
+			polling-delay-passive = <20>;
+			polling-delay = <1000>;
+			sustainable-power = <2100>;
+			thermal-sensors = <&tsadc 0>;
+
+			trips {
+				threshold: trip-point-0 {
+					temperature = <75000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				target: trip-point-1 {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+
+				soc_crit: soc-crit {
+					temperature = <115000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+		clock-frequency = <24000000>;
+	};
+
+	grf: syscon@ff000000 {
+		compatible = "rockchip,rv1106-grf", "syscon", "simple-mfd";
+		reg = <0xff000000 0x68000>;
+
+		grf_cru: grf-clock-controller {
+			compatible = "rockchip,rv1106-grf-cru";
+			#clock-cells = <1>;
+		};
+
+		reboot_mode: reboot-mode {
+			compatible = "syscon-reboot-mode";
+			offset = <0x20200>;
+			mode-recovery = <0xb0010002>;
+		};
+
+		rknpor_powergood: rknpor-powergood {
+			compatible = "rockchip,rv1106-npor-powergood";
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	rtc: rtc@ff1c0000 {
+		compatible = "rockchip,rv1106-rtc";
+		reg = <0xff1c0000 0x1000>;
+		rockchip,grf = <&grf>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_VI_RTC_PHY>, <&cru PCLK_VI_RTC_TEST>;
+		clock-names = "pclk_phy", "pclk_test";
+		assigned-clocks = <&cru PCLK_VI_RTC_PHY>;
+		assigned-clock-rates = <24000000>;
+		status = "disabled";
+	};
+
+	gic: interrupt-controller@ff1f0000 {
+		compatible = "arm,gic-400";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+
+		reg = <0xff1f1000 0x1000>,
+		      <0xff1f2000 0x2000>,
+		      <0xff1f4000 0x2000>,
+		      <0xff1f6000 0x2000>;
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	arm-debug@ff200000 {
+		compatible = "rockchip,debug";
+		reg = <0xff200000 0x1000>;
+	};
+
+	pmu: power-management@ff300000 {
+		compatible = "rockchip,rv1106-pmu", "syscon";
+		reg = <0xff300000 0x1000>;
+	};
+
+	i2c0: i2c@ff310000 {
+		compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+		reg = <0xff310000 0x1000>;
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+		clock-names = "i2c", "pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c0m0_xfer>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@ff320000 {
+		compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+		reg = <0xff320000 0x1000>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+		clock-names = "i2c", "pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c1m0_xfer>;
+		status = "disabled";
+	};
+
+	dsm: codec-digital@ff340000 {
+		compatible = "rockchip,rv1106-codec-digital", "rockchip,codec-digital-v1";
+		reg = <0xff340000 0x1000>;
+		clocks = <&cru MCLK_DSM>, <&cru PCLK_DSM>;
+		clock-names = "dac", "pclk";
+		resets = <&cru SRST_M_DSM>;
+		reset-names = "reset" ;
+		rockchip,grf = <&grf>;
+		rockchip,pwm-output-mode;
+		#sound-dai-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&dsmaudio_pins>;
+		status = "disabled";
+	};
+
+	pwm0: pwm@ff350000 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff350000 0x10>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm0m0_pins>;
+		clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm1: pwm@ff350010 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff350010 0x10>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm1m0_pins>;
+		clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm2: pwm@ff350020 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff350020 0x10>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm2m0_pins>;
+		clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm3: pwm@ff350030 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff350030 0x10>;
+		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm3m0_pins>;
+		clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm4: pwm@ff360000 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff360000 0x10>;
+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm4m0_pins>;
+		clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm5: pwm@ff360010 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff360010 0x10>;
+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm5m0_pins>;
+		clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm6: pwm@ff360020 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff360020 0x10>;
+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm6m0_pins>;
+		clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm7: pwm@ff360030 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff360030 0x10>;
+		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm7m0_pins>;
+		clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	//tx-dma-size = <256>;
+	//rx-dma-size = <128>;
+
+	gmac: ethernet@ffa80000 {
+		compatible = "rockchip,rv1106-gmac";
+		reg = <0xffa80000 0x10000>;
+		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "macirq", "eth_wake_irq";
+		clocks = <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>,
+			 <&cru ACLK_MAC>, <&cru PCLK_MAC>;
+		clock-names = "stmmaceth", "clk_mac_ref",
+			      "aclk_mac", "pclk_mac";
+		resets = <&cru SRST_A_MAC>;
+		reset-names = "stmmaceth";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		nvmem-cells = <&macphy_bgs>;
+		nvmem-cell-names = "bgs";
+
+		phy-mode = "rmii";
+		clock_in_out = "input";
+		phy-handle = <&rmii_phy>;
+
+		snps,axi-config = <&stmmac_axi_setup>;
+		snps,mtl-rx-config = <&mtl_rx_setup>;
+		snps,mtl-tx-config = <&mtl_tx_setup>;
+		snps,mixed-burst;
+		snps,tso;
+		/* FLOW_OFF: 0, FLOW_RX: 1, FLOW_TX: 2, FLOW_AUTO: 3 */
+		//snps,flow-ctrl = <0>;
+
+		mdio: mdio {
+			compatible = "snps,dwmac-mdio";
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+
+			rmii_phy: ethernet-phy@2 {
+				compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22";
+				reg = <2>;
+				clocks = <&cru CLK_MACPHY>;
+				resets = <&cru SRST_MACPHY>;
+				nvmem-cells = <&macphy_txlevel>;
+				nvmem-cell-names = "txlevel";
+				phy-is-integrated;
+			};
+		};
+
+		stmmac_axi_setup: stmmac-axi-config {
+			snps,wr_osr_lmt = <4>;
+			snps,rd_osr_lmt = <8>;
+			snps,blen = <0 0 0 0 16 8 4>;
+		};
+
+		mtl_rx_setup: rx-queues-config {
+			snps,rx-queues-to-use = <1>;
+			queue0 {
+				status = "okay";
+			};
+		};
+
+		mtl_tx_setup: tx-queues-config {
+			snps,tx-queues-to-use = <1>;
+			queue0 {
+				status = "okay";
+			};
+		};
+	};
+
+	pmu_mailbox: mailbox@ff378000 {
+		compatible = "rockchip,rv1106-mailbox",
+			     "rockchip,rk3368-mailbox";
+		reg = <0xff378000 0x200>;
+		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_PMU_MAILBOX>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	pmuioc: syscon@ff388000 {
+		compatible = "rockchip,rv1106-pmuioc", "syscon";
+		reg = <0xff388000 0x1000>;
+	};
+
+	cru: clock-controller@ff3a0000 {
+		compatible = "rockchip,rv1106-cru";
+		reg = <0xff3a0000 0x20000>;
+		rockchip,grf = <&grf>;
+		#clock-cells = <1>;
+		#reset-cells = <1>;
+
+		assigned-clocks =
+			<&cru PLL_GPLL>, <&cru PLL_CPLL>,
+			<&cru ARMCLK>,
+			<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
+			<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
+			<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
+			<&cru HCLK_PMU_ROOT>, <&cru CLK_339M_SRC>;
+		assigned-clock-rates =
+			<1188000000>, <1000000000>,
+			<1104000000>,
+			<400000000>, <200000000>,
+			<100000000>, <300000000>,
+			<100000000>, <100000000>,
+			<200000000>, <264000000>;
+	};
+
+	saradc: saradc@ff3c0000 {
+		compatible = "rockchip,rv1106-saradc";
+		reg = <0xff3c0000 0x200>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		#io-channel-cells = <1>;
+		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_P_SARADC>;
+		reset-names = "saradc-apb";
+		status = "disabled";
+	};
+
+	tsadc: tsadc@ff3c8000 {
+		compatible = "rockchip,rv1106-tsadc";
+		reg = <0xff3c8000 0x1000>;
+		rockchip,grf = <&grf>;
+		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>;
+		clock-names = "tsadc", "apb_pclk", "tsen";
+		assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
+		assigned-clock-rates = <1000000>, <12000000>;
+		resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
+		reset-names = "tsadc", "tsadc-apb";
+		#thermal-sensor-cells = <1>;
+		rockchip,hw-tshut-temp = <120000>;
+		rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+		rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+		status = "disabled";
+	};
+
+	otp: otp@ff3d0000 {
+		compatible = "rockchip,rv1106-otp";
+		reg = <0xff3d0000 0x4000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
+			 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>,
+			 <&cru CLK_OTPC_ARB>, <&cru CLK_PMC_OTP>;
+		clock-names = "usr", "sbpi", "apb", "phy", "arb", "pmc";
+		resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
+			 <&cru SRST_P_OTPC_NS>, <&cru SRST_P_OTP_MASK>,
+			 <&cru SRST_OTPC_ARB>, <&cru SRST_PMC_OTP>;
+		reset-names = "usr", "sbpi", "apb", "phy", "arb", "pmc";
+
+		cpu_code: cpu-code@2 {
+			reg = <0x02 0x2>;
+		};
+
+		otp_cpu_version: cpu-version@8 {
+			reg = <0x08 0x1>;
+			bits = <3 3>;
+		};
+
+		otp_id: id@a {
+			reg = <0x0a 0x10>;
+		};
+
+		cpu_leakage: cpu-leakage@1a {
+			reg = <0x1a 0x1>;
+		};
+
+		log_leakage: log-leakage@1b {
+			reg = <0x1b 0x1>;
+		};
+
+		macphy_bgs: macphy-bgs@2d {
+			reg = <0x2d 0x1>;
+		};
+
+		macphy_txlevel: macphy-txlevel@2e {
+			reg = <0x2e 0x2>;
+		};
+	};
+
+	u2phy: usb2-phy@ff3e0000 {
+		compatible = "rockchip,rv1106-usb2phy";
+		reg = <0xff3e0000 0x8000>;
+		rockchip,usbgrf = <&grf>;
+		clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
+		clock-names = "phyclk", "pclk";
+		resets = <&cru SRST_USBPHY_POR>, <&cru SRST_P_USBPHY>;
+		reset-names = "u2phy", "u2phy-apb";
+		#clock-cells = <0>;
+		status = "disabled";
+
+		u2phy_otg: otg-port {
+			#phy-cells = <0>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "otg-bvalid", "otg-id",
+					  "linestate", "disconnect";
+			rockchip,vbus-always-on;
+			status = "disabled";
+		};
+	};
+
+	dmac: dma-controller@ff420000 {
+		compatible = "arm,pl330", "arm,primecell";
+		reg = <0xff420000 0x4000>;
+		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		#dma-cells = <1>;
+		clocks = <&cru ACLK_DMAC>;
+		clock-names = "apb_pclk";
+		arm,pl330-periph-burst;
+	};
+
+/*
+	crypto: crypto@ff440000 {
+		compatible = "rockchip,crypto-v3";
+		reg = <0xff440000 0x2000>;
+		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
+			 <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
+		clock-names = "aclk", "hclk", "sclk", "pka";
+		assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
+		assigned-clock-rates = <200000000>, <200000000>;
+		resets = <&cru SRST_CORE_CRYPTO>;
+		reset-names = "crypto-rst";
+		status = "disabled";
+	};
+*/
+
+	rng: rng@ff448000 {
+		compatible = "rockchip,trngv1";
+		reg = <0xff448000 0x200>;
+		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_TRNG_NS>;
+		clock-names = "hclk_trng";
+		resets = <&cru SRST_H_TRNG_NS>;
+		reset-names = "reset";
+		status = "disabled";
+	};
+
+	i2c2: i2c@ff450000 {
+		compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+		reg = <0xff450000 0x1000>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+		clock-names = "i2c", "pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c2m0_xfer>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@ff460000 {
+		compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+		reg = <0xff460000 0x1000>;
+		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+		clock-names = "i2c", "pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c3m1_xfer>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@ff470000 {
+		compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+		reg = <0xff470000 0x1000>;
+		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+		clock-names = "i2c", "pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&i2c4m1_xfer>;
+		status = "disabled";
+	};
+
+/*
+	acodec: acodec@ff480000 {
+		compatible = "rockchip,rv1103-codec";
+		reg = <0xff480000 0x1000>;
+		rockchip,grf = <&grf>;
+		clocks = <&cru PCLK_ACODEC>,
+			 <&cru MCLK_ACODEC_TX>,
+			 <&cru MCLK_I2S0_8CH_TX>;
+		clock-names = "pclk_acodec", "mclk_acodec", "mclk_cpu";
+		resets = <&cru SRST_P_ACODEC>;
+		reset-names = "acodec-reset";
+		acodec,micbias;
+		init-mic-gain = <0x22>; // Left:20dB Right:20dB
+		status = "disabled";
+	};
+*/
+
+	pwm8: pwm@ff490000 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff490000 0x10>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm8m0_pins>;
+		clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm9: pwm@ff490010 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff490010 0x10>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm9m0_pins>;
+		clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm10: pwm@ff490020 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff490020 0x10>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm10m0_pins>;
+		clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	pwm11: pwm@ff490030 {
+		compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+		reg = <0xff490030 0x10>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+		#pwm-cells = <3>;
+		pinctrl-names = "active";
+		pinctrl-0 = <&pwm11m0_pins>;
+		clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+		clock-names = "pwm", "pclk";
+		status = "disabled";
+	};
+
+	uart0: serial@ff4a0000 {
+		compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+		reg = <0xff4a0000 0x100>;
+		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		dmas = <&dmac 7>, <&dmac 6>;
+		clock-frequency = <24000000>;
+		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart0m0_xfer>;
+		status = "disabled";
+	};
+
+	uart1: serial@ff4b0000 {
+		compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+		reg = <0xff4b0000 0x100>;
+		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		dmas = <&dmac 9>, <&dmac 8>;
+		clock-frequency = <24000000>;
+		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+		status = "disabled";
+	};
+
+	uart2: serial@ff4c0000 {
+		compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+		reg = <0xff4c0000 0x100>;
+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		dmas = <&dmac 11>, <&dmac 10>;
+		clock-frequency = <24000000>;
+		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart2m1_xfer>;
+		status = "disabled";
+	};
+
+	uart3: serial@ff4d0000 {
+		compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+		reg = <0xff4d0000 0x100>;
+		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		dmas = <&dmac 13>, <&dmac 12>;
+		clock-frequency = <24000000>;
+		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart3m0_xfer>;
+		status = "disabled";
+	};
+
+	uart4: serial@ff4e0000 {
+		compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+		reg = <0xff4e0000 0x100>;
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		dmas = <&dmac 15>, <&dmac 14>;
+		clock-frequency = <24000000>;
+		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart4m0_xfer>;
+		status = "disabled";
+	};
+
+	uart5: serial@ff4f0000 {
+		compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
+		reg = <0xff4f0000 0x100>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		dmas = <&dmac 17>, <&dmac 16>;
+		clock-frequency = <24000000>;
+		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+		clock-names = "baudclk", "apb_pclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
+		status = "disabled";
+	};
+
+	spi0: spi@ff500000 {
+		compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi";
+		reg = <0xff500000 0x1000>;
+		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>;
+		clock-names = "spiclk", "apb_pclk", "sclk_in";
+		dmas = <&dmac 1>, <&dmac 0>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
+		status = "disabled";
+	};
+
+	spi1: spi@ff510000 {
+		compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi";
+		reg = <0xff510000 0x1000>;
+		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+		clock-names = "spiclk", "apb_pclk";
+		assigned-clocks = <&cru CLK_SPI1>;
+		assigned-clock-rates = <200000000>;
+		dmas = <&dmac 3>, <&dmac 2>;
+		dma-names = "tx", "rx";
+		pinctrl-names = "default";
+		pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
+		status = "disabled";
+	};
+
+	ioc: syscon@ff538000 {
+		compatible = "rockchip,rv1106-ioc", "syscon";
+		reg = <0xff538000 0x40000>;
+	};
+
+	wdt: watchdog@ff5a0000 {
+		compatible = "rockchip,rv1106-wdt", "snps,dw-wdt";
+		reg = <0xff5a0000 0x100>;
+		clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
+		clock-names = "tclk", "pclk";
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
+	mailbox: mailbox@ff5c0000 {
+		compatible = "rockchip,rv1106-mailbox",
+			     "rockchip,rk3368-mailbox";
+		reg = <0xff5c0000 0x200>;
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_MAILBOX>;
+		clock-names = "pclk_mailbox";
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
+	system_sram: sram@ff6c0000 {
+		compatible = "mmio-sram";
+		reg = <0xff6c0000 0x40000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xff6c0000 0x40000>;
+		rkisp_sram: rkisp-sram@0 {
+			reg = <0x0 0x3f000>;
+		};
+		hpmcu_sram: hpmcu-sram@3f000 {
+			reg = <0x3f000 0x1000>;
+		};
+	};
+
+	sdio: mmc@ff9a0000 {
+		compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0xff9a0000 0x4000>;
+		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
+			 <&grf_cru SCLK_SDIO_DRV>, <&grf_cru SCLK_SDIO_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <200000000>;
+		status = "disabled";
+	};
+
+	emmc: mmc@ffa90000 {
+		compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0xffa90000 0x4000>;
+		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_EMMC>, <&cru CCLK_SRC_EMMC>,
+			 <&grf_cru SCLK_EMMC_DRV>, <&grf_cru SCLK_EMMC_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <200000000>;
+		rockchip,use-v2-tuning;
+		status = "disabled";
+	};
+
+	sdmmc: mmc@ffaa0000 {
+		compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
+		reg = <0xffaa0000 0x4000>;
+		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru HCLK_SDMMC>, <&cru CCLK_SRC_SDMMC>,
+			 <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>;
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+		fifo-depth = <0x100>;
+		max-frequency = <200000000>;
+		status = "disabled";
+	};
+
+	sfc: spi@ffac0000 {
+		compatible = "rockchip,sfc";
+		reg = <0xffac0000 0x4000>;
+		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+		clock-names = "clk_sfc", "hclk_sfc";
+		assigned-clocks = <&cru SCLK_SFC>;
+		assigned-clock-rates = <75000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2s0_8ch: i2s@ffae0000 {
+		compatible = "rockchip,rv1106-i2s-tdm";
+		reg = <0xffae0000 0x1000>;
+		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>;
+		clock-names = "mclk_tx", "mclk_rx", "hclk";
+		dmas = <&dmac 22>, <&dmac 21>;
+		dma-names = "tx", "rx";
+		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
+		reset-names = "tx-m", "rx-m";
+		rockchip,trcm-sync-tx-only;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+	};
+
+	usbdrd: usbdrd {
+		compatible = "rockchip,rv1106-dwc3", "rockchip,rk3399-dwc3";
+		clocks = <&cru CLK_REF_USBOTG>, <&cru CLK_UTMI_USBOTG>,
+			 <&cru ACLK_USBOTG>;
+		clock-names = "ref", "utmi", "bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		status = "disabled";
+
+		usbdrd_dwc3: usb@ffb00000 {
+			compatible = "snps,dwc3";
+			reg = <0xffb00000 0x100000>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&cru SRST_A_USBOTG>;
+			reset-names = "usb3-otg";
+			dr_mode = "otg";
+			maximum-speed = "high-speed";
+			phys = <&u2phy_otg>;
+			phy-names = "usb2-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,usb2-gadget-lpm-disable;
+			snps,usb2-lpm-disable;
+			snps,parkmode-disable-hs-quirk;
+			status = "disabled";
+		};
+	};
+
+	pinctrl: pinctrl {
+		compatible = "rockchip,rv1106-pinctrl";
+		rockchip,grf = <&ioc>;
+		rockchip,pmu = <&pmuioc>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gpio0: gpio@ff380000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0xff380000 0x100>;
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio1: gpio@ff530000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0xff530000 0x100>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 32 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@ff550000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0xff550000 0x100>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 96 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio4: gpio@ff560000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0xff560000 0x100>;
+			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 128 32>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_up: pcfg-pull-up {
+			bias-pull-up;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_down: pcfg-pull-down {
+			bias-pull-down;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_none: pcfg-pull-none {
+			bias-disable;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+			bias-disable;
+			drive-strength = <0>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+			bias-disable;
+			drive-strength = <1>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+			bias-disable;
+			drive-strength = <3>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
+			bias-disable;
+			drive-strength = <4>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+			bias-pull-up;
+			drive-strength = <0>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+			bias-pull-up;
+			drive-strength = <1>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+			bias-pull-up;
+			drive-strength = <2>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
+			bias-pull-up;
+			drive-strength = <3>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
+			bias-pull-up;
+			drive-strength = <4>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
+			bias-pull-down;
+			drive-strength = <0>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
+			bias-pull-down;
+			drive-strength = <1>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
+			bias-pull-down;
+			drive-strength = <2>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
+			bias-pull-down;
+			drive-strength = <3>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
+			bias-pull-down;
+			drive-strength = <4>;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_up_smt: pcfg-pull-up-smt {
+			bias-pull-up;
+			input-schmitt-enable;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_down_smt: pcfg-pull-down-smt {
+			bias-pull-down;
+			input-schmitt-enable;
+		};
+
+		/omit-if-no-ref/
+		pcfg_pull_none_smt: pcfg-pull-none-smt {
+			bias-disable;
+			input-schmitt-enable;
+		};
+
+		/omit-if-no-ref/
+		pcfg_output_high: pcfg-output-high {
+			output-high;
+		};
+
+		/omit-if-no-ref/
+		pcfg_output_high_pull_up: pcfg-output-high-pull-up {
+			output-high;
+			bias-pull-up;
+		};
+
+		/omit-if-no-ref/
+		pcfg_output_high_pull_down: pcfg-output-high-pull-down {
+			output-high;
+			bias-pull-down;
+		};
+
+		/omit-if-no-ref/
+		pcfg_output_high_pull_none: pcfg-output-high-pull-none {
+			output-high;
+			bias-disable;
+		};
+
+		/omit-if-no-ref/
+		pcfg_output_low: pcfg-output-low {
+			output-low;
+		};
+
+		/omit-if-no-ref/
+		pcfg_output_low_pull_up: pcfg-output-low-pull-up {
+			output-low;
+			bias-pull-up;
+		};
+
+		/omit-if-no-ref/
+		pcfg_output_low_pull_down: pcfg-output-low-pull-down {
+			output-low;
+			bias-pull-down;
+		};
+
+		/omit-if-no-ref/
+		pcfg_output_low_pull_none: pcfg-output-low-pull-none {
+			output-low;
+			bias-disable;
+		};
+
+		adc {
+			/omit-if-no-ref/
+			adc_pins: adc-pins {
+				rockchip,pins =
+					/* adc_in0 */
+					<4 RK_PC0 1 &pcfg_pull_none>,
+					/* adc_in1 */
+					<4 RK_PC1 1 &pcfg_pull_none>;
+			};
+		};
+
+		avs {
+			/omit-if-no-ref/
+			avs_pins: avs-pins {
+				rockchip,pins =
+					/* avs_arm */
+					<1 RK_PA2 2 &pcfg_pull_none>;
+			};
+		};
+
+		clk {
+			/omit-if-no-ref/
+			clk_32k: clk-32k {
+				rockchip,pins =
+					/* clk_32k */
+					<0 RK_PA0 2 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			clk_refout: clk-refout {
+				rockchip,pins =
+					/* clk_refout */
+					<0 RK_PA0 3 &pcfg_pull_none>;
+			};
+		};
+
+		dsmaudio {
+			/omit-if-no-ref/
+			dsmaudio_pins: dsmaudio-pins {
+				rockchip,pins =
+					/* dsmaudio_n */
+					<1 RK_PD3 7 &pcfg_pull_none>,
+					/* dsmaudio_p */
+					<1 RK_PD2 7 &pcfg_pull_none>;
+			};
+		};
+
+		emmc {
+			/omit-if-no-ref/
+			emmc_bus8: emmc-bus8 {
+				rockchip,pins =
+					/* emmc_d0 */
+					<4 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+					/* emmc_d1 */
+					<4 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+					/* emmc_d2 */
+					<4 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+					/* emmc_d3 */
+					<4 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+					/* emmc_d4 */
+					<4 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+					/* emmc_d5 */
+					<4 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
+					/* emmc_d6 */
+					<4 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+					/* emmc_d7 */
+					<4 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			emmc_clk: emmc-clk {
+				rockchip,pins =
+					/* emmc_clk */
+					<4 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			emmc_cmd: emmc-cmd {
+				rockchip,pins =
+					/* emmc_cmd */
+					<4 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+			};
+		};
+
+		flash {
+			/omit-if-no-ref/
+			flash_pins: flash-pins {
+				rockchip,pins =
+					/* flash_trig_out */
+					<2 RK_PA6 6 &pcfg_pull_none>;
+			};
+		};
+
+		fspi {
+			/omit-if-no-ref/
+			fspi_pins: fspi-pins {
+				rockchip,pins =
+					/* fspi_clk */
+					<4 RK_PB1 2 &pcfg_pull_up_drv_level_2>,
+					/* fspi_d0 */
+					<4 RK_PA4 2 &pcfg_pull_none>,
+					/* fspi_d1 */
+					<4 RK_PA3 2 &pcfg_pull_none>,
+					/* fspi_d2 */
+					<4 RK_PA2 2 &pcfg_pull_none>,
+					/* fspi_d3 */
+					<4 RK_PA6 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			fspi_cs0: fspi-cs0 {
+				rockchip,pins =
+					/* fspi_cs0n */
+					<4 RK_PB0 2 &pcfg_pull_up>;
+			};
+		};
+
+		hpmcu {
+			/omit-if-no-ref/
+			hpmcum0_pins: hpmcum0-pins {
+				rockchip,pins =
+					/* hpmcu_jtag_tck_m0 */
+					<1 RK_PB2 3 &pcfg_pull_none>,
+					/* hpmcu_jtag_tms_m0 */
+					<1 RK_PB3 3 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			hpmcum1_pins: hpmcum1-pins {
+				rockchip,pins =
+					/* hpmcu_jtag_tck_m1 */
+					<3 RK_PA7 4 &pcfg_pull_none>,
+					/* hpmcu_jtag_tms_m1 */
+					<3 RK_PA6 4 &pcfg_pull_none>;
+			};
+		};
+
+		i2c0 {
+			/omit-if-no-ref/
+			i2c0m0_xfer: i2c0m0-xfer {
+				rockchip,pins =
+					/* i2c0_scl_m0 */
+					<1 RK_PA3 2 &pcfg_pull_none_smt>,
+					/* i2c0_sda_m0 */
+					<1 RK_PA4 2 &pcfg_pull_none_smt>;
+			};
+
+			/omit-if-no-ref/
+			i2c0m1_xfer: i2c0m1-xfer {
+				rockchip,pins =
+					/* i2c0_scl_m1 */
+					<4 RK_PA1 4 &pcfg_pull_none_smt>,
+					/* i2c0_sda_m1 */
+					<4 RK_PA0 4 &pcfg_pull_none_smt>;
+			};
+
+			/omit-if-no-ref/
+			i2c0m2_xfer: i2c0m2-xfer {
+				rockchip,pins =
+					/* i2c0_scl_m2 */
+					<3 RK_PA4 3 &pcfg_pull_none_smt>,
+					/* i2c0_sda_m2 */
+					<3 RK_PA5 3 &pcfg_pull_none_smt>;
+			};
+		};
+
+		i2c1 {
+			/omit-if-no-ref/
+			i2c1m0_xfer: i2c1m0-xfer {
+				rockchip,pins =
+					/* i2c1_scl_m0 */
+					<0 RK_PA5 1 &pcfg_pull_none_smt>,
+					/* i2c1_sda_m0 */
+					<0 RK_PA6 1 &pcfg_pull_none_smt>;
+			};
+
+			/omit-if-no-ref/
+			i2c1m1_xfer: i2c1m1-xfer {
+				rockchip,pins =
+					/* i2c1_scl_m1 */
+					<2 RK_PB0 2 &pcfg_pull_none_smt>,
+					/* i2c1_sda_m1 */
+					<2 RK_PB1 2 &pcfg_pull_none_smt>;
+			};
+		};
+
+		i2c2 {
+			/omit-if-no-ref/
+			i2c2m0_xfer: i2c2m0-xfer {
+				rockchip,pins =
+					/* i2c2_scl_m0 */
+					<1 RK_PA0 2 &pcfg_pull_none_smt>,
+					/* i2c2_sda_m0 */
+					<1 RK_PA1 2 &pcfg_pull_none_smt>;
+			};
+
+			/omit-if-no-ref/
+			i2c2m1_xfer: i2c2m1-xfer {
+				rockchip,pins =
+					/* i2c2_scl_m1 */
+					<4 RK_PA7 4 &pcfg_pull_none_smt>,
+					/* i2c2_sda_m1 */
+					<4 RK_PA5 4 &pcfg_pull_none_smt>;
+			};
+		};
+
+		i2c3 {
+			/omit-if-no-ref/
+			i2c3m0_xfer: i2c3m0-xfer {
+				rockchip,pins =
+					/* i2c3_scl_m0 */
+					<2 RK_PA6 5 &pcfg_pull_none_smt>,
+					/* i2c3_sda_m0 */
+					<2 RK_PA7 5 &pcfg_pull_none_smt>;
+			};
+
+			/omit-if-no-ref/
+			i2c3m1_xfer: i2c3m1-xfer {
+				rockchip,pins =
+					/* i2c3_scl_m1 */
+					<1 RK_PD3 3 &pcfg_pull_none_smt>,
+					/* i2c3_sda_m1 */
+					<1 RK_PD2 3 &pcfg_pull_none_smt>;
+			};
+
+			/omit-if-no-ref/
+			i2c3m2_xfer: i2c3m2-xfer {
+				rockchip,pins =
+					/* i2c3_scl_m2 */
+					<3 RK_PD1 3 &pcfg_pull_none_smt>,
+					/* i2c3_sda_m2 */
+					<3 RK_PD2 3 &pcfg_pull_none_smt>;
+			};
+		};
+
+		i2c4 {
+			/omit-if-no-ref/
+			i2c4m0_xfer: i2c4m0-xfer {
+				rockchip,pins =
+					/* i2c4_scl_m0 */
+					<2 RK_PA1 5 &pcfg_pull_none_smt>,
+					/* i2c4_sda_m0 */
+					<2 RK_PA0 5 &pcfg_pull_none_smt>;
+			};
+
+			/omit-if-no-ref/
+			i2c4m1_xfer: i2c4m1-xfer {
+				rockchip,pins =
+					/* i2c4_scl_m1 */
+					<1 RK_PC2 4 &pcfg_pull_none_smt>,
+					/* i2c4_sda_m1 */
+					<1 RK_PC3 4 &pcfg_pull_none_smt>;
+			};
+
+			/omit-if-no-ref/
+			i2c4m2_xfer: i2c4m2-xfer {
+				rockchip,pins =
+					/* i2c4_scl_m2 */
+					<3 RK_PC7 3 &pcfg_pull_none_smt>,
+					/* i2c4_sda_m2 */
+					<3 RK_PD0 3 &pcfg_pull_none_smt>;
+			};
+		};
+
+		i2s0 {
+			/omit-if-no-ref/
+			i2s0_pins: i2s0-pins {
+				rockchip,pins =
+					/* i2s0_lrck */
+					<2 RK_PA1 2 &pcfg_pull_none>,
+					/* i2s0_mclk */
+					<2 RK_PA2 2 &pcfg_pull_none>,
+					/* i2s0_sclk */
+					<2 RK_PA0 2 &pcfg_pull_none>,
+					/* i2s0_sdi0 */
+					<2 RK_PA5 2 &pcfg_pull_none>,
+					/* i2s0_sdo0 */
+					<2 RK_PA4 2 &pcfg_pull_none>,
+					/* i2s0_sdo1_sdi3 */
+					<2 RK_PA7 2 &pcfg_pull_none>,
+					/* i2s0_sdo2_sdi2 */
+					<2 RK_PA6 2 &pcfg_pull_none>,
+					/* i2s0_sdo3_sdi1 */
+					<2 RK_PA3 2 &pcfg_pull_none>;
+			};
+		};
+
+		lcd {
+			/omit-if-no-ref/
+			lcd_pins: lcd-pins {
+				rockchip,pins =
+					/* lcd_clk */
+					<1 RK_PD3 1 &pcfg_pull_none_drv_level_4>,
+					/* lcd_d0 */
+					<1 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d1 */
+					<1 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d2 */
+					<1 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d3 */
+					<1 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d4 */
+					<1 RK_PC3 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d5 */
+					<1 RK_PC2 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d6 */
+					<1 RK_PC1 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d7 */
+					<1 RK_PC0 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d8 */
+					<2 RK_PA0 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d9 */
+					<2 RK_PA1 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d10 */
+					<2 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d11 */
+					<2 RK_PA3 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d12 */
+					<2 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d13 */
+					<2 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d14 */
+					<2 RK_PA6 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d15 */
+					<2 RK_PA7 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d16 */
+					<2 RK_PB0 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d17 */
+					<2 RK_PB1 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_den */
+					<1 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_hsync */
+					<1 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_vsync */
+					<1 RK_PD2 1 &pcfg_pull_none_drv_level_3>;
+			};
+
+			/omit-if-no-ref/
+			bt1120_pins: bt1120-pins {
+				rockchip,pins =
+					/* lcd_clk */
+					<1 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d0 */
+					<1 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d1 */
+					<1 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d2 */
+					<1 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d3 */
+					<1 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d4 */
+					<1 RK_PC3 1 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d5 */
+					<1 RK_PC2 1 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d6 */
+					<1 RK_PC1 1 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d7 */
+					<1 RK_PC0 1 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d8 */
+					<2 RK_PA0 3 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d9 */
+					<2 RK_PA1 3 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d10 */
+					<2 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d11 */
+					<2 RK_PA3 3 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d12 */
+					<2 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d13 */
+					<2 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d14 */
+					<2 RK_PA6 3 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d15 */
+					<2 RK_PA7 3 &pcfg_pull_none_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			bt656_pins: bt656-pins {
+				rockchip,pins =
+					/* lcd_clk */
+					<1 RK_PD3 1 &pcfg_pull_none_drv_level_2>,
+					/* lcd_d0 */
+					<1 RK_PC7 1 &pcfg_pull_none_drv_level_1>,
+					/* lcd_d1 */
+					<1 RK_PC6 1 &pcfg_pull_none_drv_level_1>,
+					/* lcd_d2 */
+					<1 RK_PC5 1 &pcfg_pull_none_drv_level_1>,
+					/* lcd_d3 */
+					<1 RK_PC4 1 &pcfg_pull_none_drv_level_1>,
+					/* lcd_d4 */
+					<1 RK_PC3 1 &pcfg_pull_none_drv_level_1>,
+					/* lcd_d5 */
+					<1 RK_PC2 1 &pcfg_pull_none_drv_level_1>,
+					/* lcd_d6 */
+					<1 RK_PC1 1 &pcfg_pull_none_drv_level_1>,
+					/* lcd_d7 */
+					<1 RK_PC0 1 &pcfg_pull_none_drv_level_1>;
+			};
+
+			/omit-if-no-ref/
+			rgb3x8_pins: rgb3x8-pins {
+				rockchip,pins =
+					/* lcd_clk */
+					<1 RK_PD3 1 &pcfg_pull_none_drv_level_4>,
+					/* lcd_d0 */
+					<1 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d1 */
+					<1 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d2 */
+					<1 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d3 */
+					<1 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d4 */
+					<1 RK_PC3 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d5 */
+					<1 RK_PC2 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d6 */
+					<1 RK_PC1 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d7 */
+					<1 RK_PC0 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_den */
+					<1 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_hsync */
+					<1 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_vsync */
+					<1 RK_PD2 1 &pcfg_pull_none_drv_level_3>;
+			};
+
+			/omit-if-no-ref/
+			rgb565_pins: rgb565-pins {
+				rockchip,pins =
+					/* lcd_clk */
+					<1 RK_PD3 1 &pcfg_pull_none_drv_level_4>,
+					/* lcd_d0 */
+					<1 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d1 */
+					<1 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d2 */
+					<1 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d3 */
+					<1 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d4 */
+					<1 RK_PC3 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d5 */
+					<1 RK_PC2 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d6 */
+					<1 RK_PC1 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d7 */
+					<1 RK_PC0 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d8 */
+					<2 RK_PA0 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d9 */
+					<2 RK_PA1 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d10 */
+					<2 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d11 */
+					<2 RK_PA3 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d12 */
+					<2 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d13 */
+					<2 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d14 */
+					<2 RK_PA6 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_d15 */
+					<2 RK_PA7 3 &pcfg_pull_none_drv_level_3>,
+					/* lcd_den */
+					<1 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_hsync */
+					<1 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
+					/* lcd_vsync */
+					<1 RK_PD2 1 &pcfg_pull_none_drv_level_3>;
+			};
+		};
+
+		lpmcu {
+			/omit-if-no-ref/
+			lpmcum0_pins: lpmcum0-pins {
+				rockchip,pins =
+					/* lpmcu_jtag_tck_m0 */
+					<1 RK_PB2 4 &pcfg_pull_none>,
+					/* lpmcu_jtag_tms_m0 */
+					<1 RK_PB3 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			lpmcum1_pins: lpmcum1-pins {
+				rockchip,pins =
+					/* lpmcu_jtag_tck_m1 */
+					<3 RK_PA4 4 &pcfg_pull_none>,
+					/* lpmcu_jtag_tms_m1 */
+					<3 RK_PA5 4 &pcfg_pull_none>;
+			};
+		};
+
+		mipi {
+			/omit-if-no-ref/
+			mipi_pins: mipi-pins {
+				rockchip,pins =
+					/* mipi_lvds_ck0n */
+					<3 RK_PC0 2 &pcfg_pull_none>,
+					/* mipi_lvds_ck0p */
+					<3 RK_PC1 2 &pcfg_pull_none>,
+					/* mipi_lvds_ck1n */
+					<3 RK_PB2 2 &pcfg_pull_none>,
+					/* mipi_lvds_ck1p */
+					<3 RK_PB3 2 &pcfg_pull_none>,
+					/* mipi_lvds_d0n */
+					<3 RK_PC2 2 &pcfg_pull_none>,
+					/* mipi_lvds_d0p */
+					<3 RK_PC3 2 &pcfg_pull_none>,
+					/* mipi_lvds_d1n */
+					<3 RK_PB6 2 &pcfg_pull_none>,
+					/* mipi_lvds_d1p */
+					<3 RK_PB7 2 &pcfg_pull_none>,
+					/* mipi_lvds_d2n */
+					<3 RK_PB4 2 &pcfg_pull_none>,
+					/* mipi_lvds_d2p */
+					<3 RK_PB5 2 &pcfg_pull_none>,
+					/* mipi_lvds_d3n */
+					<3 RK_PB0 2 &pcfg_pull_none>,
+					/* mipi_lvds_d3p */
+					<3 RK_PB1 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			mipi_refclk_out0: mipi-refclk-out0 {
+				rockchip,pins =
+					/* mipi_refclk_out0 */
+					<3 RK_PC4 2 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			mipi_refclk_out1: mipi-refclk-out1 {
+				rockchip,pins =
+					/* mipi_refclk_out1 */
+					<3 RK_PC6 3 &pcfg_pull_none>;
+			};
+		};
+
+		pmic {
+			/omit-if-no-ref/
+			pmicm0_pins: pmicm0-pins {
+				rockchip,pins =
+					/* pmic_sleep_m0 */
+					<0 RK_PA4 1 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pmicm1_pins: pmicm1-pins {
+				rockchip,pins =
+					/* pmic_sleep_m1 */
+					<0 RK_PA3 1 &pcfg_pull_none>;
+			};
+		};
+
+		pmu {
+			/omit-if-no-ref/
+			pmu_pins: pmu-pins {
+				rockchip,pins =
+					/* pmu_debug */
+					<1 RK_PA1 3 &pcfg_pull_none>;
+			};
+		};
+
+		prelight {
+			/omit-if-no-ref/
+			prelight_pins: prelight-pins {
+				rockchip,pins =
+					/* prelight_trig_out */
+					<2 RK_PA7 6 &pcfg_pull_none>;
+			};
+		};
+
+		pwm0 {
+			/omit-if-no-ref/
+			pwm0m0_pins: pwm0m0-pins {
+				rockchip,pins =
+					/* pwm0_m0 */
+					<1 RK_PA2 1 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm0m1_pins: pwm0m1-pins {
+				rockchip,pins =
+					/* pwm0_m1 */
+					<1 RK_PD2 6 &pcfg_pull_none>;
+			};
+		};
+
+		pwm1 {
+			/omit-if-no-ref/
+			pwm1m0_pins: pwm1m0-pins {
+				rockchip,pins =
+					/* pwm1_m0 */
+					<0 RK_PA4 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm1m1_pins: pwm1m1-pins {
+				rockchip,pins =
+					/* pwm1_m1 */
+					<4 RK_PC1 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm1m2_pins: pwm1m2-pins {
+				rockchip,pins =
+					/* pwm1_m2 */
+					<3 RK_PD3 2 &pcfg_pull_none>;
+			};
+		};
+
+		pwm2 {
+			/omit-if-no-ref/
+			pwm2m0_pins: pwm2m0-pins {
+				rockchip,pins =
+					/* pwm2_m0 */
+					<0 RK_PA1 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm2m1_pins: pwm2m1-pins {
+				rockchip,pins =
+					/* pwm2_m1 */
+					<2 RK_PA6 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm2m2_pins: pwm2m2-pins {
+				rockchip,pins =
+					/* pwm2_m2 */
+					<1 RK_PC0 3 &pcfg_pull_none>;
+			};
+		};
+
+		pwm3 {
+			/omit-if-no-ref/
+			pwm3m0_pins: pwm3m0-pins {
+				rockchip,pins =
+					/* pwm3_ir_m0 */
+					<0 RK_PA2 1 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm3m1_pins: pwm3m1-pins {
+				rockchip,pins =
+					/* pwm3_ir_m1 */
+					<1 RK_PB0 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm3m2_pins: pwm3m2-pins {
+				rockchip,pins =
+					/* pwm3_ir_m2 */
+					<1 RK_PD0 3 &pcfg_pull_none>;
+			};
+		};
+
+		pwm4 {
+			/omit-if-no-ref/
+			pwm4m0_pins: pwm4m0-pins {
+				rockchip,pins =
+					/* pwm4_m0 */
+					<1 RK_PA1 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm4m1_pins: pwm4m1-pins {
+				rockchip,pins =
+					/* pwm4_m1 */
+					<2 RK_PA7 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm4m2_pins: pwm4m2-pins {
+				rockchip,pins =
+					/* pwm4_m2 */
+					<1 RK_PC1 3 &pcfg_pull_none>;
+			};
+		};
+
+		pwm5 {
+			/omit-if-no-ref/
+			pwm5m0_pins: pwm5m0-pins {
+				rockchip,pins =
+					/* pwm5_m0 */
+					<0 RK_PA5 3 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm5m1_pins: pwm5m1-pins {
+				rockchip,pins =
+					/* pwm5_m1 */
+					<2 RK_PB0 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm5m2_pins: pwm5m2-pins {
+				rockchip,pins =
+					/* pwm5_m2 */
+					<1 RK_PC2 3 &pcfg_pull_none>;
+			};
+		};
+
+		pwm6 {
+			/omit-if-no-ref/
+			pwm6m0_pins: pwm6m0-pins {
+				rockchip,pins =
+					/* pwm6_m0 */
+					<0 RK_PA6 3 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm6m1_pins: pwm6m1-pins {
+				rockchip,pins =
+					/* pwm6_m1 */
+					<2 RK_PB1 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm6m2_pins: pwm6m2-pins {
+				rockchip,pins =
+					/* pwm6_m2 */
+					<1 RK_PC3 3 &pcfg_pull_none>;
+			};
+		};
+
+		pwm7 {
+			/omit-if-no-ref/
+			pwm7m0_pins: pwm7m0-pins {
+				rockchip,pins =
+					/* pwm7_ir_m0 */
+					<1 RK_PA0 3 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm7m1_pins: pwm7m1-pins {
+				rockchip,pins =
+					/* pwm7_ir_m1 */
+					<1 RK_PB1 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm7m2_pins: pwm7m2-pins {
+				rockchip,pins =
+					/* pwm7_ir_m2 */
+					<3 RK_PC6 2 &pcfg_pull_none>;
+			};
+		};
+
+		pwm8 {
+			/omit-if-no-ref/
+			pwm8m0_pins: pwm8m0-pins {
+				rockchip,pins =
+					/* pwm8_m0 */
+					<3 RK_PA3 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm8m1_pins: pwm8m1-pins {
+				rockchip,pins =
+					/* pwm8_m1 */
+					<1 RK_PC4 3 &pcfg_pull_none>;
+			};
+		};
+
+		pwm9 {
+			/omit-if-no-ref/
+			pwm9m0_pins: pwm9m0-pins {
+				rockchip,pins =
+					/* pwm9_m0 */
+					<3 RK_PA2 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm9m1_pins: pwm9m1-pins {
+				rockchip,pins =
+					/* pwm9_m1 */
+					<1 RK_PC5 3 &pcfg_pull_none>;
+			};
+		};
+
+		pwm10 {
+			/omit-if-no-ref/
+			pwm10m0_pins: pwm10m0-pins {
+				rockchip,pins =
+					/* pwm10_m0 */
+					<3 RK_PA4 5 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm10m1_pins: pwm10m1-pins {
+				rockchip,pins =
+					/* pwm10_m1 */
+					<1 RK_PC6 3 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm10m2_pins: pwm10m2-pins {
+				rockchip,pins =
+					/* pwm10_m2 */
+					<1 RK_PD1 3 &pcfg_pull_none>;
+			};
+		};
+
+		pwm11 {
+			/omit-if-no-ref/
+			pwm11m0_pins: pwm11m0-pins {
+				rockchip,pins =
+					/* pwm11_ir_m0 */
+					<3 RK_PA5 5 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm11m1_pins: pwm11m1-pins {
+				rockchip,pins =
+					/* pwm11_ir_m1 */
+					<1 RK_PC7 3 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			pwm11m2_pins: pwm11m2-pins {
+				rockchip,pins =
+					/* pwm11_ir_m2 */
+					<1 RK_PD3 5 &pcfg_pull_none>;
+			};
+		};
+
+		rtc {
+			/omit-if-no-ref/
+			rtc_pins: rtc-pins {
+				rockchip,pins =
+					/* rtc_clko */
+					<0 RK_PA0 4 &pcfg_pull_none>;
+			};
+		};
+
+		sdmmc0 {
+			/omit-if-no-ref/
+			sdmmc0_bus4: sdmmc0-bus4 {
+				rockchip,pins =
+					/* sdmmc0_d0 */
+					<3 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+					/* sdmmc0_d1 */
+					<3 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+					/* sdmmc0_d2 */
+					<3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
+					/* sdmmc0_d3 */
+					<3 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			sdmmc0_clk: sdmmc0-clk {
+				rockchip,pins =
+					/* sdmmc0_clk */
+					<3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			sdmmc0_cmd: sdmmc0-cmd {
+				rockchip,pins =
+					/* sdmmc0_cmd */
+					<3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			sdmmc0_det: sdmmc0-det {
+				rockchip,pins =
+					/* sdmmc0_det */
+					<3 RK_PA1 1 &pcfg_pull_up>;
+			};
+		};
+
+		sdmmc1 {
+			/omit-if-no-ref/
+			sdmmc1m0_bus1: sdmmc1m0-bus1 {
+				rockchip,pins =
+					/* sdmmc1_d0_m0 */
+					<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			sdmmc1m0_bus4: sdmmc1m0-bus4 {
+				rockchip,pins =
+					/* sdmmc1_d0_m0 */
+					<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+					/* sdmmc1_d1_m0 */
+					<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+					/* sdmmc1_d2_m0 */
+					<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+					/* sdmmc1_d3_m0 */
+					<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			sdmmc1m0_clk: sdmmc1m0-clk {
+				rockchip,pins =
+					/* sdmmc1_clk_m0 */
+					<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			sdmmc1m0_cmd: sdmmc1m0-cmd {
+				rockchip,pins =
+					/* sdmmc1_cmd_m0 */
+					<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			sdmmc1m1_bus4: sdmmc1m1-bus4 {
+				rockchip,pins =
+					/* sdmmc1_d0_m1 */
+					<1 RK_PC1 5 &pcfg_pull_up_drv_level_2>,
+					/* sdmmc1_d1_m1 */
+					<1 RK_PC0 5 &pcfg_pull_up_drv_level_2>,
+					/* sdmmc1_d2_m1 */
+					<1 RK_PC5 5 &pcfg_pull_up_drv_level_2>,
+					/* sdmmc1_d3_m1 */
+					<1 RK_PC4 5 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			sdmmc1m1_clk: sdmmc1m1-clk {
+				rockchip,pins =
+					/* sdmmc1_clk_m1 */
+					<1 RK_PC2 5 &pcfg_pull_up_drv_level_2>;
+			};
+
+			/omit-if-no-ref/
+			sdmmc1m1_cmd: sdmmc1m1-cmd {
+				rockchip,pins =
+					/* sdmmc1_cmd_m1 */
+					<1 RK_PC3 5 &pcfg_pull_up_drv_level_2>;
+			};
+		};
+
+		spi0 {
+			/omit-if-no-ref/
+			spi0m0_pins: spi0m0-pins {
+				rockchip,pins =
+					/* spi0_clk_m0 */
+					<1 RK_PC1 4 &pcfg_pull_none>,
+					/* spi0_miso_m0 */
+					<1 RK_PC3 6 &pcfg_pull_none>,
+					/* spi0_mosi_m0 */
+					<1 RK_PC2 6 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			spi0m0_cs0: spi0m0-cs0 {
+				rockchip,pins =
+					/* spi0_cs0n_m0 */
+					<1 RK_PC0 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			spi0m0_cs1: spi0m0-cs1 {
+				rockchip,pins =
+					/* spi0_cs1n_m0 */
+					<1 RK_PD2 5 &pcfg_pull_none>;
+			};
+		};
+
+		spi1 {
+			/omit-if-no-ref/
+			spi1m0_pins: spi1m0-pins {
+				rockchip,pins =
+					/* spi1_clk_m0 */
+					<4 RK_PA7 2 &pcfg_pull_none>,
+					/* spi1_miso_m0 */
+					<4 RK_PA0 2 &pcfg_pull_none>,
+					/* spi1_mosi_m0 */
+					<4 RK_PA1 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			spi1m0_cs0: spi1m0-cs0 {
+				rockchip,pins =
+					/* spi1_cs0n_m0 */
+					<4 RK_PA5 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			spi1m0_cs1: spi1m0-cs1 {
+				rockchip,pins =
+					/* spi1_cs1n_m0 */
+					<1 RK_PB1 3 &pcfg_pull_none>;
+			};
+		};
+
+		uart0 {
+			/omit-if-no-ref/
+			uart0m0_xfer: uart0m0-xfer {
+				rockchip,pins =
+					/* uart0_rx_m0 */
+					<0 RK_PA0 1 &pcfg_pull_up>,
+					/* uart0_tx_m0 */
+					<0 RK_PA1 1 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart0m1_xfer: uart0m1-xfer {
+				rockchip,pins =
+					/* uart0_rx_m1 */
+					<2 RK_PB0 1 &pcfg_pull_up>,
+					/* uart0_tx_m1 */
+					<2 RK_PB1 1 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart0m1_ctsn: uart0m1-ctsn {
+				rockchip,pins =
+					/* uart0m1_ctsn */
+					<2 RK_PA7 1 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			uart0m1_rtsn: uart0m1-rtsn {
+				rockchip,pins =
+					/* uart0m1_rtsn */
+					<2 RK_PA6 1 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			uart0m2_xfer: uart0m2-xfer {
+				rockchip,pins =
+					/* uart0_rx_m2 */
+					<4 RK_PA0 3 &pcfg_pull_up>,
+					/* uart0_tx_m2 */
+					<4 RK_PA1 3 &pcfg_pull_up>;
+			};
+		};
+
+		uart1 {
+			/omit-if-no-ref/
+			uart1m0_xfer: uart1m0-xfer {
+				rockchip,pins =
+					/* uart1_rx_m0 */
+					<1 RK_PA4 1 &pcfg_pull_up>,
+					/* uart1_tx_m0 */
+					<1 RK_PA3 1 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart1m0_ctsn: uart1m0-ctsn {
+				rockchip,pins =
+					/* uart1m0_ctsn */
+					<0 RK_PA6 2 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			uart1m0_rtsn: uart1m0-rtsn {
+				rockchip,pins =
+					/* uart1m0_rtsn */
+					<0 RK_PA5 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			uart1m1_xfer: uart1m1-xfer {
+				rockchip,pins =
+					/* uart1_rx_m1 */
+					<2 RK_PA5 4 &pcfg_pull_up>,
+					/* uart1_tx_m1 */
+					<2 RK_PA4 4 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart1m1_ctsn: uart1m1-ctsn {
+				rockchip,pins =
+					/* uart1m1_ctsn */
+					<2 RK_PA0 4 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			uart1m1_rtsn: uart1m1-rtsn {
+				rockchip,pins =
+					/* uart1m1_rtsn */
+					<2 RK_PA1 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			uart1m2_xfer: uart1m2-xfer {
+				rockchip,pins =
+					/* uart1_rx_m2 */
+					<4 RK_PA7 3 &pcfg_pull_up>,
+					/* uart1_tx_m2 */
+					<4 RK_PA5 3 &pcfg_pull_up>;
+			};
+		};
+
+		uart2 {
+			/omit-if-no-ref/
+			uart2m0_xfer: uart2m0-xfer {
+				rockchip,pins =
+					/* uart2_rx_m0 */
+					<3 RK_PA3 2 &pcfg_pull_up>,
+					/* uart2_tx_m0 */
+					<3 RK_PA2 2 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart2m1_xfer: uart2m1-xfer {
+				rockchip,pins =
+					/* uart2_rx_m1 */
+					<1 RK_PB3 2 &pcfg_pull_up>,
+					/* uart2_tx_m1 */
+					<1 RK_PB2 2 &pcfg_pull_up>;
+			};
+		};
+
+		uart3 {
+			/omit-if-no-ref/
+			uart3m0_xfer: uart3m0-xfer {
+				rockchip,pins =
+					/* uart3_rx_m0 */
+					<1 RK_PA1 1 &pcfg_pull_up>,
+					/* uart3_tx_m0 */
+					<1 RK_PA0 1 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart3m1_xfer: uart3m1-xfer {
+				rockchip,pins =
+					/* uart3_rx_m1 */
+					<1 RK_PD1 5 &pcfg_pull_up>,
+					/* uart3_tx_m1 */
+					<1 RK_PD0 5 &pcfg_pull_up>;
+			};
+		};
+
+		uart4 {
+			/omit-if-no-ref/
+			uart4m0_xfer: uart4m0-xfer {
+				rockchip,pins =
+					/* uart4_rx_m0 */
+					<1 RK_PB0 1 &pcfg_pull_up>,
+					/* uart4_tx_m0 */
+					<1 RK_PB1 1 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart4m1_xfer: uart4m1-xfer {
+				rockchip,pins =
+					/* uart4_rx_m1 */
+					<1 RK_PC4 4 &pcfg_pull_up>,
+					/* uart4_tx_m1 */
+					<1 RK_PC5 4 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart4m1_ctsn: uart4m1-ctsn {
+				rockchip,pins =
+					/* uart4m1_ctsn */
+					<1 RK_PC7 4 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			uart4m1_rtsn: uart4m1-rtsn {
+				rockchip,pins =
+					/* uart4m1_rtsn */
+					<1 RK_PC6 4 &pcfg_pull_none>;
+			};
+		};
+
+		uart5 {
+			/omit-if-no-ref/
+			uart5m0_xfer: uart5m0-xfer {
+				rockchip,pins =
+					/* uart5_rx_m0 */
+					<3 RK_PA7 2 &pcfg_pull_up>,
+					/* uart5_tx_m0 */
+					<3 RK_PA6 2 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart5m0_ctsn: uart5m0-ctsn {
+				rockchip,pins =
+					/* uart5m0_ctsn */
+					<3 RK_PA5 2 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			uart5m0_rtsn: uart5m0-rtsn {
+				rockchip,pins =
+					/* uart5m0_rtsn */
+					<3 RK_PA4 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			uart5m1_xfer: uart5m1-xfer {
+				rockchip,pins =
+					/* uart5_rx_m1 */
+					<1 RK_PD2 4 &pcfg_pull_up>,
+					/* uart5_tx_m1 */
+					<1 RK_PD3 4 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart5m1_ctsn: uart5m1-ctsn {
+				rockchip,pins =
+					/* uart5m1_ctsn */
+					<1 RK_PD1 4 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			uart5m1_rtsn: uart5m1-rtsn {
+				rockchip,pins =
+					/* uart5m1_rtsn */
+					<1 RK_PD0 4 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			uart5m2_xfer: uart5m2-xfer {
+				rockchip,pins =
+					/* uart5_rx_m2 */
+					<3 RK_PD0 2 &pcfg_pull_up>,
+					/* uart5_tx_m2 */
+					<3 RK_PC7 2 &pcfg_pull_up>;
+			};
+
+			/omit-if-no-ref/
+			uart5m2_ctsn: uart5m2-ctsn {
+				rockchip,pins =
+					/* uart5m2_ctsn */
+					<3 RK_PD2 2 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			uart5m2_rtsn: uart5m2-rtsn {
+				rockchip,pins =
+					/* uart5m2_rtsn */
+					<3 RK_PD1 2 &pcfg_pull_none>;
+			};
+		};
+
+		vicap {
+			/omit-if-no-ref/
+			vicapm0_pins: vicapm0-pins {
+				rockchip,pins =
+					/* vicap_clkin_m0 */
+					<3 RK_PC2 1 &pcfg_pull_none>,
+					/* vicap_d0_m0 */
+					<3 RK_PB0 1 &pcfg_pull_none>,
+					/* vicap_d1_m0 */
+					<3 RK_PB1 1 &pcfg_pull_none>,
+					/* vicap_d2_m0 */
+					<3 RK_PB2 1 &pcfg_pull_none>,
+					/* vicap_d3_m0 */
+					<3 RK_PB3 1 &pcfg_pull_none>,
+					/* vicap_d4_m0 */
+					<3 RK_PB4 1 &pcfg_pull_none>,
+					/* vicap_d5_m0 */
+					<3 RK_PB5 1 &pcfg_pull_none>,
+					/* vicap_d6_m0 */
+					<3 RK_PB6 1 &pcfg_pull_none>,
+					/* vicap_d7_m0 */
+					<3 RK_PB7 1 &pcfg_pull_none>,
+					/* vicap_d8_m0 */
+					<3 RK_PC0 1 &pcfg_pull_none>,
+					/* vicap_d9_m0 */
+					<3 RK_PC1 1 &pcfg_pull_none>,
+					/* vicap_hsync_m0 */
+					<3 RK_PC3 1 &pcfg_pull_none>,
+					/* vicap_vsync_m0 */
+					<3 RK_PC5 1 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			vicapm1_pins: vicapm1-pins {
+				rockchip,pins =
+					/* vicap_clkin_m1 */
+					<1 RK_PD0 2 &pcfg_pull_none>,
+					/* vicap_d0_m1 */
+					<1 RK_PA2 3 &pcfg_pull_none>,
+					/* vicap_d1_m1 */
+					<1 RK_PB1 4 &pcfg_pull_none>,
+					/* vicap_d2_m1 */
+					<1 RK_PC0 2 &pcfg_pull_none>,
+					/* vicap_d3_m1 */
+					<1 RK_PC1 2 &pcfg_pull_none>,
+					/* vicap_d4_m1 */
+					<1 RK_PC2 2 &pcfg_pull_none>,
+					/* vicap_d5_m1 */
+					<1 RK_PC3 2 &pcfg_pull_none>,
+					/* vicap_d6_m1 */
+					<1 RK_PC4 2 &pcfg_pull_none>,
+					/* vicap_d7_m1 */
+					<1 RK_PC5 2 &pcfg_pull_none>,
+					/* vicap_d8_m1 */
+					<1 RK_PC6 2 &pcfg_pull_none>,
+					/* vicap_d9_m1 */
+					<1 RK_PC7 2 &pcfg_pull_none>,
+					/* vicap_hsync_m1 */
+					<1 RK_PD1 2 &pcfg_pull_none>,
+					/* vicap_vsync_m1 */
+					<1 RK_PD2 2 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			vicap_d10: vicap-d10 {
+				rockchip,pins =
+					/* vicap_d10 */
+					<3 RK_PC6 1 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			vicap_d11: vicap-d11 {
+				rockchip,pins =
+					/* vicap_d11 */
+					<3 RK_PC7 1 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			vicap_d12: vicap-d12 {
+				rockchip,pins =
+					/* vicap_d12 */
+					<3 RK_PD0 1 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			vicap_d13: vicap-d13 {
+				rockchip,pins =
+					/* vicap_d13 */
+					<3 RK_PD1 1 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			vicap_d14: vicap-d14 {
+				rockchip,pins =
+					/* vicap_d14 */
+					<3 RK_PD2 1 &pcfg_pull_none>;
+			};
+			/omit-if-no-ref/
+			vicap_d15: vicap-d15 {
+				rockchip,pins =
+					/* vicap_d15 */
+					<3 RK_PD3 1 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			vicap_clkout_m0: vicap-clkout-m0 {
+				rockchip,pins =
+					/* vicap_clkout_m0 */
+					<3 RK_PC4 1 &pcfg_pull_none>;
+			};
+
+			/omit-if-no-ref/
+			vicap_clkout_m1: vicap-clkout-m1 {
+				rockchip,pins =
+					/* vicap_clkout_m1 */
+					<1 RK_PD3 2 &pcfg_pull_none>;
+			};
+		};
+	};
+};
-- 
2.46.0

