colin/piezo-ddr-controller
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Lots of debugging stuff: works, but sample rate is low enough that it's not super useful

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Colin
2019-12-28 15:37:37 -08:00
parent 858618f41c
commit 2369db3657
1 changed files with 43 additions and 6 deletions
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49
src/main.rs
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@@ -112,7 +112,7 @@ extern crate panic_itm; // panic handler
mod bsp; mod bsp;
use cortex_m::iprintln; use cortex_m::{iprintln, itm};
use cortex_m::asm::{bkpt, delay}; use cortex_m::asm::{bkpt, delay};
use cortex_m_rt::entry; use cortex_m_rt::entry;
@@ -260,13 +260,50 @@ fn main() -> ! {
bkpt(); bkpt();
// We have 48 KBytes of ram
// But sizes >= 4096 seem to cause faults :s
let mut buffer = [0u8; 2048];
loop {
for sample in buffer.iter_mut() {
*sample = (per.adc1.dr.read().bits() >> 4) as u8;
}
itm::write_all(&mut per.itm.stim[0], &buffer);
//let avg_sample = (buffer.iter().map(|x| *x as u32).sum::<u32>() / buffer.len() as u32) as u16;
//if buffer.iter().any(|&s| s as u32 * 4 > avg_sample as u32 * 5 || s as u32 * 5 < avg_sample as u32 * 4) {
// // Dump the buffer:
// itm::write_all(&mut per.itm.stim[0], &buffer);
// //for sample in buffer.iter() {
// ////for i in 0..2048 {
// // //let data = (buffer[i] >> 4) as u32;
// // let data = (sample >> 4) as u8;
// // while !per.itm.stim[0].is_fifo_ready() {}
// // per.itm.stim[0].write_u8(data);
// // //per.itm.stim[0].write_u32(data | (data << 8) | (data << 16) | (data << 24));
// // //delay(10000);
// //}
//}
}
loop {
iprintln!(&mut per.itm.stim[0], "hello!");
}
loop { loop {
//let push_button = per.gpioa.idr.read().idr0().bit(); //let push_button = per.gpioa.idr.read().idr0().bit();
let push_button = per.gpiod.idr.read().idr0().bit(); //let push_button = per.gpiod.idr.read().idr0().bit();
per.gpioe.odr.modify(|_, w| { //per.gpioe.odr.modify(|_, w| {
w.odr8().bit(push_button) // w.odr8().bit(push_button)
}); //});
iprintln!(&mut per.itm.stim[0], "ADC: {:x}", per.adc1.dr.read().bits()); //iprintln!(&mut per.itm.stim[0], "ADC: {:x}", per.adc1.dr.read().bits());
//per.itm.stim[0].write_u32(per.adc1.dr.read().bits());
while !per.itm.stim[0].is_fifo_ready() {}
let adc = per.adc1.dr.read().bits();
//let data = adc as u16;
//per.itm.stim[0].write_u16(data);
let data = (adc >> 4) as u32;
//per.itm.stim[0].write_u8(data);
per.itm.stim[0].write_u32(data | (data << 8) | (data << 16) | (data << 24));
delay(1);
} }
} }