sh: cache: Fill in invalidate_icache_all()
Implement invalidate_icache_all() by clearing all V bits in IC and OC. This is done by setting CCR cache control register ICI and OCI bits. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> --- Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Tom Rini <trini@konsulko.com> Cc: u-boot@lists.denx.de
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@@ -33,8 +33,9 @@ static inline void cache_wback_all(void)
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}
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}
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}
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}
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#define CACHE_ENABLE 0
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#define CACHE_ENABLE 0
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#define CACHE_DISABLE 1
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#define CACHE_DISABLE 1
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#define CACHE_INVALIDATE 2
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static int cache_control(unsigned int cmd)
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static int cache_control(unsigned int cmd)
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{
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{
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@@ -46,7 +47,9 @@ static int cache_control(unsigned int cmd)
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if (ccr & CCR_CACHE_ENABLE)
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if (ccr & CCR_CACHE_ENABLE)
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cache_wback_all();
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cache_wback_all();
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if (cmd == CACHE_DISABLE)
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if (cmd == CACHE_INVALIDATE)
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outl(CCR_CACHE_ICI | ccr, CCR);
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else if (cmd == CACHE_DISABLE)
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outl(CCR_CACHE_STOP, CCR);
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outl(CCR_CACHE_STOP, CCR);
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else
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else
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outl(CCR_CACHE_INIT, CCR);
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outl(CCR_CACHE_INIT, CCR);
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@@ -103,7 +106,7 @@ void icache_disable(void)
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void invalidate_icache_all(void)
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void invalidate_icache_all(void)
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{
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{
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puts("No arch specific invalidate_icache_all available!\n");
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cache_control(CACHE_INVALIDATE);
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}
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}
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int icache_status(void)
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int icache_status(void)
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