Merge branch 'master' of ../master into next
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@@ -36,6 +36,7 @@
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_FEC_MXC
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extern void mx25_fec_init_pins(void);
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extern void imx_get_mac_from_fuse(unsigned char *mac);
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#endif
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/* Clock Control Module (CCM) registers */
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@@ -129,12 +130,17 @@ struct iim_regs {
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u32 iim_srev;
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u32 iim_prog_p;
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u32 res1[0x1f5];
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u32 iim_bank_area0[0x20];
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u32 res2[0xe0];
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u32 iim_bank_area1[0x20];
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u32 res3[0xe0];
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u32 iim_bank_area2[0x20];
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struct fuse_bank {
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u32 fuse_regs[0x20];
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u32 fuse_rsvd[0xe0];
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} bank[3];
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};
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struct fuse_bank0_regs {
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u32 fuse0_25[0x1a];
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u32 mac_addr[6];
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};
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#endif
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/* AIPS 1 */
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@@ -312,7 +318,4 @@ struct iim_regs {
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#define WSR_UNLOCK1 0x5555
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#define WSR_UNLOCK2 0xAAAA
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/* FUSE bank offsets */
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#define IIM0_MAC 0x1a
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#endif /* _IMX_REGS_H */
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@@ -34,6 +34,7 @@ extern void mx27_uart_init_pins(void);
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#ifdef CONFIG_FEC_MXC
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extern void mx27_fec_init_pins(void);
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extern void imx_get_mac_from_fuse(unsigned char *mac);
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#endif /* CONFIG_FEC_MXC */
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#ifdef CONFIG_MXC_MMC
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@@ -202,9 +203,19 @@ struct iim_regs {
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u32 iim_scs1;
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u32 iim_scs2;
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u32 iim_scs3;
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u32 res[0x1F0];
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u32 iim_bank_area0[0x100];
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u32 res[0x1f1];
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struct fuse_bank {
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u32 fuse_regs[0x20];
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u32 fuse_rsvd[0xe0];
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} bank[1];
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};
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struct fuse_bank0_regs {
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u32 fuse0_3[5];
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u32 mac_addr[6];
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u32 fuse10_31[0x16];
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};
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#endif
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#define IMX_IO_BASE 0x10000000
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@@ -512,9 +523,4 @@ struct iim_regs {
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#define IIM_ERR_SNSE (1 << 2)
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#define IIM_ERR_PARITYE (1 << 1)
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/* Definitions for i.MX27 TO2 */
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#define IIM0_MAC 5
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#define IIM0_SCC_KEY 11
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#define IIM1_SUID 1
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#endif /* _IMX_REGS_H */
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@@ -205,9 +205,13 @@
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#define BOARD_REV_1_0 0x0
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#define BOARD_REV_2_0 0x1
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#define IMX_IIM_BASE (IIM_BASE_ADDR)
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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extern void imx_get_mac_from_fuse(unsigned char *mac);
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#define __REG(x) (*((volatile u32 *)(x)))
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#define __REG16(x) (*((volatile u16 *)(x)))
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#define __REG8(x) (*((volatile u8 *)(x)))
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@@ -275,6 +279,36 @@ struct src {
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u32 sisr;
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u32 simr;
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};
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struct iim_regs {
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u32 stat;
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u32 statm;
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u32 err;
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u32 emask;
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u32 fctl;
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u32 ua;
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u32 la;
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u32 sdat;
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u32 prev;
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u32 srev;
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u32 preg_p;
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u32 scs0;
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u32 scs1;
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u32 scs2;
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u32 scs3;
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u32 res0[0x1f1];
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struct fuse_bank {
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u32 fuse_regs[0x20];
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u32 fuse_rsvd[0xe0];
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} bank[4];
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};
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struct fuse_bank1_regs {
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u32 fuse0_8[9];
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u32 mac_addr[6];
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u32 fuse15_31[0x11];
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};
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#endif /* __ASSEMBLER__*/
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#endif /* __ASM_ARCH_MXC_MX51_H__ */
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@@ -55,11 +55,14 @@ typedef struct global_data {
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unsigned long plla_rate_hz;
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unsigned long pllb_rate_hz;
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unsigned long at91_pllb_usb_init;
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/* "static data" needed by at91's timer.c */
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#endif
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#ifdef CONFIG_ARM
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/* "static data" needed by most of timer.c on ARM platforms */
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unsigned long timer_rate_hz;
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unsigned long tbl;
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unsigned long tbu;
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unsigned long long timer_reset_value;
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unsigned long lastinc;
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#endif
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unsigned long relocaddr; /* Start address of U-Boot in RAM */
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phys_size_t ram_size; /* RAM size */
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