Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next

- Disable CMD_IRQ for RISC-V.
- Update sipeed/maix doc
- Obtain reg of SiFive RAM via dev_read_addr_index() instead of regmap API.
- Cleans up RISC-V timer drivers and converts them to DM.
- Correctly handle IPIs already pending upon prior stage bootloader (on the K210)

drivers/clk/kendryte/clk.c

@@ -646,6 +646,10 @@ static int k210_clk_probe(struct udevice *dev)
 	REGISTER_GATE(K210_CLK_RTC,   "rtc",   in0);
 #undef REGISTER_GATE
 
+	/* The MTIME register in CLINT runs at one 50th the CPU clock speed */
+	clk_dm(K210_CLK_CLINT,
+	       clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
+
 	return 0;
 }
 

drivers/cpu/cpu_sandbox.c

@@ -8,14 +8,15 @@
 #include <dm.h>
 #include <cpu.h>
 
-int cpu_sandbox_get_desc(const struct udevice *dev, char *buf, int size)
+static int cpu_sandbox_get_desc(const struct udevice *dev, char *buf, int size)
 {
 	snprintf(buf, size, "LEG Inc. SuperMegaUltraTurbo CPU No. 1");
 
 	return 0;
 }
 
-int cpu_sandbox_get_info(const struct udevice *dev, struct cpu_info *info)
+static int cpu_sandbox_get_info(const struct udevice *dev,
+				struct cpu_info *info)
 {
 	info->cpu_freq = 42 * 42 * 42 * 42 * 42;
 	info->features = 0x42424242;
@@ -24,21 +25,29 @@ int cpu_sandbox_get_info(const struct udevice *dev, struct cpu_info *info)
 	return 0;
 }
 
-int cpu_sandbox_get_count(const struct udevice *dev)
+static int cpu_sandbox_get_count(const struct udevice *dev)
 {
 	return 42;
 }
 
-int cpu_sandbox_get_vendor(const struct udevice *dev, char *buf, int size)
+static int cpu_sandbox_get_vendor(const struct udevice *dev, char *buf,
+				  int size)
 {
 	snprintf(buf, size, "Languid Example Garbage Inc.");
 
 	return 0;
 }
 
-int cpu_sandbox_is_current(struct udevice *dev)
+static const char *cpu_current = "cpu-test1";
+
+void cpu_sandbox_set_current(const char *name)
 {
-	if (!strcmp(dev->name, "cpu-test1"))
+	cpu_current = name;
+}
+
+static int cpu_sandbox_is_current(struct udevice *dev)
+{
+	if (!strcmp(dev->name, cpu_current))
 		return 1;
 
 	return 0;
@@ -52,7 +61,22 @@ static const struct cpu_ops cpu_sandbox_ops = {
 	.is_current = cpu_sandbox_is_current,
 };
 
-int cpu_sandbox_probe(struct udevice *dev)
+static int cpu_sandbox_bind(struct udevice *dev)
+{
+	int ret;
+	struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+
+	/* first examine the property in current cpu node */
+	ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
+	/* if not found, then look at the parent /cpus node */
+	if (ret)
+		ret = dev_read_u32(dev->parent, "timebase-frequency",
+				   &plat->timebase_freq);
+
+	return ret;
+}
+
+static int cpu_sandbox_probe(struct udevice *dev)
 {
 	return 0;
 }
@@ -67,5 +91,6 @@ U_BOOT_DRIVER(cpu_sandbox) = {
 	.id             = UCLASS_CPU,
 	.ops		= &cpu_sandbox_ops,
 	.of_match       = cpu_sandbox_ids,
+	.bind		= cpu_sandbox_bind,
 	.probe          = cpu_sandbox_probe,
 };

drivers/ram/sifive/fu540_ddr.c

@@ -11,7 +11,6 @@
 #include <fdtdec.h>
 #include <init.h>
 #include <ram.h>
-#include <regmap.h>
 #include <syscon.h>
 #include <asm/io.h>
 #include <clk.h>
@@ -339,17 +338,12 @@ static int fu540_ddr_probe(struct udevice *dev)
 	priv->info.size = gd->ram_size;
 
 #if defined(CONFIG_SPL_BUILD)
-	struct regmap *map;
 	int ret;
 	u32 clock = 0;
 
 	debug("FU540 DDR probe\n");
 	priv->dev = dev;
 
-	ret = regmap_init_mem(dev_ofnode(dev), &map);
-	if (ret)
-		return ret;
-
 	ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
 	if (ret) {
 		debug("clk get failed %d\n", ret);
@@ -369,9 +363,14 @@ static int fu540_ddr_probe(struct udevice *dev)
 	}
 
 	ret = clk_enable(&priv->ddr_clk);
-	priv->ctl = regmap_get_range(map, 0);
-	priv->phy = regmap_get_range(map, 1);
-	priv->physical_filter_ctrl = regmap_get_range(map, 2);
+	if (ret < 0) {
+		debug("Could not enable DDR clock\n");
+		return ret;
+	}
+
+	priv->ctl = (struct fu540_ddrctl *)dev_read_addr_index(dev, 0);
+	priv->phy = (struct fu540_ddrphy *)dev_read_addr_index(dev, 1);
+	priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2);
 
 	return fu540_ddr_setup(dev);
 #endif

drivers/timer/Kconfig

@@ -146,8 +146,8 @@ config RISCV_TIMER
 	bool "RISC-V timer support"
 	depends on TIMER && RISCV
 	help
-	  Select this to enable support for the timer as defined
-	  by the RISC-V privileged architecture spec.
+	  Select this to enable support for a generic RISC-V S-Mode timer
+	  driver.
 
 config ROCKCHIP_TIMER
 	bool "Rockchip timer support"

drivers/timer/riscv_timer.c

@@ -1,36 +1,37 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2018, Anup Patel <anup@brainfault.org>
+ * Copyright (C) 2012 Regents of the University of California
  *
- * RISC-V privileged architecture defined generic timer driver
+ * RISC-V architecturally-defined generic timer driver
  *
- * This driver relies on RISC-V platform codes to provide the essential API
- * riscv_get_time() which is supposed to return the timer counter as defined
- * by the RISC-V privileged architecture spec.
- *
- * This driver can be used in both M-mode and S-mode U-Boot.
+ * This driver provides generic timer support for S-mode U-Boot.
  */
 
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
 #include <timer.h>
-#include <asm/io.h>
-
-/**
- * riscv_get_time() - get the timer counter
- *
- * Platform codes should provide this API in order to make this driver function.
- *
- * @time:	the 64-bit timer count  as defined by the RISC-V privileged
- *		architecture spec.
- * @return:	0 on success, -ve on error.
- */
-extern int riscv_get_time(u64 *time);
+#include <asm/csr.h>
 
 static int riscv_timer_get_count(struct udevice *dev, u64 *count)
 {
-	return riscv_get_time(count);
+	if (IS_ENABLED(CONFIG_64BIT)) {
+		*count = csr_read(CSR_TIME);
+	} else {
+		u32 hi, lo;
+
+		do {
+			hi = csr_read(CSR_TIMEH);
+			lo = csr_read(CSR_TIME);
+		} while (hi != csr_read(CSR_TIMEH));
+
+		*count = ((u64)hi << 32) | lo;
+	}
+
+	return 0;
 }
 
 static int riscv_timer_probe(struct udevice *dev)

drivers/timer/sandbox_timer.c

@@ -40,7 +40,9 @@ static int sandbox_timer_probe(struct udevice *dev)
 {
 	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 
-	if (!uc_priv->clock_rate)
+	if (dev_read_bool(dev, "sandbox,timebase-frequency-fallback"))
+		return timer_timebase_fallback(dev);
+	else if (!uc_priv->clock_rate)
 		uc_priv->clock_rate = SANDBOX_TIMER_RATE;
 
 	return 0;

drivers/timer/timer-uclass.c

@@ -4,6 +4,7 @@
  */
 
 #include <common.h>
+#include <cpu.h>
 #include <dm.h>
 #include <init.h>
 #include <dm/lists.h>
@@ -79,6 +80,36 @@ static int timer_post_probe(struct udevice *dev)
 	return 0;
 }
 
+/*
+ * TODO: should be CONFIG_IS_ENABLED(CPU), but the SPL config has _SUPPORT on
+ * the end...
+ */
+#if defined(CONFIG_CPU) || defined(CONFIG_SPL_CPU_SUPPORT)
+int timer_timebase_fallback(struct udevice *dev)
+{
+	struct udevice *cpu;
+	struct cpu_platdata *cpu_plat;
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+	/* Did we get our clock rate from the device tree? */
+	if (uc_priv->clock_rate)
+		return 0;
+
+	/* Fall back to timebase-frequency */
+	dev_dbg(dev, "missing clocks or clock-frequency property; falling back on timebase-frequency\n");
+	cpu = cpu_get_current_dev();
+	if (!cpu)
+		return -ENODEV;
+
+	cpu_plat = dev_get_parent_platdata(cpu);
+	if (!cpu_plat)
+		return -ENODEV;
+
+	uc_priv->clock_rate = cpu_plat->timebase_freq;
+	return 0;
+}
+#endif
+
 u64 timer_conv_64(u32 count)
 {
 	/* increment tbh if tbl has rolled over */