Merge https://source.denx.de/u-boot/custodians/u-boot-sh

- A few clean ups for the RZG2

arch/arm/dts/beacon-renesom-baseboard.dtsi

@@ -197,6 +197,14 @@
 		compatible = "audio-graph-card";
 		label = "rcar-sound";
 		dais = <&rsnd_port0>, <&rsnd_port1>;
+		widgets = "Microphone", "Mic Jack",
+			  "Line", "Line In Jack",
+			  "Headphone", "Headphone Jack";
+		mic-det-gpio = <&gpio0 2 GPIO_ACTIVE_LOW>;
+		routing = "Headphone Jack", "HPOUTL",
+			 "Headphone Jack", "HPOUTR",
+			 "IN3R", "MICBIAS",
+			 "Mic Jack", "IN3R";
 	};
 
 	vccq_sdhi0: regulator-vccq-sdhi0 {
@@ -271,12 +279,12 @@
 &ehci0 {
 	dr_mode = "otg";
 	status = "okay";
-	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
 };
 
 &ehci1 {
 	status = "okay";
-	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
 };
 
 &hdmi0 {
@@ -615,7 +623,7 @@
 };
 
 &rcar_sound {
-	pinctrl-0 = <&sound_pins &sound_clk_pins>;
+	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
 	pinctrl-names = "default";
 
 	/* Single DAI */
@@ -639,7 +647,7 @@
 				bitclock-master = <&rsnd_endpoint0>;
 				frame-master = <&rsnd_endpoint0>;
 
-				playback = <&ssi1 &dvc1 &src1>;
+				playback = <&ssi1>, <&dvc1>, <&src1>;
 				capture = <&ssi0>;
 			};
 		};

arch/arm/dts/beacon-renesom-som.dtsi

@@ -7,19 +7,10 @@
 #include <dt-bindings/clk/versaclock.h>
 
 / {
-	aliases {
-		spi0 = &rpc;
-	};
-
 	memory@48000000 {
 		device_type = "memory";
 		/* first 128MB is reserved for secure area. */
-		reg = <0x0 0x48000000 0x0 0xc000000>;
+		reg = <0x0 0x48000000 0x0 0x78000000>;
-	};
-
-	memory@57000000 {
-		device_type = "memory";
-		reg = <0x0 0x57000000 0x0 0x29000000>;
 	};
 
 	osc_32k: osc_32k {
@@ -59,12 +50,17 @@
 &avb {
 	pinctrl-0 = <&avb_pins>;
 	pinctrl-names = "default";
+	phy-mode = "rgmii-rxid";
 	phy-handle = <&phy0>;
 	rx-internal-delay-ps = <1800>;
 	tx-internal-delay-ps = <2000>;
+	clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
+	clock-names = "fck", "refclk";
 	status = "okay";
 
 	phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id004d.d074",
+			     "ethernet-phy-ieee802.3-c22";
 		reg = <0>;
 		interrupt-parent = <&gpio2>;
 		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
@@ -153,7 +149,7 @@
 	};
 
 	eeprom@50 {
-		compatible = "microchip,at24c64", "atmel,24c64";
+		compatible = "microchip,24c64", "atmel,24c64";
 		pagesize = <32>;
 		read-only;	/* Manufacturing EEPROM programmed at factory */
 		reg = <0x50>;
@@ -279,25 +275,6 @@
 	};
 };
 
-&rpc {
-	compatible = "renesas,rcar-gen3-rpc";
-	num-cs = <1>;
-	spi-max-frequency = <40000000>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-
-	flash0: spi-flash@0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		reg = <0>;
-		compatible = "spi-flash", "jedec,spi-nor";
-		spi-max-frequency = <40000000>;
-		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <1>;
-	};
-};
-
 &scif_clk {
 	clock-frequency = <14745600>;
 };
@@ -340,17 +317,17 @@
 	vqmmc-supply = <&reg_1p8v>;
 	bus-width = <8>;
 	mmc-hs200-1_8v;
+	no-sd;
+	no-sdio;
 	non-removable;
 	fixed-emmc-driver-type = <1>;
 	status = "okay";
 };
 
 &usb2_clksel {
-	status = "okay";
 	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
 		  <&versaclock5 3>, <&usb3s0_clk>;
-	clock-names = "ehci_ohci", "hs-usb-if",
+	status = "okay";
-		      "usb_extal", "usb_xtal";
 };
 
 &usb3s0_clk {

arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi

@@ -1,34 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
  */
 
-/ {
+#include "rz-g2-beacon-u-boot.dtsi"
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
-&cpg {
-	u-boot,dm-pre-reloc;
-};
-
-&extal_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&prr {
-	u-boot,dm-pre-reloc;
-};
-
-&extalr_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&sdhi0 {
-	/delete-property/ cd-gpios;
-};
-
-&sdhi2 {
-	status = "disabled";
-};

arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts

@@ -21,6 +21,9 @@
 		serial4 = &hscif2;
 		serial5 = &scif5;
 		ethernet0 = &avb;
+		mmc0 = &sdhi3;
+		mmc1 = &sdhi0;
+		mmc2 = &sdhi2;
 	};
 
 	chosen {

arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi

@@ -1,34 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
  */
 
-/ {
+#include "rz-g2-beacon-u-boot.dtsi"
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
-&cpg {
-	u-boot,dm-pre-reloc;
-};
-
-&extal_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&prr {
-	u-boot,dm-pre-reloc;
-};
-
-&extalr_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&sdhi0 {
-	/delete-property/ cd-gpios;
-};
-
-&sdhi2 {
-	status = "disabled";
-};

arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts

@@ -22,6 +22,9 @@
 		serial5 = &scif5;
 		serial6 = &scif4;
 		ethernet0 = &avb;
+		mmc0 = &sdhi3;
+		mmc1 = &sdhi0;
+		mmc2 = &sdhi2;
 	};
 
 	chosen {

arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi

@@ -1,44 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright 2020 Compass Electronics Group, LLC
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
  */
 
-/ {
+#include "rz-g2-beacon-u-boot.dtsi"
-	soc {
-		u-boot,dm-pre-reloc;
-	};
-};
-
-&cpg {
-	u-boot,dm-pre-reloc;
-};
-
-&extal_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&prr {
-	u-boot,dm-pre-reloc;
-};
-
-&extalr_clk {
-	u-boot,dm-pre-reloc;
-};
-
-&sdhi0 {
-	/delete-property/ cd-gpios;
-	sd-uhs-sdr12;
-	sd-uhs-sdr25;
-	sd-uhs-sdr104;
-	max-frequency = <208000000>;
-};
-
-&sdhi2 {
-	status = "disabled";
-};
-
-&sdhi3 {
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	mmc-hs400-1_8v;
-};

arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts

@@ -22,6 +22,9 @@
 		serial5 = &scif5;
 		serial6 = &scif4;
 		ethernet0 = &avb;
+		mmc0 = &sdhi3;
+		mmc1 = &sdhi0;
+		mmc2 = &sdhi2;
 	};
 
 	chosen {

arch/arm/dts/rz-g2-beacon-u-boot.dtsi

@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2021 LogicPD dba Beacon EmbeddedWorks
+ */
+
+/ {
+	aliases {
+		spi0 = &rpc;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&cpg {
+	u-boot,dm-pre-reloc;
+};
+
+&ehci0 {
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+};
+
+&ehci1 {
+	clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&versaclock5 3>;
+};
+
+&extal_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&extalr_clk {
+	u-boot,dm-pre-reloc;
+};
+
+&prr {
+	u-boot,dm-pre-reloc;
+};
+
+&rpc {
+	compatible = "renesas,rcar-gen3-rpc";
+	num-cs = <1>;
+	spi-max-frequency = <40000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	flash0: spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		compatible = "spi-flash", "jedec,spi-nor";
+		spi-max-frequency = <40000000>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <1>;
+	};
+};
+
+&sdhi0 {
+	/delete-property/ cd-gpios;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr104;
+	max-frequency = <208000000>;
+};
+
+&sdhi2 {
+	status = "disabled";
+};
+
+&sdhi3 {
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+};

board/beacon/beacon-rzg2m/MAINTAINERS

@@ -4,3 +4,13 @@ S:	Maintained
 F:	board/beacon/beacon-rzg2m/
 F:	include/configs/beacon-rzg2m.h
 F:	configs/rzg2_beacon_defconfig
+F:	arch/arm/dts/beacon-renesom-baseboard.dtsi
+F:	arch/arm/dts/beacon-renesom-som.dtsi
+F:	arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts
+F:	arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
+F:	arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
+F:	arch/arm/dts/r8a774a1-beacon-rzg2m-kit-u-boot.dtsi
+F:	arch/arm/dts/r8a774b1-beacon-rzg2n-kit-u-boot.dtsi
+F:	arch/arm/dts/r8a774e1-beacon-rzg2h-kit-u-boot.dtsi
+F:	arch/arm/dts/rz-g2-beacon-u-boot.dtsi
+

configs/rzg2_beacon_defconfig

@@ -39,7 +39,6 @@ CONFIG_MULTI_DTB_FIT_LZO=y
 CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_SYS_MMC_ENV_PART=2
 CONFIG_VERSION_VARIABLE=y
 CONFIG_REGMAP=y

drivers/net/ravb.c

@@ -129,7 +129,7 @@ struct ravb_priv {
 	struct phy_device	*phydev;
 	struct mii_dev		*bus;
 	void __iomem		*iobase;
-	struct clk		clk;
+	struct clk_bulk		clks;
 	struct gpio_desc	reset_gpio;
 };
 
@@ -485,7 +485,7 @@ static int ravb_probe(struct udevice *dev)
 	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
 	eth->iobase = iobase;
 
-	ret = clk_get_by_index(dev, 0, &eth->clk);
+	ret = clk_get_bulk(dev, &eth->clks);
 	if (ret < 0)
 		goto err_mdio_alloc;
 
@@ -518,7 +518,7 @@ static int ravb_probe(struct udevice *dev)
 	eth->bus = miiphy_get_dev_by_name(dev->name);
 
 	/* Bring up PHY */
-	ret = clk_enable(&eth->clk);
+	ret = clk_enable_bulk(&eth->clks);
 	if (ret)
 		goto err_mdio_register;
 
@@ -533,7 +533,7 @@ static int ravb_probe(struct udevice *dev)
 	return 0;
 
 err_mdio_reset:
-	clk_disable(&eth->clk);
+	clk_release_bulk(&eth->clks);
 err_mdio_register:
 	mdio_free(mdiodev);
 err_mdio_alloc:
@@ -545,7 +545,7 @@ static int ravb_remove(struct udevice *dev)
 {
 	struct ravb_priv *eth = dev_get_priv(dev);
 
-	clk_disable(&eth->clk);
+	clk_release_bulk(&eth->clks);
 
 	free(eth->phydev);
 	mdio_unregister(eth->bus);

include/configs/beacon-rzg2m.h

@@ -23,7 +23,7 @@
 	"boot_fdt=try\0" \
 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	"initrd_addr=0x43800000\0"		\
-	"mmcdev=0\0" \
+	"mmcdev=1\0" \
 	"mmcpart=1\0" \
 	"mmcrootpart=2\0" \
 	"finduuid=part uuid mmc ${mmcdev}:${mmcrootpart} uuid\0" \