Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc1 v2 xilinx: - Allow booting bigger kernels till 100MB zynqmp: - DT updates (reset IDs) - Remove unneeded low level uart initialization from psu_init* - Enable PWM features - Add support for 1EG device serial_zynq: - Change fifo behavior in DEBUG mode zynq_sdhci: - Fix BASECLK setting calculation clk_zynqmp: - Add support for showing video clock gpio: - Update slg driver to handle DT flags net: - Update ethernet_id code to support also DM_ETH_PHY - Add support for DM_ETH_PHY in gem driver - Enable dynamic mode for SGMII config in gem driver pwm: - Add driver for cadence PWM versal: - Add support for reserved memory firmware: - Handle PD enabling for SPL - Add support for IOUSLCR SGMII configurations include: - Sync phy.h with Linux - Update xilinx power domain dt binding headers
This commit is contained in:
Tom Rini
@@ -23,6 +23,13 @@ config PWM_AT91
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help
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Support for PWM hardware on AT91 based SoC.
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config PWM_CADENCE_TTC
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bool "Enable support for the Cadence TTC PWM"
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depends on DM_PWM && !CADENCE_TTC_TIMER
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help
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Cadence TTC can be configured as timer which is done via
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CONFIG_CADENCE_TTC_TIMER or as PWM. This is covering only PWM now.
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config PWM_CROS_EC
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bool "Enable support for the Chrome OS EC PWM"
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depends on DM_PWM
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@@ -12,6 +12,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o
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obj-$(CONFIG_PWM_ASPEED) += pwm-aspeed.o
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obj-$(CONFIG_PWM_AT91) += pwm-at91.o
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obj-$(CONFIG_PWM_CADENCE_TTC) += pwm-cadence-ttc.o
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obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o
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obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o
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obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o
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261
drivers/pwm/pwm-cadence-ttc.c
Normal file
261
drivers/pwm/pwm-cadence-ttc.c
Normal file
@@ -0,0 +1,261 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2021 Xilinx, Inc. Michal Simek
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*/
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#define LOG_CATEGORY UCLASS_PWM
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#include <clk.h>
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <log.h>
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#include <pwm.h>
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#include <asm/io.h>
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#include <log.h>
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#include <div64.h>
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#include <linux/bitfield.h>
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#include <linux/math64.h>
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#include <linux/log2.h>
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#include <dm/device_compat.h>
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#define CLOCK_CONTROL 0
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#define COUNTER_CONTROL 0xc
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#define INTERVAL_COUNTER 0x24
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#define MATCH_1_COUNTER 0x30
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#define CLK_FALLING_EDGE BIT(6)
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#define CLK_SRC_EXTERNAL BIT(5)
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#define CLK_PRESCALE_MASK GENMASK(4, 1)
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#define CLK_PRESCALE_ENABLE BIT(0)
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#define COUNTER_WAVE_POL BIT(6)
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#define COUNTER_WAVE_DISABLE BIT(5)
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#define COUNTER_RESET BIT(4)
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#define COUNTER_MATCH_ENABLE BIT(3)
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#define COUNTER_DECREMENT_ENABLE BIT(2)
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#define COUNTER_INTERVAL_ENABLE BIT(1)
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#define COUNTER_COUNTING_DISABLE BIT(0)
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#define NSEC_PER_SEC 1000000000L
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#define TTC_REG(reg, channel) ((reg) + (channel) * sizeof(u32))
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#define TTC_CLOCK_CONTROL(reg, channel) \
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TTC_REG((reg) + CLOCK_CONTROL, (channel))
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#define TTC_COUNTER_CONTROL(reg, channel) \
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TTC_REG((reg) + COUNTER_CONTROL, (channel))
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#define TTC_INTERVAL_COUNTER(reg, channel) \
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TTC_REG((reg) + INTERVAL_COUNTER, (channel))
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#define TTC_MATCH_1_COUNTER(reg, channel) \
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TTC_REG((reg) + MATCH_1_COUNTER, (channel))
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struct cadence_ttc_pwm_plat {
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u8 *regs;
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u32 timer_width;
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};
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struct cadence_ttc_pwm_priv {
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u8 *regs;
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u32 timer_width;
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u32 timer_mask;
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unsigned long frequency;
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bool invert[2];
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};
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static int cadence_ttc_pwm_set_invert(struct udevice *dev, uint channel,
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bool polarity)
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{
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struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
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if (channel > 2) {
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dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
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return -EINVAL;
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}
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priv->invert[channel] = polarity;
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dev_dbg(dev, "polarity=%u. Please config PWM again\n", polarity);
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return 0;
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}
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static int cadence_ttc_pwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
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u32 counter_ctrl, clock_ctrl;
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int period_clocks, duty_clocks, prescaler;
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dev_dbg(dev, "channel %d, duty %d/period %d ns\n", channel,
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duty_ns, period_ns);
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if (channel > 2) {
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dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
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return -EINVAL;
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}
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/* Make sure counter is stopped */
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counter_ctrl = readl(TTC_COUNTER_CONTROL(priv->regs, channel));
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setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
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COUNTER_COUNTING_DISABLE | COUNTER_WAVE_DISABLE);
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/* Calculate period, prescaler and set clock control register */
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period_clocks = div64_u64(((int64_t)period_ns * priv->frequency),
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NSEC_PER_SEC);
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prescaler = ilog2(period_clocks) + 1 - priv->timer_width;
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if (prescaler < 0)
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prescaler = 0;
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clock_ctrl = readl(TTC_CLOCK_CONTROL(priv->regs, channel));
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if (!prescaler) {
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clock_ctrl &= ~(CLK_PRESCALE_ENABLE | CLK_PRESCALE_MASK);
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} else {
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clock_ctrl &= ~CLK_PRESCALE_MASK;
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clock_ctrl |= CLK_PRESCALE_ENABLE;
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clock_ctrl |= FIELD_PREP(CLK_PRESCALE_MASK, prescaler - 1);
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};
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/* External source is not handled by this driver now */
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clock_ctrl &= ~CLK_SRC_EXTERNAL;
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writel(clock_ctrl, TTC_CLOCK_CONTROL(priv->regs, channel));
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/* Calculate interval and set counter control value */
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duty_clocks = div64_u64(((int64_t)duty_ns * priv->frequency),
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NSEC_PER_SEC);
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writel((period_clocks >> prescaler) & priv->timer_mask,
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TTC_INTERVAL_COUNTER(priv->regs, channel));
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writel((duty_clocks >> prescaler) & priv->timer_mask,
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TTC_MATCH_1_COUNTER(priv->regs, channel));
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/* Restore/reset counter */
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counter_ctrl &= ~COUNTER_DECREMENT_ENABLE;
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counter_ctrl |= COUNTER_INTERVAL_ENABLE |
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COUNTER_RESET |
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COUNTER_MATCH_ENABLE;
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if (priv->invert[channel])
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counter_ctrl |= COUNTER_WAVE_POL;
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else
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counter_ctrl &= ~COUNTER_WAVE_POL;
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writel(counter_ctrl, TTC_COUNTER_CONTROL(priv->regs, channel));
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dev_dbg(dev, "%d/%d clocks, prescaler 2^%d\n", duty_clocks,
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period_clocks, prescaler);
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return 0;
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};
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static int cadence_ttc_pwm_set_enable(struct udevice *dev, uint channel,
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bool enable)
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{
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struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
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if (channel > 2) {
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dev_err(dev, "Unsupported channel number %d(max 2)\n", channel);
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return -EINVAL;
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}
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dev_dbg(dev, "Enable: %d, channel %d\n", enable, channel);
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if (enable) {
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clrbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
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COUNTER_COUNTING_DISABLE |
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COUNTER_WAVE_DISABLE);
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setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
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COUNTER_RESET);
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} else {
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setbits_le32(TTC_COUNTER_CONTROL(priv->regs, channel),
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COUNTER_COUNTING_DISABLE |
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COUNTER_WAVE_DISABLE);
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}
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return 0;
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};
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static int cadence_ttc_pwm_probe(struct udevice *dev)
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{
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struct cadence_ttc_pwm_priv *priv = dev_get_priv(dev);
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struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
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struct clk clk;
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int ret;
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priv->regs = plat->regs;
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priv->timer_width = plat->timer_width;
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priv->timer_mask = GENMASK(priv->timer_width - 1, 0);
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret < 0) {
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dev_err(dev, "failed to get clock\n");
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return ret;
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}
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priv->frequency = clk_get_rate(&clk);
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if (IS_ERR_VALUE(priv->frequency)) {
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dev_err(dev, "failed to get rate\n");
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return priv->frequency;
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}
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dev_dbg(dev, "Clk frequency: %ld\n", priv->frequency);
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ret = clk_enable(&clk);
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if (ret) {
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dev_err(dev, "failed to enable clock\n");
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return ret;
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}
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return 0;
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}
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static int cadence_ttc_pwm_of_to_plat(struct udevice *dev)
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{
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struct cadence_ttc_pwm_plat *plat = dev_get_plat(dev);
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const char *cells;
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cells = dev_read_prop(dev, "#pwm-cells", NULL);
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if (!cells)
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return -EINVAL;
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plat->regs = dev_read_addr_ptr(dev);
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plat->timer_width = dev_read_u32_default(dev, "timer-width", 16);
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return 0;
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}
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static int cadence_ttc_pwm_bind(struct udevice *dev)
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{
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const char *cells;
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cells = dev_read_prop(dev, "#pwm-cells", NULL);
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if (!cells)
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return -ENODEV;
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return 0;
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}
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static const struct pwm_ops cadence_ttc_pwm_ops = {
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.set_invert = cadence_ttc_pwm_set_invert,
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.set_config = cadence_ttc_pwm_set_config,
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.set_enable = cadence_ttc_pwm_set_enable,
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};
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static const struct udevice_id cadence_ttc_pwm_ids[] = {
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{ .compatible = "cdns,ttc" },
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{ }
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};
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U_BOOT_DRIVER(cadence_ttc_pwm) = {
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.name = "cadence_ttc_pwm",
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.id = UCLASS_PWM,
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.of_match = cadence_ttc_pwm_ids,
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.ops = &cadence_ttc_pwm_ops,
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.bind = cadence_ttc_pwm_bind,
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.of_to_plat = cadence_ttc_pwm_of_to_plat,
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.probe = cadence_ttc_pwm_probe,
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.priv_auto = sizeof(struct cadence_ttc_pwm_priv),
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.plat_auto = sizeof(struct cadence_ttc_pwm_plat),
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};
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