colin/u-boot
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4

Browse Source 
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.

Also check dimm size and rank size for memory controller interleaving

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
york
2010-07-02 22:25:52 +00:00
committed by Kumar Gala
parent 79e4e6480b
commit 076bff8f47
7 changed files with 190 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
doc/README.fsl-ddr
View File

@@ -27,6 +27,9 @@ Table of interleaving modes supported in cpu/8xxx/ddr/
from each controller. {CS2+CS3} on each controller are only rank
interleaved on that controller.
For memory controller interleaving, identical DIMMs are suggested. Software
doesn't check the size or organization of interleaved DIMMs.
The ways to configure the ddr interleaving mode
==============================================
1. In board header file(e.g.MPC8572DS.h), add default interleaving setting