TI:omap5: Clarify comments about SPL and DDR timings in common config
Signed-off-by: Tom Rini <trini@ti.com>
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@@ -28,9 +28,12 @@
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/* Use General purpose timer 1 */
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/* Use General purpose timer 1 */
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#define CONFIG_SYS_TIMERBASE GPT2_BASE
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#define CONFIG_SYS_TIMERBASE GPT2_BASE
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/*
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* For the DDR timing information we can either dynamically determine
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* the timings to use or use pre-determined timings (based on using the
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* dynamic method. Default to the static timing infomation.
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*/
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#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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/* Defines for SDRAM init */
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#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
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#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
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#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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@@ -127,7 +130,13 @@
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"fi"
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"fi"
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/* Defines for SPL */
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/*
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* SPL related defines. The Public RAM memory map the ROM defines the
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* area between 0x40300000 and 0x4031E000 as a download area for OMAP5
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* (dra7xx is larger, but we do not need to be larger at this time). We
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* set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and
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* print some information.
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*/
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#define CONFIG_SPL_TEXT_BASE 0x40300000
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#define CONFIG_SPL_TEXT_BASE 0x40300000
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#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE)
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#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE)
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#define CONFIG_SPL_DISPLAY_PRINT
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#define CONFIG_SPL_DISPLAY_PRINT
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