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Merge patch series "Inline ECC Series"

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Santhosh Kumar K <s-k6@ti.com> says:

Hello,

This series adds support for Inline ECC in DDR for AM64X, AM62X,
AM62AX, AM62PX, J721E, J721S2, J722S and J784S4 devices.

Test Results: https://gist.github.com/santhosh21/88de920771ed2efa0463a5a367cb8d7b

Link: https://lore.kernel.org/r/20250106090708.1541212-1-s-k6@ti.com
This commit is contained in:
Tom Rini
2025-01-14 15:49:41 -06:00
parent e5ce3b44cc bc07851897
commit 08733bf313
36 changed files with 427 additions and 295 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/dts/k3-am62a-ddr.dtsi
View File

@@ -4,11 +4,12 @@
*/
/ {
memorycontroller: memory-controller@f308000 {
memorycontroller: memory-controller@f300000 {
compatible = "ti,am62a-ddrss";
reg = <0x00 0x0f308000 0x00 0x4000>,
<0x00 0x43014000 0x00 0x100>;
reg-names = "cfg", "ctrl_mmr_lp4";
<0x00 0x43014000 0x00 0x100>,
<0x00 0x0f300000 0x00 0x200>;
reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;

12
arch/arm/dts/k3-j721s2-ddr.dtsi
View File

@@ -5,6 +5,8 @@
&main_navss {
ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
<0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
<0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
<0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
<0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
@@ -24,8 +26,9 @@
memorycontroller0: memorycontroller@2990000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x02990000 0x0 0x4000>,
<0x0 0x0114000 0x0 0x100>;
reg-names = "cfg", "ctrl_mmr_lp4";
<0x0 0x0114000 0x0 0x100>,
<0x0 0x02980000 0x0 0x200>;
reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
<&k3_pds 96 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 138 0>, <&k3_clks 43 2>;
@@ -2232,8 +2235,9 @@
memorycontroller1: memorycontroller@29b0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029b0000 0x0 0x4000>,
<0x0 0x0114000 0x0 0x100>;
reg-names = "cfg", "ctrl_mmr_lp4";
<0x0 0x0114000 0x0 0x100>,
<0x0 0x029a0000 0x0 0x200>;
reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>,
<&k3_pds 97 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 139 0>, <&k3_clks 43 2>;

24
arch/arm/dts/k3-j784s4-ddr.dtsi
View File

@@ -9,6 +9,10 @@
<0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
<0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
<0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
<0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
<0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
<0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2
<0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
msmc0: msmc {
@@ -26,8 +30,9 @@
memorycontroller0: memorycontroller@2990000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x02990000 0x0 0x4000>,
<0x0 0x0114000 0x0 0x100>;
reg-names = "cfg", "ctrl_mmr_lp4";
<0x0 0x0114000 0x0 0x100>,
<0x0 0x02980000 0x0 0x200>;
reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
<&k3_pds 131 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
@@ -2234,8 +2239,9 @@
memorycontroller1: memorycontroller@29b0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029b0000 0x0 0x4000>,
<0x0 0x0114000 0x0 0x100>;
reg-names = "cfg", "ctrl_mmr_lp4";
<0x0 0x0114000 0x0 0x100>,
<0x0 0x029a0000 0x0 0x200>;
reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
<&k3_pds 132 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
@@ -4442,8 +4448,9 @@
memorycontroller2: memorycontroller@29d0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029d0000 0x0 0x4000>,
<0x0 0x0114000 0x0 0x100>;
reg-names = "cfg", "ctrl_mmr_lp4";
<0x0 0x0114000 0x0 0x100>,
<0x0 0x029c0000 0x0 0x200>;
reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
<&k3_pds 133 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
@@ -6650,8 +6657,9 @@
memorycontroller3: memorycontroller@29f0000 {
compatible = "ti,j721s2-ddrss";
reg = <0x0 0x029f0000 0x0 0x4000>,
<0x0 0x0114000 0x0 0x100>;
reg-names = "cfg", "ctrl_mmr_lp4";
<0x0 0x0114000 0x0 0x100>,
<0x0 0x29e0000 0x0 0x200>;
reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
<&k3_pds 139 TI_SCI_PD_SHARED>;
clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;

3
arch/arm/mach-k3/Kconfig
View File

@@ -156,6 +156,9 @@ config K3_X509_SWRV
help
SWRV for X509 certificate used for boot images
config NR_DRAM_BANKS
default 2
if CPU_V7R
source "arch/arm/mach-k3/r5/Kconfig"
endif

2
arch/arm/mach-k3/Makefile
View File

@@ -6,7 +6,7 @@
obj-$(CONFIG_ARM64) += arm64/
obj-$(CONFIG_CPU_V7R) += r5/
obj-$(CONFIG_OF_LIBFDT) += common_fdt.o
obj-y += common.o security.o
obj-y += common.o security.o k3-ddr.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
obj-$(CONFIG_SOC_K3_AM625) += am62x/

15
arch/arm/mach-k3/include/mach/k3-ddr.h Normal file
View File

@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2024, Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef _K3_DDR_H_
#define _K3_DDR_H_
int dram_init(void);
int dram_init_banksize(void);
void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image);
void fixup_memory_node(struct spl_image_info *spl_image);
#endif /* _K3_DDR_H_ */

72
arch/arm/mach-k3/k3-ddr.c Normal file
View File

@@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024, Texas Instruments Incorporated - https://www.ti.com/
*/
#include <fdt_support.h>
#include <dm/uclass.h>
#include <k3-ddrss.h>
#include <spl.h>
#include <asm/arch/k3-ddr.h>
__weak int dram_init(void)
{
return 0;
}
__weak int dram_init_banksize(void)
{
return 0;
}
#if defined(CONFIG_SPL_BUILD)
void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
{
struct udevice *dev;
int ret, ctr = 1;
dram_init_banksize();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
panic("Cannnot get RAM device for ddr size fixup: %d\n", ret);
ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
if (ret)
printf("Error fixing up ddr node for ECC use! %d\n", ret);
ret = uclass_next_device_err(&dev);
while (ret && ret != -ENODEV) {
ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
if (ret)
printf("Error fixing up ddr node %d for ECC use! %d\n", ctr, ret);
ret = uclass_next_device_err(&dev);
ctr++;
}
}
void fixup_memory_node(struct spl_image_info *spl_image)
{
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
int bank;
int ret;
dram_init();
dram_init_banksize();
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = gd->bd->bi_dram[bank].start;
size[bank] = gd->bd->bi_dram[bank].size;
}
ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
CONFIG_NR_DRAM_BANKS);
if (ret)
printf("Error fixing up memory node! %d\n", ret);
}
#endif

17
board/ti/am62ax/evm.c
View File

@@ -12,6 +12,7 @@
#include <env.h>
#include <fdt_support.h>
#include <spl.h>
#include <asm/arch/k3-ddr.h>
#include "../common/fdt_ops.h"
@@ -20,15 +21,17 @@ int board_init(void)
return 0;
}
int dram_init(void)
#if defined(CONFIG_XPL_BUILD)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
} else {
fixup_memory_node(spl_image);
}
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)

17
board/ti/am62px/evm.c
View File

@@ -13,6 +13,7 @@
#include <env.h>
#include <fdt_support.h>
#include <spl.h>
#include <asm/arch/k3-ddr.h>
#include "../common/fdt_ops.h"
struct efi_fw_image fw_images[] = {
@@ -53,15 +54,17 @@ int board_init(void)
return 0;
}
int dram_init(void)
#if defined(CONFIG_XPL_BUILD)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
} else {
fixup_memory_node(spl_image);
}
}
#endif
#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
int board_late_init(void)

63
board/ti/am62x/evm.c
View File

@@ -20,6 +20,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <dm/uclass.h>
#include <asm/arch/k3-ddr.h>
#include "../common/fdt_ops.h"
@@ -86,11 +87,6 @@ int board_init(void)
return 0;
}
int dram_init(void)
{
return fdtdec_setup_mem_size_base();
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
@@ -99,13 +95,7 @@ int board_late_init(void)
}
#endif
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
#if defined(CONFIG_XPL_BUILD)
void spl_board_init(void)
{
enable_caches();
@@ -114,53 +104,14 @@ void spl_board_init(void)
}
#if defined(CONFIG_K3_AM64_DDRSS)
static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
{
struct udevice *dev;
int ret;
dram_init_banksize();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
if (ret)
printf("Error fixing up ddr node for ECC use! %d\n", ret);
}
#else
static void fixup_memory_node(struct spl_image_info *spl_image)
{
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
int bank;
int ret;
dram_init();
dram_init_banksize();
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = gd->bd->bi_dram[bank].start;
size[bank] = gd->bd->bi_dram[bank].size;
}
/* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
CONFIG_NR_DRAM_BANKS);
if (ret)
printf("Error fixing up memory node! %d\n", ret);
}
#endif
void spl_perform_fixups(struct spl_image_info *spl_image)
{
#if defined(CONFIG_K3_AM64_DDRSS)
fixup_ddr_driver_for_ecc(spl_image);
#else
fixup_memory_node(spl_image);
#endif
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
} else {
fixup_memory_node(spl_image);
}
}
#endif

73
board/ti/am64x/evm.c
View File

@@ -15,6 +15,7 @@
#include <fdt_support.h>
#include <asm/arch/hardware.h>
#include <env.h>
#include <asm/arch/k3-ddr.h>
#include "../common/board_detect.h"
#include "../common/fdt_ops.h"
@@ -66,28 +67,6 @@ int board_init(void)
return 0;
}
int dram_init(void)
{
s32 ret;
ret = fdtdec_setup_mem_size_base();
if (ret)
printf("Error setting up mem size and base. %d\n", ret);
return ret;
}
int dram_init_banksize(void)
{
s32 ret;
ret = fdtdec_setup_memory_banksize();
if (ret)
printf("Error setting up memory banksize. %d\n", ret);
return ret;
}
#if defined(CONFIG_SPL_LOAD_FIT)
int board_fit_config_name_match(const char *name)
{
@@ -132,52 +111,14 @@ static int fixup_usb_boot(const void *fdt_blob)
}
#endif
#if defined(CONFIG_K3_AM64_DDRSS)
static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
{
struct udevice *dev;
int ret;
dram_init_banksize();
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
if (ret)
printf("Error fixing up ddr node for ECC use! %d\n", ret);
}
#else
static void fixup_memory_node(struct spl_image_info *spl_image)
{
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
int bank;
int ret;
dram_init();
dram_init_banksize();
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = gd->bd->bi_dram[bank].start;
size[bank] = gd->bd->bi_dram[bank].size;
}
/* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS);
if (ret)
printf("Error fixing up memory node! %d\n", ret);
}
#endif
void spl_perform_fixups(struct spl_image_info *spl_image)
{
#if defined(CONFIG_K3_AM64_DDRSS)
fixup_ddr_driver_for_ecc(spl_image);
#else
fixup_memory_node(spl_image);
#endif
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
} else {
fixup_memory_node(spl_image);
}
#if CONFIG_IS_ENABLED(USB_STORAGE)
fixup_usb_boot(spl_image->fdt_addr);

29
board/ti/am65x/evm.c
View File

@@ -20,6 +20,7 @@
#include <env.h>
#include <spl.h>
#include <linux/printk.h>
#include <asm/arch/k3-ddr.h>
#include "../common/board_detect.h"
#include "../common/fdt_ops.h"
@@ -49,17 +50,6 @@ int board_init(void)
return 0;
}
int dram_init(void)
{
#ifdef CONFIG_PHYS_64BIT
gd->ram_size = 0x100000000;
#else
gd->ram_size = 0x80000000;
#endif
return 0;
}
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
@@ -71,23 +61,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return gd->ram_top;
}
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
return 0;
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{

1
board/ti/common/Makefile
View File

@@ -4,3 +4,4 @@
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
obj-${CONFIG_CMD_EXTENSION} += cape_detect.o
obj-${CONFIG_OF_LIBFDT} += fdt_ops.o
obj-${CONFIG_ARCH_K3} += k3-ddr.o

33
board/ti/common/k3-ddr.c Normal file
View File

@@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2024, Texas Instruments Incorporated - https://www.ti.com/
*/
#include <fdt_support.h>
#include <dm/uclass.h>
#include <k3-ddrss.h>
#include <spl.h>
#include "k3-ddr.h"
int dram_init(void)
{
s32 ret;
ret = fdtdec_setup_mem_size_base_lowest();
if (ret)
printf("Error setting up mem size and base. %d\n", ret);
return ret;
}
int dram_init_banksize(void)
{
s32 ret;
ret = fdtdec_setup_memory_banksize();
if (ret)
printf("Error setting up memory banksize. %d\n", ret);
return ret;
}

12
board/ti/common/k3-ddr.h Normal file
View File

@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2024, Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef __K3_DDR_INIT_H
#define __K3_DDR_INIT_H
int dram_init(void);
int dram_init_banksize(void);
#endif /* __K3_DDR_INIT_H */

29
board/ti/j721e/evm.c
View File

@@ -15,6 +15,7 @@
#include <asm/gpio.h>
#include <spl.h>
#include <dm.h>
#include <asm/arch/k3-ddr.h>
#include "../common/board_detect.h"
#include "../common/fdt_ops.h"
@@ -77,17 +78,6 @@ int board_init(void)
return 0;
}
int dram_init(void)
{
#ifdef CONFIG_PHYS_64BIT
gd->ram_size = 0x100000000;
#else
gd->ram_size = 0x80000000;
#endif
return 0;
}
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
@@ -99,23 +89,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return gd->ram_top;
}
int dram_init_banksize(void)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
return 0;
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{

35
board/ti/j721s2/evm.c
View File

@@ -21,6 +21,7 @@
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/root.h>
#include <asm/arch/k3-ddr.h>
#include "../common/board_detect.h"
#include "../common/fdt_ops.h"
@@ -32,17 +33,6 @@ int board_init(void)
return 0;
}
int dram_init(void)
{
#ifdef CONFIG_PHYS_64BIT
gd->ram_size = 0x100000000;
#else
gd->ram_size = 0x80000000;
#endif
return 0;
}
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
#ifdef CONFIG_PHYS_64BIT
@@ -54,22 +44,17 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return gd->ram_top;
}
int dram_init_banksize(void)
#if defined(CONFIG_XPL_BUILD)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = 0x7fffffff;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = 0x880000000;
gd->bd->bi_dram[1].size = 0x37fffffff;
gd->ram_size = 0x400000000;
#endif
return 0;
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
} else {
fixup_memory_node(spl_image);
}
}
#endif
#ifdef CONFIG_TI_I2C_BOARD_DETECT
/*

17
board/ti/j722s/evm.c
View File

@@ -12,6 +12,7 @@
#include <env.h>
#include <fdt_support.h>
#include <spl.h>
#include <asm/arch/k3-ddr.h>
#include "../common/fdt_ops.h"
int board_init(void)
@@ -19,15 +20,17 @@ int board_init(void)
return 0;
}
int dram_init(void)
#if defined(CONFIG_XPL_BUILD)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
} else {
fixup_memory_node(spl_image);
}
}
#endif
#if IS_ENABLED(CONFIG_BOARD_LATE_INIT)
int board_late_init(void)

17
board/ti/j784s4/evm.c
View File

@@ -10,6 +10,7 @@
#include <efi_loader.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/k3-ddr.h>
#include "../common/fdt_ops.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -52,15 +53,17 @@ int board_init(void)
return 0;
}
int dram_init(void)
#if defined(CONFIG_XPL_BUILD)
void spl_perform_fixups(struct spl_image_info *spl_image)
{
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))
fixup_ddr_driver_for_ecc(spl_image);
} else {
fixup_memory_node(spl_image);
}
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)

1
configs/am62ax_evm_a53_defconfig
View File

@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM62A7=y
CONFIG_TARGET_AM62A7_A53_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/am62px_evm_a53_defconfig
View File

@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM62P5=y
CONFIG_TARGET_AM62P5_A53_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/am62x_evm_a53_defconfig
View File

@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM625=y
CONFIG_TARGET_AM625_A53_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/am62x_evm_r5_defconfig
View File

@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_LEN=0x08000000
CONFIG_SYS_MALLOC_F_LEN=0x9000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM625=y
CONFIG_TARGET_AM625_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/am64x_evm_a53_defconfig
View File

@@ -6,7 +6,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM642=y
CONFIG_K3_ATF_LOAD_ADDR=0x701c0000
CONFIG_TARGET_AM642_A53_EVM=y

1
configs/am64x_evm_r5_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM642=y
CONFIG_TARGET_AM642_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/am65x_evm_a53_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM654=y
CONFIG_TARGET_AM654_A53_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/am65x_evm_r5_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM654=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y

1
configs/am65x_evm_r5_usbdfu_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM654=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y

1
configs/am65x_evm_r5_usbmsc_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x55000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_AM654=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_AM654_R5_EVM=y

1
configs/j7200_evm_a72_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J7200_A72_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/j721e_evm_a72_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_A72_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/j721s2_evm_a72_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721S2=y
CONFIG_TARGET_J721S2_A72_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/j722s_evm_a53_defconfig
View File

@@ -4,7 +4,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J722S=y
CONFIG_TARGET_J722S_A53_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

1
configs/j784s4_evm_a72_defconfig
View File

@@ -5,7 +5,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J784S4=y
CONFIG_TARGET_J784S4_A72_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

10
drivers/ram/Kconfig
View File

@@ -116,6 +116,16 @@ config IMXRT_SDRAM
to support external memories like sdram, psram & nand.
This driver is for the sdram memory interface with the SEMC.
config K3_INLINE_ECC
bool "Enable TI Inline ECC support"
depends on K3_DDRSS
help
Enable Inline ECC support on K3 platforms. 1/9th of the SDRAM space
is used for ECC storage and the rest 8/9th is available for system
use. Enabling ECC increases boot time as the ECC protected regions
need to be primed with a predefined value prior to enabling ECC
check.
source "drivers/ram/aspeed/Kconfig"
source "drivers/ram/cadence/Kconfig"
source "drivers/ram/octeon/Kconfig"

219
drivers/ram/k3-ddrss/k3-ddrss.c
View File

@@ -6,6 +6,7 @@
*/
#include <config.h>
#include <time.h>
#include <clk.h>
#include <div64.h>
#include <dm.h>
@@ -44,6 +45,11 @@
#define DDRSS_ECC_R2_STR_ADDR_REG 0x0140
#define DDRSS_ECC_R2_END_ADDR_REG 0x0144
#define DDRSS_ECC_1B_ERR_CNT_REG 0x0150
#define DDRSS_V2A_INT_SET_REG 0x00a8
#define DDRSS_V2A_INT_SET_REG_ECC1BERR_EN BIT(3)
#define DDRSS_V2A_INT_SET_REG_ECC2BERR_EN BIT(4)
#define DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN BIT(5)
#define SINGLE_DDR_SUBSYSTEM 0x1
#define MULTI_DDR_SUBSYSTEM 0x2
@@ -120,8 +126,8 @@ struct k3_msmc {
#define K3_DDRSS_MAX_ECC_REGIONS 3
struct k3_ddrss_ecc_region {
u32 start;
u32 range;
u64 start;
u64 range;
};
struct k3_ddrss_desc {
@@ -145,7 +151,9 @@ struct k3_ddrss_desc {
lpddr4_privatedata pd;
struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS];
u64 ecc_reserved_space;
bool ti_ecc_enabled;
u64 ddr_bank_base[CONFIG_NR_DRAM_BANKS];
u64 ddr_bank_size[CONFIG_NR_DRAM_BANKS];
u64 ddr_ram_size;
};
struct reginitdata {
@@ -399,8 +407,6 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
if (ret)
dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable");
return ret;
}
@@ -542,27 +548,174 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
}
}
static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size)
static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size)
{
writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG);
writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG);
}
static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word)
#define BIST_MODE_MEM_INIT 4
#define BIST_MEM_INIT_TIMEOUT 10000 /* 1msec loops per block = 10s */
static void k3_lpddr4_bist_init_mem_region(struct k3_ddrss_desc *ddrss,
u64 addr, u64 size,
u32 pattern)
{
int i;
lpddr4_obj *driverdt = ddrss->driverdt;
lpddr4_privatedata *pd = &ddrss->pd;
u32 status, offset, regval;
bool int_status;
int i = 0;
/* Set BIST_START_ADDR_0 [31:0] */
regval = (u32)(addr & TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_0__FLD));
TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_0__REG, CTL_SHIFT, offset);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);
/* Set BIST_START_ADDR_1 [32 or 34:32] */
regval = (u32)(addr >> TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD));
regval &= TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_1__FLD);
TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_1__REG, CTL_SHIFT, offset);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);
/* Set ADDR_SPACE = log2(size) */
regval = (u32)(ilog2(size) << TH_FLD_SHIFT(LPDDR4__ADDR_SPACE__FLD));
TH_OFFSET_FROM_REG(LPDDR4__ADDR_SPACE__REG, CTL_SHIFT, offset);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);
/* Enable the BIST data check. On 32bit lpddr4 (e.g J7) this shares a
* register with ADDR_SPACE and BIST_GO.
*/
TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_CHECK__REG, CTL_SHIFT, offset);
driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
regval |= TH_FLD_MASK(LPDDR4__BIST_DATA_CHECK__FLD);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);
/* Clear the address check bit */
TH_OFFSET_FROM_REG(LPDDR4__BIST_ADDR_CHECK__REG, CTL_SHIFT, offset);
driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
regval &= ~TH_FLD_MASK(LPDDR4__BIST_ADDR_CHECK__FLD);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);
/* Set BIST_TEST_MODE[2:0] to memory initialize (4) */
regval = BIST_MODE_MEM_INIT;
TH_OFFSET_FROM_REG(LPDDR4__BIST_TEST_MODE__REG, CTL_SHIFT, offset);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);
/* Set BIST_DATA_PATTERN[31:0] */
TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_0__REG, CTL_SHIFT, offset);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern);
/* Set BIST_DATA_PATTERN[63:32] */
TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_1__REG, CTL_SHIFT, offset);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern);
udelay(1000);
/* Enable the programmed BIST operation - BIST_GO = 1 */
TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset);
driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval);
regval |= TH_FLD_MASK(LPDDR4__BIST_GO__FLD);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval);
/* Wait for the BIST_DONE interrupt */
while (i < BIST_MEM_INIT_TIMEOUT) {
status = driverdt->checkctlinterrupt(pd, LPDDR4_INTR_BIST_DONE,
&int_status);
if (!status & int_status) {
/* Clear LPDDR4_INTR_BIST_DONE */
driverdt->ackctlinterrupt(pd, LPDDR4_INTR_BIST_DONE);
break;
}
udelay(1000);
i++;
}
/* Before continuing we have to stop BIST - BIST_GO = 0 */
TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset);
driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, 0);
/* Timeout hit while priming the memory. We can't continue,
* since the memory is not fully initialized and we most
* likely get an uncorrectable error exception while booting.
*/
if (i == BIST_MEM_INIT_TIMEOUT) {
printf("ERROR: Timeout while priming the memory.\n");
hang();
}
}
static void k3_ddrss_lpddr4_preload_full_mem(struct k3_ddrss_desc *ddrss,
u64 total_size, u32 pattern)
{
u32 done, max_size2;
/* Get the max size (log2) supported in this config (16/32 lpddr4)
* from the start_addess width - 16bit: 8G, 32bit: 32G
*/
max_size2 = TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD) +
TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_1__FLD) + 1;
/* ECC is enabled in dt but we can't preload the memory if
* the memory configuration is recognized and supported.
*/
if (!total_size || total_size > (1ull << max_size2) ||
total_size & (total_size - 1)) {
printf("ECC: the memory configuration is not supported\n");
hang();
}
printf("ECC is enabled, priming DDR which will take several seconds.\n");
done = get_timer(0);
k3_lpddr4_bist_init_mem_region(ddrss, 0, total_size, pattern);
printf("ECC: priming DDR completed in %lu msec\n", get_timer(done));
}
for (i = 0; i < (size / 4); i++)
addr[i] = word;
static void k3_ddrss_ddr_bank_base_size_calc(struct k3_ddrss_desc *ddrss)
{
int bank, na, ns, len, parent;
const fdt32_t *ptr, *end;
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
ddrss->ddr_bank_base[bank] = 0;
ddrss->ddr_bank_size[bank] = 0;
}
ofnode mem = ofnode_null();
do {
mem = ofnode_by_prop_value(mem, "device_type", "memory", 7);
} while (!ofnode_is_enabled(mem));
const void *fdt = ofnode_to_fdt(mem);
int node = ofnode_to_offset(mem);
const char *property = "reg";
parent = fdt_parent_offset(fdt, node);
na = fdt_address_cells(fdt, parent);
ns = fdt_size_cells(fdt, parent);
ptr = fdt_getprop(fdt, node, property, &len);
end = ptr + len / sizeof(*ptr);
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
if (ptr + na + ns <= end) {
if (CONFIG_IS_ENABLED(OF_TRANSLATE))
ddrss->ddr_bank_base[bank] = fdt_translate_address(fdt, node, ptr);
else
ddrss->ddr_bank_base[bank] = fdtdec_get_number(ptr, na);
ddrss->ddr_bank_size[bank] = fdtdec_get_number(&ptr[na], ns);
}
ptr += na + ns;
}
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++)
ddrss->ddr_ram_size += ddrss->ddr_bank_size[bank];
}
static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
{
fdtdec_setup_mem_size_base_lowest();
ddrss->ecc_reserved_space = gd->ram_size;
ddrss->ecc_reserved_space = ddrss->ddr_ram_size;
do_div(ddrss->ecc_reserved_space, 9);
/* Round to clean number */
@@ -571,25 +724,29 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
{
u32 ecc_region_start = ddrss->ecc_regions[0].start;
u32 ecc_range = ddrss->ecc_regions[0].range;
u64 ecc_region_start = ddrss->ecc_regions[0].start;
u64 ecc_range = ddrss->ecc_regions[0].range;
u32 base = (u32)ddrss->ddrss_ss_cfg;
u32 val;
/* Only Program region 0 which covers full ddr space */
k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range);
k3_ddrss_set_ecc_range_r0(base, ecc_region_start - ddrss->ddr_bank_base[0], ecc_range);
/* Enable ECC, RMW, WR_ALLOC */
writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN |
DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG);
/* Preload ECC Mem region with 0's */
k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range,
0x00000000);
/* Preload the full memory with 0's using the BIST engine of
* the LPDDR4 controller.
*/
k3_ddrss_lpddr4_preload_full_mem(ddrss, ddrss->ddr_ram_size, 0);
/* Clear Error Count Register */
writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);
writel(DDRSS_V2A_INT_SET_REG_ECC1BERR_EN | DDRSS_V2A_INT_SET_REG_ECC2BERR_EN |
DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN, base + DDRSS_V2A_INT_SET_REG);
/* Enable ECC Check */
val = readl(base + DDRSS_ECC_CTRL_REG);
val |= DDRSS_ECC_CTRL_REG_ECC_CK;
@@ -630,7 +787,9 @@ static int k3_ddrss_probe(struct udevice *dev)
k3_lpddr4_start(ddrss);
if (ddrss->ti_ecc_enabled) {
k3_ddrss_ddr_bank_base_size_calc(ddrss);
if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) {
if (!ddrss->ddrss_ss_cfg) {
printf("%s: ss_cfg is required if ecc is enabled but not provided.",
__func__);
@@ -640,8 +799,8 @@ static int k3_ddrss_probe(struct udevice *dev)
k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss);
/* Always configure one region that covers full DDR space */
ddrss->ecc_regions[0].start = gd->ram_base;
ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space;
ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0];
ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space;
k3_ddrss_lpddr4_ecc_init(ddrss);
}
@@ -650,30 +809,24 @@ static int k3_ddrss_probe(struct udevice *dev)
int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd)
{
struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
u64 start[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
int bank;
struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
if (ddrss->ecc_reserved_space == 0)
return 0;
for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) {
if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) {
ddrss->ecc_reserved_space -= bd->bi_dram[bank].size;
bd->bi_dram[bank].size = 0;
if (ddrss->ecc_reserved_space > ddrss->ddr_bank_size[bank]) {
ddrss->ecc_reserved_space -= ddrss->ddr_bank_size[bank];
ddrss->ddr_bank_size[bank] = 0;
} else {
bd->bi_dram[bank].size -= ddrss->ecc_reserved_space;
ddrss->ddr_bank_size[bank] -= ddrss->ecc_reserved_space;
break;
}
}
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = bd->bi_dram[bank].start;
size[bank] = bd->bi_dram[bank].size;
}
return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
return fdt_fixup_memory_banks(blob, ddrss->ddr_bank_base,
ddrss->ddr_bank_size, CONFIG_NR_DRAM_BANKS);
}
static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)