arm: mmp: add initial support for PXA1908 SoC
Add initial support for Marvell PXA1908. The SoC has 4 Cortex-A53 cores, a GC7000UL GPU and a variety of peripheral controllers. Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:

committed by
Stefan Roese

parent
2d84e1519c
commit
08b27fce29
@@ -386,6 +386,14 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-marvell.git
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F: drivers/pci/pci-aardvark.c
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F: drivers/pci/pci-aardvark.c
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F: drivers/pci/pci_mvebu.c
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F: drivers/pci/pci_mvebu.c
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ARM MARVELL PXA1908
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M: Duje Mihanović <duje.mihanovic@skole.hr>
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S: Maintained
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T: git git://git.dujemihanovic.xyz/u-boot.git
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F: arch/arm/dts/pxa1908*
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F: arch/arm/mach-mmp/
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F: include/configs/pxa1908.h
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ARM MARVELL SERIAL DRIVERS
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ARM MARVELL SERIAL DRIVERS
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M: Pali Rohár <pali@kernel.org>
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M: Pali Rohár <pali@kernel.org>
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M: Stefan Roese <sr@denx.de>
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M: Stefan Roese <sr@denx.de>
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@@ -842,6 +842,15 @@ config ARCH_MEDIATEK
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Support for the MediaTek SoCs family developed by MediaTek Inc.
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Support for the MediaTek SoCs family developed by MediaTek Inc.
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Please refer to doc/README.mediatek for more information.
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Please refer to doc/README.mediatek for more information.
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config ARCH_MMP
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bool "Marvell MMP"
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select ARM64
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select DM
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select DM_SERIAL
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select OF_CONTROL
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select SAVE_PREV_BL_FDT_ADDR
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select SAVE_PREV_BL_INITRAMFS_START_ADDR
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config ARCH_LPC32XX
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config ARCH_LPC32XX
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bool "NXP LPC32xx platform"
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bool "NXP LPC32xx platform"
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select CPU_ARM926EJS
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select CPU_ARM926EJS
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@@ -2310,6 +2319,8 @@ source "arch/arm/mach-meson/Kconfig"
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source "arch/arm/mach-mediatek/Kconfig"
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source "arch/arm/mach-mediatek/Kconfig"
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source "arch/arm/mach-mmp/Kconfig"
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source "arch/arm/mach-qemu/Kconfig"
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source "arch/arm/mach-qemu/Kconfig"
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source "arch/arm/mach-rockchip/Kconfig"
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source "arch/arm/mach-rockchip/Kconfig"
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@@ -69,6 +69,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD) += kirkwood
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machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
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machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
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machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
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machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
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machine-$(CONFIG_ARCH_MESON) += meson
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machine-$(CONFIG_ARCH_MESON) += meson
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machine-$(CONFIG_ARCH_MMP) += mmp
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machine-$(CONFIG_ARCH_MVEBU) += mvebu
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machine-$(CONFIG_ARCH_MVEBU) += mvebu
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machine-$(CONFIG_ARCH_NEXELL) += nexell
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machine-$(CONFIG_ARCH_NEXELL) += nexell
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machine-$(CONFIG_ARCH_NPCM) += npcm
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machine-$(CONFIG_ARCH_NPCM) += npcm
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106
arch/arm/dts/pxa1908.dtsi
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106
arch/arm/dts/pxa1908.dtsi
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@@ -0,0 +1,106 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Marvell Armada PXA1908";
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compatible = "marvell,pxa1908";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0 3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@d1df9000 {
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compatible = "arm,gic-400";
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reg = <0 0xd1df9000 0 0x1000>,
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<0 0xd1dfa000 0 0x2000>,
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/* The subsequent registers are guesses. */
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<0 0xd1dfc000 0 0x2000>,
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<0 0xd1dfe000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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apb@d4000000 {
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compatible = "simple-bus";
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reg = <0 0xd4000000 0 0x200000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xd4000000 0x200000>;
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uart0: serial@17000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0x17000 0x1000>;
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clock-frequency = <14745600>;
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reg-shift = <2>;
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};
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uart1: serial@18000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0x18000 0x1000>;
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clock-frequency = <14745600>;
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reg-shift = <2>;
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};
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uart2: serial@36000 {
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compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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reg = <0x36000 0x1000>;
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clock-frequency = <117000000>;
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reg-shift = <2>;
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};
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};
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};
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};
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6
arch/arm/mach-mmp/Kconfig
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6
arch/arm/mach-mmp/Kconfig
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@@ -0,0 +1,6 @@
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if ARCH_MMP
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config LNX_KRNL_IMG_TEXT_OFFSET_BASE
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default TEXT_BASE
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endif
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1
arch/arm/mach-mmp/Makefile
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1
arch/arm/mach-mmp/Makefile
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@@ -0,0 +1 @@
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obj-y += board.o mmu.o
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84
arch/arm/mach-mmp/board.c
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84
arch/arm/mach-mmp/board.c
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@@ -0,0 +1,84 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024
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* Duje Mihanović <duje.mihanovic@skole.hr>
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*/
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#include <errno.h>
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#include <init.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/global_data.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Timer constants */
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#define APBC_COUNTER_CLK_SEL 0xd4015064
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#define COUNTER_BASE 0xd4101000
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#define COUNTER_EN BIT(0)
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#define COUNTER_HALT_ON_DEBUG BIT(1)
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int timer_init(void)
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{
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u32 tmp = readl(APBC_COUNTER_CLK_SEL);
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if ((tmp >> 16) != 0x319)
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return -1;
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/* Set timer frequency to 26MHz */
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writel(tmp | 1, APBC_COUNTER_CLK_SEL);
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writel(COUNTER_EN | COUNTER_HALT_ON_DEBUG, COUNTER_BASE);
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gd->arch.timer_rate_hz = 26000000;
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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puts("fdtdec_setup_mem_size_base() has failed\n");
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return 0;
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}
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#ifndef CONFIG_SYSRESET
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void reset_cpu(void)
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{
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}
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#endif
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/* Stolen from arch/arm/mach-snapdragon/board.c */
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int board_fdt_blob_setup(void **fdtp)
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{
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struct fdt_header *fdt;
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bool internal_valid, external_valid;
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int ret = 0;
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fdt = (struct fdt_header *)get_prev_bl_fdt_addr();
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external_valid = fdt && !fdt_check_header(fdt);
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internal_valid = !fdt_check_header(*fdtp);
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/*
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* There is no point returning an error here, U-Boot can't do anything useful in this situation.
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* Bail out while we can still print a useful error message.
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*/
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if (!internal_valid && !external_valid)
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panic("Internal FDT is invalid and no external FDT was provided! (fdt=%#llx)\n",
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(phys_addr_t)fdt);
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if (internal_valid) {
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debug("Using built in FDT\n");
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ret = -EEXIST;
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} else {
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debug("Using external FDT\n");
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/* So we can use it before returning */
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*fdtp = fdt;
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}
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return ret;
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}
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30
arch/arm/mach-mmp/mmu.c
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30
arch/arm/mach-mmp/mmu.c
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@@ -0,0 +1,30 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2024
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* Duje Mihanović <duje.mihanovic@skole.hr>
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*/
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#include <asm/armv8/mmu.h>
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#include <linux/sizes.h>
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static struct mm_region pxa1908_mem_map[] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 2UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 2UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_INNER_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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{
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0,
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}
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};
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struct mm_region *mem_map = pxa1908_mem_map;
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18
include/configs/pxa1908.h
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18
include/configs/pxa1908.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2024
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* Duje Mihanović <duje.mihanovic@skole.hr>
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*/
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#ifndef __PXA1908_H
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#define __PXA1908_H
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#define CFG_SYS_SDRAM_BASE 0x1000000
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#define CFG_SYS_INIT_RAM_ADDR 0x10000000
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#define CFG_SYS_INIT_RAM_SIZE 0x4000
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#define CFG_SYS_NS16550_IER 0x40
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#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
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#define CFG_EXTRA_ENV_SETTINGS \
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"bootcmd=bootm $prevbl_initrd_start_addr\0"
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#endif
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