arm: dts: qcom: Sync pinctrl DT nodes with Linux bindings

Currently for all Qcom SoCs/boards there are separate compatibles for
GPIO and pinctrl. But this is inconsistent with official (upstream) Linux
bindings which requires only a single compatible "qcom,<SoC name>-pinctrl"
and there is no such compatible property as "qcom,tlmm-<SoC name>".

So fix this inconsistency for Qcom SoCs in order to comply with upstream
DT bindings. This is done via removing compatibles from "msm_gpio" driver
and via binding to "msm_gpio" driver from pinctrl driver in case
"gpio-controller" property is specified for pinctrl node.

Suggested-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

arch/arm/dts/dragonboard410c-uboot.dtsi

@@ -14,7 +14,7 @@
 	soc {
 		u-boot,dm-pre-reloc;
 
-		qcom,tlmm@1000000 {
+		pinctrl@1000000 {
 			u-boot,dm-pre-reloc;
 
 			uart {

arch/arm/dts/dragonboard410c.dts

@@ -60,9 +60,13 @@
 			reg = <0x60000 0x8000>;
 		};
 
-		pinctrl: qcom,tlmm@1000000 {
+		soc_gpios: pinctrl@1000000 {
-			compatible = "qcom,tlmm-apq8016";
+			compatible = "qcom,msm8916-pinctrl";
 			reg = <0x1000000 0x400000>;
+			gpio-controller;
+			gpio-count = <122>;
+			gpio-bank-name="soc";
+			#gpio-cells = <2>;
 
 			blsp1_uart: uart {
 				function = "blsp1_uart";
@@ -86,15 +90,6 @@
 			pinctrl-0 = <&blsp1_uart>;
 		};
 
-		soc_gpios: pinctrl@1000000 {
-			compatible = "qcom,apq8016-pinctrl";
-			reg = <0x1000000 0x300000>;
-			gpio-controller;
-			gpio-count = <122>;
-			gpio-bank-name="soc";
-			#gpio-cells = <2>;
-		};
-
 		ehci@78d9000 {
 			compatible = "qcom,ehci-host";
 			reg = <0x78d9000 0x400>;

arch/arm/dts/dragonboard820c-uboot.dtsi

@@ -13,7 +13,7 @@
 	soc {
 		u-boot,dm-pre-reloc;
 
-		qcom,tlmm@1010000 {
+		pinctrl@1010000 {
 			u-boot,dm-pre-reloc;
 
 			uart {

arch/arm/dts/dragonboard820c.dts

@@ -64,8 +64,8 @@
 			reg = <0x300000 0x90000>;
 		};
 
-		pinctrl: qcom,tlmm@1010000 {
+		pinctrl: pinctrl@1010000 {
-			compatible = "qcom,tlmm-apq8096";
+			compatible = "qcom,msm8996-pinctrl";
 			reg = <0x1010000 0x400000>;
 
 			blsp8_uart: uart {

arch/arm/dts/qcom-ipq4019.dtsi

@@ -75,9 +75,13 @@
 			u-boot,dm-pre-reloc;
 		};
 
-		pinctrl: qcom,tlmm@1000000 {
+		soc_gpios: pinctrl@1000000 {
-			compatible = "qcom,tlmm-ipq4019";
+			compatible = "qcom,ipq4019-pinctrl";
 			reg = <0x1000000 0x300000>;
+			gpio-controller;
+			gpio-count = <100>;
+			gpio-bank-name="soc";
+			#gpio-cells = <2>;
 			u-boot,dm-pre-reloc;
 		};
 
@@ -90,16 +94,6 @@
 			u-boot,dm-pre-reloc;
 		};
 
-		soc_gpios: pinctrl@1000000 {
-			compatible = "qcom,ipq4019-pinctrl";
-			reg = <0x1000000 0x300000>;
-			gpio-controller;
-			gpio-count = <100>;
-			gpio-bank-name="soc";
-			#gpio-cells = <2>;
-			u-boot,dm-pre-reloc;
-		};
-
 		blsp1_spi1: spi@78b5000 {
 			compatible = "qcom,spi-qup-v2.2.1";
 			reg = <0x78b5000 0x600>;

arch/arm/dts/qcs404-evb.dts

@@ -38,7 +38,7 @@
 		compatible = "simple-bus";
 
 		pinctrl_north@1300000 {
-			compatible = "qcom,tlmm-qcs404";
+			compatible = "qcom,qcs404-pinctrl";
 			reg = <0x1300000 0x200000>;
 
 			blsp1_uart2: uart {

arch/arm/dts/sdm845.dtsi

@@ -37,7 +37,7 @@
 		};
 
 		tlmm_north: pinctrl_north@3900000 {
-			compatible = "qcom,tlmm-sdm845";
+			compatible = "qcom,sdm845-pinctrl";
 			reg = <0x3900000 0x400000>;
 			gpio-count = <150>;
 			gpio-controller;

arch/arm/mach-ipq40xx/pinctrl-snapdragon.c

@@ -14,6 +14,8 @@
 #include <dm.h>
 #include <errno.h>
 #include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
 #include <dm/pinctrl.h>
 #include <linux/bitops.h>
 #include "pinctrl-snapdragon.h"
@@ -110,6 +112,32 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector,
 	return 0;
 }
 
+static int msm_pinctrl_bind(struct udevice *dev)
+{
+	ofnode node = dev_ofnode(dev);
+	const char *name;
+	int ret;
+
+	ofnode_get_property(node, "gpio-controller", &ret);
+	if (ret < 0)
+		return 0;
+
+	/* Get the name of gpio node */
+	name = ofnode_get_name(node);
+	if (!name)
+		return -EINVAL;
+
+	/* Bind gpio node */
+	ret = device_bind_driver_to_node(dev, "gpio_msm",
+					 name, node, NULL);
+	if (ret)
+		return ret;
+
+	dev_dbg(dev, "bind %s\n", name);
+
+	return 0;
+}
+
 static struct pinctrl_ops msm_pinctrl_ops = {
 	.get_pins_count = msm_get_pins_count,
 	.get_pin_name = msm_get_pin_name,
@@ -123,7 +151,7 @@ static struct pinctrl_ops msm_pinctrl_ops = {
 };
 
 static const struct udevice_id msm_pinctrl_ids[] = {
-	{ .compatible = "qcom,tlmm-ipq4019", .data = (ulong)&ipq4019_data },
+	{ .compatible = "qcom,ipq4019-pinctrl", .data = (ulong)&ipq4019_data },
 	{ }
 };
 
@@ -134,4 +162,5 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = {
 	.priv_auto	= sizeof(struct msm_pinctrl_priv),
 	.ops		= &msm_pinctrl_ops,
 	.probe		= msm_pinctrl_probe,
+	.bind		= msm_pinctrl_bind,
 };

arch/arm/mach-snapdragon/pinctrl-snapdragon.c

@@ -10,6 +10,8 @@
 #include <dm.h>
 #include <errno.h>
 #include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/lists.h>
 #include <dm/pinctrl.h>
 #include <linux/bitops.h>
 #include "pinctrl-snapdragon.h"
@@ -113,11 +115,37 @@ static struct pinctrl_ops msm_pinctrl_ops = {
 	.get_function_name = msm_get_function_name,
 };
 
+static int msm_pinctrl_bind(struct udevice *dev)
+{
+	ofnode node = dev_ofnode(dev);
+	const char *name;
+	int ret;
+
+	ofnode_get_property(node, "gpio-controller", &ret);
+	if (ret < 0)
+		return 0;
+
+	/* Get the name of gpio node */
+	name = ofnode_get_name(node);
+	if (!name)
+		return -EINVAL;
+
+	/* Bind gpio node */
+	ret = device_bind_driver_to_node(dev, "gpio_msm",
+					 name, node, NULL);
+	if (ret)
+		return ret;
+
+	dev_dbg(dev, "bind %s\n", name);
+
+	return 0;
+}
+
 static const struct udevice_id msm_pinctrl_ids[] = {
-	{ .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data },
+	{ .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
-	{ .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data },
+	{ .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
-	{ .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data },
+	{ .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
-	{ .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data },
+	{ .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
 	{ }
 };
 
@@ -128,4 +156,5 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = {
 	.priv_auto	= sizeof(struct msm_pinctrl_priv),
 	.ops		= &msm_pinctrl_ops,
 	.probe		= msm_pinctrl_probe,
+	.bind		= msm_pinctrl_bind,
 };

drivers/gpio/msm_gpio.c

@@ -116,20 +116,12 @@ static int msm_gpio_of_to_plat(struct udevice *dev)
 	return 0;
 }
 
-static const struct udevice_id msm_gpio_ids[] = {
-	{ .compatible = "qcom,msm8916-pinctrl" },
-	{ .compatible = "qcom,apq8016-pinctrl" },
-	{ .compatible = "qcom,ipq4019-pinctrl" },
-	{ .compatible = "qcom,sdm845-pinctrl" },
-	{ }
-};
-
 U_BOOT_DRIVER(gpio_msm) = {
 	.name	= "gpio_msm",
 	.id	= UCLASS_GPIO,
-	.of_match = msm_gpio_ids,
 	.of_to_plat = msm_gpio_of_to_plat,
 	.probe	= msm_gpio_probe,
 	.ops	= &gpio_msm_ops,
+	.flags	= DM_UC_FLAG_SEQ_ALIAS,
 	.priv_auto	= sizeof(struct msm_gpio_bank),
 };