From 29602a52903f34653081e6ecbaa4a5ab056409b9 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Wed, 16 Apr 2025 17:38:28 +0530 Subject: [PATCH 1/3] pci: pcie_cdns_ti: Include linux/sizes.h header Driver uses macro SZ_4G to configure inbound base address register. The macro is used without including the header file in which it is defined. Fix this. Fixes: 59ad5480098 ("pci: Add TI K3 Cadence PCIe Controller") Signed-off-by: Hrushikesh Salunke Reviewed-by: Siddharth Vadapalli --- drivers/pci/pcie_cdns_ti.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c index 41469a186a3..e5bcc6eb53e 100644 --- a/drivers/pci/pcie_cdns_ti.c +++ b/drivers/pci/pcie_cdns_ti.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include From a478d0f05b20b96e0911d78ddf1751ba94e171fc Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Wed, 16 Apr 2025 17:38:29 +0530 Subject: [PATCH 2/3] pci: pcie_cdns_ti: Enable PCIe root-complex mode in AM64 SoC TI's AM64 SoC has single instance of PCIe Controller namely PCIe0 which is Cadence PCIe Controller. Add support to configure PCIe0 in Root- Complex mode of operation. Signed-off-by: Hrushikesh Salunke Reviewed-by: Siddharth Vadapalli --- drivers/pci/pcie_cdns_ti.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/pcie_cdns_ti.c b/drivers/pci/pcie_cdns_ti.c index e5bcc6eb53e..9d1d123a18c 100644 --- a/drivers/pci/pcie_cdns_ti.c +++ b/drivers/pci/pcie_cdns_ti.c @@ -835,11 +835,21 @@ static const struct pcie_cdns_ti_data j7200_pcie_rc_data = { .max_lanes = 2, }; +static const struct pcie_cdns_ti_data am64_pcie_rc_data = { + .mode = PCIE_MODE_RC, + .quirk_detect_quiet_flag = true, + .max_lanes = 1, +}; + static const struct udevice_id pcie_cdns_ti_ids[] = { { .compatible = "ti,j7200-pcie-host", .data = (ulong)&j7200_pcie_rc_data, }, + { + .compatible = "ti,am64-pcie-host", + .data = (ulong)&am64_pcie_rc_data, + }, {}, }; From f4baa55c5bee5a2eaedf80c8a84cc839230a9a73 Mon Sep 17 00:00:00 2001 From: Hrushikesh Salunke Date: Wed, 16 Apr 2025 17:38:30 +0530 Subject: [PATCH 3/3] configs: am64x_evm_a53_defconfig: Enable configs for PCIe support TI's AM64 SoC has single instance of PCIe Controller namely PCIe0 which is Cadence PCIe Controller. To support PCIe functionality with PCIe0 instance in Root-Complex mode enable corresponding configs. Also enable configs to support NVMe over PCIe. Signed-off-by: Hrushikesh Salunke Reviewed-by: Siddharth Vadapalli --- configs/am64x_evm_a53_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index c2ad1242d20..9fc95798ffb 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_PCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 @@ -70,6 +71,7 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_EFIDEBUG=y @@ -135,6 +137,9 @@ CONFIG_PHY_TI_DP83869=y CONFIG_PHY_FIXED=y CONFIG_TI_AM65_CPSW_NUSS=y CONFIG_TI_ICSSG_PRUETH=y +CONFIG_NVME_PCI=y +CONFIG_PCI_CONFIG_HOST_BRIDGE=y +CONFIG_PCIE_CDNS_TI=y CONFIG_PHY=y CONFIG_SPL_PHY=y CONFIG_PHY_CADENCE_TORRENT=y