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spi: Add zynq spi controller driver

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Zynq spi controller driver supports 2 buses and
3 chipselects on each bus.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Jagannadha Sutradharudu Teki
2013-07-29 23:45:16 +05:30
parent 3488850629
commit 1465d055f9
3 changed files with 283 additions and 0 deletions
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2
arch/arm/include/asm/arch-zynq/hardware.h
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@@ -17,6 +17,8 @@
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
/* Reflect slcr offsets */
struct slcr_regs {