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pwm: mtk: add support for MediaTek MT7981 SoC

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This patch adds PWM support for MediaTek MT7981 SoC.
MT7981 uses a different register offset so we have to add a version field
to indicate the IP core version.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
2022-09-09 19:59:38 +08:00
committed by Tom Rini
parent c986dd9f58
commit 1ac479587f
1 changed files with 32 additions and 2 deletions
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34
drivers/pwm/pwm-mtk.c
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@@ -29,13 +29,23 @@
#define NSEC_PER_SEC 1000000000L #define NSEC_PER_SEC 1000000000L
static const unsigned int mtk_pwm_reg_offset[] = { enum mtk_pwm_reg_ver {
PWM_REG_V1,
PWM_REG_V2,
};
static const unsigned int mtk_pwm_reg_offset_v1[] = {
0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
}; };
static const unsigned int mtk_pwm_reg_offset_v2[] = {
0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
};
struct mtk_pwm_soc { struct mtk_pwm_soc {
unsigned int num_pwms; unsigned int num_pwms;
bool pwm45_fixup; bool pwm45_fixup;
enum mtk_pwm_reg_ver reg_ver;
}; };
struct mtk_pwm_priv { struct mtk_pwm_priv {
@@ -49,7 +59,16 @@ struct mtk_pwm_priv {
static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val) static void mtk_pwm_w32(struct udevice *dev, uint channel, uint reg, uint val)
{ {
struct mtk_pwm_priv *priv = dev_get_priv(dev); struct mtk_pwm_priv *priv = dev_get_priv(dev);
u32 offset = mtk_pwm_reg_offset[channel]; u32 offset;
switch (priv->soc->reg_ver) {
case PWM_REG_V2:
offset = mtk_pwm_reg_offset_v2[channel];
break;
default:
offset = mtk_pwm_reg_offset_v1[channel];
}
writel(val, priv->base + offset + reg); writel(val, priv->base + offset + reg);
} }
@@ -159,27 +178,38 @@ static const struct pwm_ops mtk_pwm_ops = {
static const struct mtk_pwm_soc mt7622_data = { static const struct mtk_pwm_soc mt7622_data = {
.num_pwms = 6, .num_pwms = 6,
.pwm45_fixup = false, .pwm45_fixup = false,
.reg_ver = PWM_REG_V1,
}; };
static const struct mtk_pwm_soc mt7623_data = { static const struct mtk_pwm_soc mt7623_data = {
.num_pwms = 5, .num_pwms = 5,
.pwm45_fixup = true, .pwm45_fixup = true,
.reg_ver = PWM_REG_V1,
}; };
static const struct mtk_pwm_soc mt7629_data = { static const struct mtk_pwm_soc mt7629_data = {
.num_pwms = 1, .num_pwms = 1,
.pwm45_fixup = false, .pwm45_fixup = false,
.reg_ver = PWM_REG_V1,
};
static const struct mtk_pwm_soc mt7981_data = {
.num_pwms = 2,
.pwm45_fixup = false,
.reg_ver = PWM_REG_V2,
}; };
static const struct mtk_pwm_soc mt7986_data = { static const struct mtk_pwm_soc mt7986_data = {
.num_pwms = 2, .num_pwms = 2,
.pwm45_fixup = false, .pwm45_fixup = false,
.reg_ver = PWM_REG_V1,
}; };
static const struct udevice_id mtk_pwm_ids[] = { static const struct udevice_id mtk_pwm_ids[] = {
{ .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data }, { .compatible = "mediatek,mt7622-pwm", .data = (ulong)&mt7622_data },
{ .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data }, { .compatible = "mediatek,mt7623-pwm", .data = (ulong)&mt7623_data },
{ .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data }, { .compatible = "mediatek,mt7629-pwm", .data = (ulong)&mt7629_data },
{ .compatible = "mediatek,mt7981-pwm", .data = (ulong)&mt7981_data },
{ .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data }, { .compatible = "mediatek,mt7986-pwm", .data = (ulong)&mt7986_data },
{ } { }
}; };