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ARM: dts: imxrt1050-evk: move all u-boot, dm-spl to imxrt1050-evk-u-boot.dtsi file

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At the moment a lot of u-boot,dm-spl properties are present in board .dts
file but this is not correct since u-boot,dm-spl property is u-boot
specific and must be listed into the separate imrt1050-evk-u-boot.dtsi
file. So let's move every u-boot,dm-spl property present in
imxrt1050-evk.dts to imxrt1050-evk-u-boot.dtsi file.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
This commit is contained in:
Giulio Benetti
2021-05-16 23:57:00 +02:00
committed by Stefano Babic
parent 31f0e58527
commit 1f3555d906
2 changed files with 38 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
arch/arm/dts/imxrt1050-evk-u-boot.dtsi
View File

@@ -8,6 +8,42 @@
chosen {
u-boot,dm-spl;
};
clocks {
u-boot,dm-spl;
};
soc {
u-boot,dm-spl;
};
};
&osc {
u-boot,dm-spl;
};
&clks {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&gpt1 {
@@ -19,6 +55,8 @@
};
&semc {
u-boot,dm-spl;
bank1: bank@0 {
u-boot,dm-spl;
};

13
arch/arm/dts/imxrt1050.dtsi
View File

@@ -26,10 +26,7 @@
};
clocks {
u-boot,dm-spl;
osc: osc {
u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
@@ -37,10 +34,7 @@
};
soc {
u-boot,dm-spl;
semc: semc@402f0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-semc";
reg = <0x402f0000 0x4000>;
clocks = <&clks IMXRT1050_CLK_SEMC>;
@@ -65,7 +59,6 @@
};
clks: ccm@400fc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
@@ -74,7 +67,6 @@
};
usdhc1: usdhc@402c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-usdhc";
reg = <0x402c0000 0x10000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
@@ -87,7 +79,6 @@
};
gpio1: gpio@401b8000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
@@ -99,7 +90,6 @@
};
gpio2: gpio@401bc000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
@@ -111,7 +101,6 @@
};
gpio3: gpio@401c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@@ -123,7 +112,6 @@
};
gpio4: gpio@401c4000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c4000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
@@ -135,7 +123,6 @@
};
gpio5: gpio@400c0000 {
u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x400c0000 0x4000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,