From cb5af7aa4f5119faf738542f6c066fa5bb352aa1 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:49 +0100 Subject: [PATCH 01/12] pci: xilinx: Handle size of ecam region properly Probe size of ecam from devicetree properly and cap accessible bus number accorading to ecam region size to ensure we don't go beyond hardware address space. Also disable all interrupts to ensure errors are handled silently. Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- drivers/pci/pcie_xilinx.c | 53 +++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/drivers/pci/pcie_xilinx.c b/drivers/pci/pcie_xilinx.c index a674ab04bee..63058e8e7c5 100644 --- a/drivers/pci/pcie_xilinx.c +++ b/drivers/pci/pcie_xilinx.c @@ -18,14 +18,19 @@ */ struct xilinx_pcie { void *cfg_base; + pci_size_t size; + int first_busno; }; /* Register definitions */ -#define XILINX_PCIE_REG_PSCR 0x144 -#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) -#define XILINX_PCIE_REG_RPSC 0x148 -#define XILINX_PCIE_REG_RPSC_BEN BIT(0) - +#define XILINX_PCIE_REG_BRIDGE_INFO 0x130 +#define XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_SHIFT 16 +#define XILINX_PCIE_REG_BRIDGE_INFO_ECAMSZ_MASK (0x7 << 16) +#define XILINX_PCIE_REG_INT_MASK 0x13c +#define XILINX_PCIE_REG_PSCR 0x144 +#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11) +#define XILINX_PCIE_REG_RPSC 0x148 +#define XILINX_PCIE_REG_RPSC_BEN BIT(0) /** * pcie_xilinx_link_up() - Check whether the PCIe link is up * @pcie: Pointer to the PCI controller state @@ -61,14 +66,18 @@ static int pcie_xilinx_config_address(const struct udevice *udev, pci_dev_t bdf, uint offset, void **paddress) { struct xilinx_pcie *pcie = dev_get_priv(udev); - unsigned int bus = PCI_BUS(bdf); + unsigned int bus = PCI_BUS(bdf) - pcie->first_busno; unsigned int dev = PCI_DEV(bdf); unsigned int func = PCI_FUNC(bdf); + int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); void *addr; if ((bus > 0) && !pcie_xilinx_link_up(pcie)) return -ENODEV; + if (bus > num_buses) + return -ENODEV; + /* * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are * limited to a single device each. @@ -142,20 +151,37 @@ static int pcie_xilinx_of_to_plat(struct udevice *dev) struct xilinx_pcie *pcie = dev_get_priv(dev); fdt_addr_t addr; fdt_size_t size; - u32 rpsc; addr = dev_read_addr_size(dev, &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; - pcie->cfg_base = devm_ioremap(dev, addr, size); - if (IS_ERR(pcie->cfg_base)) - return PTR_ERR(pcie->cfg_base); + pcie->cfg_base = map_physmem(addr, size, MAP_NOCACHE); + if (!pcie->cfg_base) + return -ENOMEM; + pcie->size = size; + return 0; +} - /* Enable the Bridge enable bit */ - rpsc = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC); +static int pci_xilinx_probe(struct udevice *dev) +{ + struct xilinx_pcie *pcie = dev_get_priv(dev); + u32 rpsc; + int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); + + pcie->first_busno = dev_seq(dev); + + /* Disable all interrupts */ + writel(0, pcie->cfg_base + XILINX_PCIE_REG_INT_MASK); + + /* Enable the bridge */ + rpsc = readl(pcie->cfg_base + XILINX_PCIE_REG_RPSC); rpsc |= XILINX_PCIE_REG_RPSC_BEN; - __raw_writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC); + writel(rpsc, pcie->cfg_base + XILINX_PCIE_REG_RPSC); + + /* Enable access to all possible subordinate buses */ + writel((0 << 0) | (1 << 8) | (num_buses << 16), + pcie->cfg_base + PCI_PRIMARY_BUS); return 0; } @@ -176,5 +202,6 @@ U_BOOT_DRIVER(pcie_xilinx) = { .of_match = pcie_xilinx_ids, .ops = &pcie_xilinx_ops, .of_to_plat = pcie_xilinx_of_to_plat, + .probe = pci_xilinx_probe, .priv_auto = sizeof(struct xilinx_pcie), }; From fc25cd0e1a1d5bea59c651782b93e70289d68c1f Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:50 +0100 Subject: [PATCH 02/12] pci: auto: Reduce bridge mem alignment boundary for boston Boston has a very limited memory range for PCI controllers, where 1MB can't easily fit into it. Make alignment boundary of PCI memory resource allocation a Kconfig option and default to 0x10000 for boston. Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- drivers/pci/Kconfig | 9 +++++++++ drivers/pci/pci_auto.c | 16 ++++++++-------- 2 files changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 8d02ab82ad9..289d1deb38b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -75,6 +75,15 @@ config PCI_MAP_SYSTEM_MEMORY This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still being used as virtual address. +config PCI_BRIDGE_MEM_ALIGNMENT + hex "Alignment boundary of PCI memory resource allocation" + default 0x10000 if TARGET_BOSTON + default 0x100000 + help + Specify a boundary for alignment of PCI memory resource allocation, + this is normally 0x100000 (1MB) but can be reduced to accommodate + hardware with tight bridge range if hardware allows. + config PCI_SRIOV bool "Enable Single Root I/O Virtualization support for PCI" help diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 90f81886445..b2c76b25801 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -372,8 +372,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff); if (pci_mem) { - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_mem, 0x100000); + /* Round memory allocator */ + pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT); /* * Set up memory and I/O filter limits, assume 32-bit @@ -387,8 +387,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) } if (pci_prefetch) { - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_prefetch, 0x100000); + /* Round memory allocator */ + pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT); /* * Set up memory and I/O filter limits, assume 32-bit @@ -465,8 +465,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr)); if (pci_mem) { - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_mem, 0x100000); + /* Round memory allocator */ + pciauto_region_align(pci_mem, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT); dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, ((pci_mem->bus_lower - 1) >> 16) & @@ -480,8 +480,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) &prefechable_64); prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; - /* Round memory allocator to 1MB boundary */ - pciauto_region_align(pci_prefetch, 0x100000); + /* Round memory allocator */ + pciauto_region_align(pci_prefetch, CONFIG_PCI_BRIDGE_MEM_ALIGNMENT); dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, (((pci_prefetch->bus_lower - 1) >> 16) & From 1864dfb1c457e090d2e84d14ee56d9579a898e7f Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:51 +0100 Subject: [PATCH 03/12] pci: Enable PCI_MAP_SYSTEM_MEMORY when ARCH_MAP_SYSMEM is not set For MIPS we are always looking gd->dram in virtual address so PCI_MAP_SYSTEM_MEMORY should always be enabled. If in future we ever want to make it physical we have to set ARCH_MAP_SYSMEM. Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- drivers/pci/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 289d1deb38b..14f6067fa29 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -67,6 +67,7 @@ config PCI_CONFIG_HOST_BRIDGE config PCI_MAP_SYSTEM_MEMORY bool "Map local system memory from a virtual base address" depends on MIPS + default y if !ARCH_MAP_SYSMEM help Say Y if base address of system memory is being used as a virtual address instead of a physical address (e.g. on MIPS). The PCI core will then remap From 8daa1fadc2c45bc954537a70942674e0a4cf85a8 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:52 +0100 Subject: [PATCH 04/12] ahci: DMA addressing fixes Ensure that we are using correct physical/virtual address for DMA buffer write and hardware register settings. The convention is: in ahci_ioports all pointers are virtual, that will be converted to physical address when writing to hardware registers or into sg/cmd_tbl. Also fixed 64bit physical address support for dwc_ahsata, ensure higher bits are written into registers/sg properly. Use memalign for allocating aligned buffer in dwc_ahsata so we don't have to do our own alignment in driver. Signed-off-by: Jiaxun Yang --- drivers/ata/ahci.c | 32 ++++++++++++------------- drivers/ata/dwc_ahsata.c | 44 +++++++++++++++++++---------------- drivers/ata/dwc_ahsata_priv.h | 2 -- include/ahci.h | 4 ++-- 4 files changed, 41 insertions(+), 41 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index ac869296d52..21b13fedac5 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -421,7 +421,7 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) { - phys_addr_t pa = virt_to_phys((void *)pp->cmd_tbl); + phys_addr_t pa = virt_to_phys(pp->cmd_tbl); pp->cmd_slot->opts = cpu_to_le32(opts); pp->cmd_slot->status = 0; @@ -450,7 +450,7 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) { struct ahci_ioports *pp = &(uc_priv->port[port]); void __iomem *port_mmio = pp->port_mmio; - u64 dma_addr; + phys_addr_t dma_addr; u32 port_status; void __iomem *mem; @@ -474,34 +474,32 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) * First item in chunk of DMA memory: 32-slot command table, * 32 bytes each in size */ - pp->cmd_slot = - (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); - debug("cmd_slot = %p\n", pp->cmd_slot); - mem += (AHCI_CMD_SLOT_SZ + 224); + pp->cmd_slot = (struct ahci_cmd_hdr *)mem; + mem += AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT; /* * Second item: Received-FIS area */ - pp->rx_fis = virt_to_phys((void *)mem); + pp->rx_fis = mem; mem += AHCI_RX_FIS_SZ; /* * Third item: data area for storing a single command * and its scatter-gather table */ - pp->cmd_tbl = virt_to_phys((void *)mem); - debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl); + pp->cmd_tbl = mem; mem += AHCI_CMD_TBL_HDR; - pp->cmd_tbl_sg = - (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); + pp->cmd_tbl_sg = (struct ahci_sg *)(mem); - dma_addr = (ulong)pp->cmd_slot; - writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR); - writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI); - dma_addr = (ulong)pp->rx_fis; - writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR); - writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI); + dma_addr = virt_to_phys(pp->cmd_slot); + debug("cmd_slot_dma = 0x%08llx\n", (u64)dma_addr); + writel_with_flush(lower_32_bits(dma_addr), port_mmio + PORT_LST_ADDR); + writel_with_flush(upper_32_bits(dma_addr), port_mmio + PORT_LST_ADDR_HI); + dma_addr = virt_to_phys(pp->rx_fis); + debug("rx_fis_dma = 0x%08llx\n", (u64)dma_addr); + writel_with_flush(lower_32_bits(dma_addr), port_mmio + PORT_FIS_ADDR); + writel_with_flush(upper_32_bits(dma_addr), port_mmio + PORT_FIS_ADDR_HI); #ifdef CONFIG_SUNXI_AHCI sunxi_dma_init(port_mmio); diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index a29d641343e..c2cde48c0b5 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -329,6 +329,7 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, { struct ahci_ioports *pp = &uc_priv->port[port]; struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; + phys_addr_t pa = virt_to_phys(buf); u32 sg_count, max_bytes; int i; @@ -340,9 +341,8 @@ static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port, } for (i = 0; i < sg_count; i++) { - ahci_sg->addr = - cpu_to_le32((u32)buf + i * max_bytes); - ahci_sg->addr_hi = 0; + ahci_sg->addr = cpu_to_le32(lower_32_bits(pa)); + ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa)); ahci_sg->flags_size = cpu_to_le32(0x3fffff & (buf_len < max_bytes ? (buf_len - 1) @@ -358,14 +358,14 @@ static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts) { struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot + AHCI_CMD_SLOT_SZ * cmd_slot); + phys_addr_t pa = virt_to_phys(pp->cmd_tbl); memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ); cmd_hdr->opts = cpu_to_le32(opts); cmd_hdr->status = 0; - pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff); + pp->cmd_slot->tbl_addr = cpu_to_le32(lower_32_bits(pa)); #ifdef CONFIG_PHYS_64BIT - pp->cmd_slot->tbl_addr_hi = - cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16)); + pp->cmd_slot->tbl_addr_hi = cpu_to_le32(upper_32_bits(pa)); #endif } @@ -403,7 +403,7 @@ static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, } ahci_fill_cmd_slot(pp, cmd_slot, opts); - flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); + flush_cache((ulong)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ); writel_with_flush(1 << cmd_slot, &port_mmio->ci); if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000, @@ -411,8 +411,8 @@ static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port, printf("timeout exit!\n"); return -1; } - invalidate_dcache_range((int)(pp->cmd_slot), - (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ); + invalidate_dcache_range((ulong)(pp->cmd_slot), + (ulong)(pp->cmd_slot) + AHCI_PORT_PRIV_DMA_SZ); debug("ahci_exec_ata_cmd: %d byte transferred.\n", pp->cmd_slot->status); if (!is_write) @@ -440,8 +440,9 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) { struct ahci_ioports *pp = &uc_priv->port[port]; struct sata_port_regs *port_mmio = pp->port_mmio; + phys_addr_t dma_addr; u32 port_status; - u32 mem; + void *mem; int timeout = 10000000; debug("Enter start port: %d\n", port); @@ -452,22 +453,20 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) return -1; } - mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024); + mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ); if (!mem) { printf("No mem for table!\n"); return -ENOMEM; } - mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */ - memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ); + memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); /* * First item in chunk of DMA memory: 32-slot command table, * 32 bytes each in size */ pp->cmd_slot = (struct ahci_cmd_hdr *)mem; - debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot); - mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS); + mem += AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT; /* * Second item: Received-FIS area, 256-Byte aligned @@ -480,14 +479,19 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) * and its scatter-gather table */ pp->cmd_tbl = mem; - debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl); - mem += AHCI_CMD_TBL_HDR; + pp->cmd_tbl_sg = (struct ahci_sg *)mem; writel_with_flush(0x00004444, &port_mmio->dmacr); - pp->cmd_tbl_sg = (struct ahci_sg *)mem; - writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb); - writel_with_flush(pp->rx_fis, &port_mmio->fb); + dma_addr = virt_to_phys(pp->cmd_slot); + debug("cmd_slot_dma = 0x%08llx\n", (u64)dma_addr); + writel_with_flush(lower_32_bits(dma_addr), &port_mmio->clb); + writel_with_flush(upper_32_bits(dma_addr), &port_mmio->clbu); + dma_addr = virt_to_phys(pp->cmd_slot); + debug("rx_fis_slot_dma = 0x%08llx\n", (u64)dma_addr); + writel_with_flush(lower_32_bits(dma_addr), &port_mmio->fb); + writel_with_flush(upper_32_bits(dma_addr), &port_mmio->fbu); + /* Enable FRE */ writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)), diff --git a/drivers/ata/dwc_ahsata_priv.h b/drivers/ata/dwc_ahsata_priv.h index 5b0579ae115..0c2cd5446b5 100644 --- a/drivers/ata/dwc_ahsata_priv.h +++ b/drivers/ata/dwc_ahsata_priv.h @@ -7,8 +7,6 @@ #ifndef __DWC_AHSATA_PRIV_H__ #define __DWC_AHSATA_PRIV_H__ -#define DWC_AHSATA_MAX_CMD_SLOTS 32 - /* Max host controller numbers */ #define SATA_HC_MAX_NUM 4 /* Max command queue depth per host controller */ diff --git a/include/ahci.h b/include/ahci.h index d4f0f3ce0e7..eb05cc687f6 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -137,8 +137,8 @@ struct ahci_ioports { void __iomem *port_mmio; struct ahci_cmd_hdr *cmd_slot; struct ahci_sg *cmd_tbl_sg; - ulong cmd_tbl; - u32 rx_fis; + void *cmd_tbl; + void *rx_fis; }; /** From 2b62ec62ac39723660bfeb6c0b4d336269a3adfc Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:53 +0100 Subject: [PATCH 05/12] ahci: dwc_ahsata: Generalize the driver Remove hard dependencies to arch headers, get clock from clk subsystem if arch clock function is not available, align compatible strings with devicetree binding. No functional change on existing platforms, just get it build on other platforms. Signed-off-by: Jiaxun Yang --- drivers/ata/dwc_ahsata.c | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/ata/dwc_ahsata.c b/drivers/ata/dwc_ahsata.c index c2cde48c0b5..27c24228ef8 100644 --- a/drivers/ata/dwc_ahsata.c +++ b/drivers/ata/dwc_ahsata.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -18,9 +19,11 @@ #include #include #include +#if IS_ENABLED(CONFIG_ARCH_MX5) || IS_ENABLED(CONFIG_ARCH_MX6) #include #include #include +#endif #include #include #include @@ -115,13 +118,12 @@ static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk) return 0; } -static int ahci_host_init(struct ahci_uc_priv *uc_priv) +static int ahci_host_init(struct ahci_uc_priv *uc_priv, int clk) { u32 tmp, cap_save, num_ports; int i, j, timeout = 1000; struct sata_port_regs *port_mmio = NULL; struct sata_host_regs *host_mmio = uc_priv->mmio_base; - int clk = mxc_get_clock(MXC_SATA_CLK); cap_save = readl(&host_mmio->cap); cap_save |= SATA_HOST_CAP_SSS; @@ -909,17 +911,41 @@ int dwc_ahsata_scan(struct udevice *dev) int dwc_ahsata_probe(struct udevice *dev) { struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk_bulk clk_bulk __maybe_unused; + struct clk clk __maybe_unused; + int sataclk; int ret; -#if defined(CONFIG_MX6) +#if IS_ENABLED(CONFIG_MX6) setup_sata(); #endif +#if IS_ENABLED(CONFIG_MX5) || IS_ENABLED(CONFIG_MX6) + sataclk = mxc_get_clock(MXC_SATA_CLK); +#else + ret = clk_get_bulk(dev, &clk_bulk); + if (ret) + return ret; + + ret = clk_enable_bulk(&clk_bulk); + if (ret) + return ret; + + ret = clk_get_by_name(dev, "sata", &clk); + if (ret) + return ret; + + sataclk = clk_get_rate(&clk); +#endif + if (IS_ERR_VALUE(sataclk)) { + log_err("Unable to get SATA clock rate\n"); + return -EINVAL; + } uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI; uc_priv->mmio_base = dev_read_addr_ptr(dev); /* initialize adapter */ - ret = ahci_host_init(uc_priv); + ret = ahci_host_init(uc_priv, sataclk); if (ret) return ret; @@ -961,7 +987,6 @@ U_BOOT_DRIVER(dwc_ahsata_blk) = { .ops = &dwc_ahsata_blk_ops, }; -#if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI) struct ahci_ops dwc_ahsata_ahci_ops = { .port_status = dwc_ahsata_port_status, .reset = dwc_ahsata_bus_reset, @@ -969,7 +994,9 @@ struct ahci_ops dwc_ahsata_ahci_ops = { }; static const struct udevice_id dwc_ahsata_ahci_ids[] = { + { .compatible = "fsl,imx53-ahci" }, { .compatible = "fsl,imx6q-ahci" }, + { .compatible = "fsl,imx6qp-ahci" }, { } }; @@ -980,4 +1007,3 @@ U_BOOT_DRIVER(dwc_ahsata_ahci) = { .ops = &dwc_ahsata_ahci_ops, .probe = dwc_ahsata_probe, }; -#endif From 0fd4686df5fe7a7b1783eec6ff21ffdd1c2b0467 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:54 +0100 Subject: [PATCH 06/12] MIPS: Provide dummy acpi_table.h Some drivers need this header. Provide this dummy header as riscv did. Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- arch/mips/include/asm/acpi_table.h | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 arch/mips/include/asm/acpi_table.h diff --git a/arch/mips/include/asm/acpi_table.h b/arch/mips/include/asm/acpi_table.h new file mode 100644 index 00000000000..b4139d0ba32 --- /dev/null +++ b/arch/mips/include/asm/acpi_table.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __ASM_ACPI_TABLE_H__ +#define __ASM_ACPI_TABLE_H__ + +/* + * This file is needed by some drivers. + */ + +#endif /* __ASM_ACPI_TABLE_H__ */ From 49cc0e1adceeeb8f149390e45a0aa8fa0c1e4ef4 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:55 +0100 Subject: [PATCH 07/12] MIPS: boston: Imply various options This is a PC-like platform board. Enable drivers for most on-board devices to make it useful. Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- arch/mips/Kconfig | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index eb7f3ad2376..748b5175b2e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -146,7 +146,34 @@ config TARGET_BOSTON select SUPPORTS_CPU_MIPS64_R2 select SUPPORTS_CPU_MIPS64_R6 select SUPPORTS_LITTLE_ENDIAN + imply BOOTSTD_FULL + imply CLK + imply CLK_BOSTON imply CMD_DM + imply AHCI + imply AHCI_PCI + imply CFI_FLASH + imply MTD_NOR_FLASH + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply PCH_GBE + imply PCI + imply PCI_XILINX + imply PCI_INIT_R + imply SCSI + imply SCSI_AHCI + imply SYS_NS16550 + imply SYSRESET + imply SYSRESET_CMD_POWEROFF + imply SYSRESET_SYSCON + imply USB + imply USB_EHCI_HCD + imply USB_EHCI_PCI + imply USB_XHCI_HCD + imply USB_XHCI_PCI + imply CMD_USB config TARGET_XILFPGA bool "Support Imagination Xilfpga" From a6661e260c5f98b578a636a5e265690435167981 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:56 +0100 Subject: [PATCH 08/12] MIPS: boston: Provide default env vars Provide default environment variables on image loading address to make the board useful. Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- board/imgtec/boston/Kconfig | 4 ++++ board/imgtec/boston/boston.env | 9 +++++++++ 2 files changed, 13 insertions(+) create mode 100644 board/imgtec/boston/boston.env diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig index 5537788001a..965847d9650 100644 --- a/board/imgtec/boston/Kconfig +++ b/board/imgtec/boston/Kconfig @@ -9,6 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "boston" + +config ENV_SOURCE_FILE + default "boston" + config TEXT_BASE default 0x9fc00000 if 32BIT default 0xffffffff9fc00000 if 64BIT diff --git a/board/imgtec/boston/boston.env b/board/imgtec/boston/boston.env new file mode 100644 index 00000000000..796e0fd6bf9 --- /dev/null +++ b/board/imgtec/boston/boston.env @@ -0,0 +1,9 @@ +#ifdef CONFIG_64BIT +fdt_addr_r=0xffffffff80001000 +kernel_addr_r=0xffffffff88000000 +ramdisk_addr_r=0xffffffff8b000000 +#else +fdt_addr_r=0x80001000 +kernel_addr_r=0x88000000 +ramdisk_addr_r=0x8b000000 +#endif From 964bb01f34741c9866917337afecab98262be562 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:57 +0100 Subject: [PATCH 09/12] clk: boston: Allow to get regmap from parent device In upstream devicetree, clk_boston is a child of syscon node and there is no "regmap" property for clk_boston node. Try to check parent device first to look for syscon. Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- drivers/clk/clk_boston.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c index 030ff7cc58e..71e030f463e 100644 --- a/drivers/clk/clk_boston.c +++ b/drivers/clk/clk_boston.c @@ -58,17 +58,21 @@ const struct clk_ops clk_boston_ops = { .get_rate = clk_boston_get_rate, }; -static int clk_boston_of_to_plat(struct udevice *dev) +static int clk_boston_probe(struct udevice *dev) { struct clk_boston *state = dev_get_plat(dev); struct udevice *syscon; int err; - err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, - "regmap", &syscon); - if (err) { - pr_err("unable to find syscon device\n"); - return err; + if (dev->parent && device_get_uclass_id(dev->parent) == UCLASS_SYSCON) { + syscon = dev->parent; + } else { + err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, + "regmap", &syscon); + if (err) { + pr_err("unable to find syscon device\n"); + return err; + } } state->regmap = syscon_get_regmap(syscon); @@ -91,7 +95,8 @@ U_BOOT_DRIVER(clk_boston) = { .name = "boston_clock", .id = UCLASS_CLK, .of_match = clk_boston_match, - .of_to_plat = clk_boston_of_to_plat, + .probe = clk_boston_probe, .plat_auto = sizeof(struct clk_boston), .ops = &clk_boston_ops, + .flags = DM_FLAG_PRE_RELOC, }; From d3730b53d9ae26bc0ec0f35d65d563f60800326d Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:58 +0100 Subject: [PATCH 10/12] dts/upstream: Add Makefile for MIPS It is required to make OF_UPSTREAM work. Reviewed-by: Sumit Garg Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- dts/upstream/src/mips/Makefile | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 dts/upstream/src/mips/Makefile diff --git a/dts/upstream/src/mips/Makefile b/dts/upstream/src/mips/Makefile new file mode 100644 index 00000000000..9a8f6aa3584 --- /dev/null +++ b/dts/upstream/src/mips/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ + +include $(srctree)/scripts/Makefile.dts + +targets += $(dtb-y) + +# Add any required device tree compiler flags here +DTC_FLAGS += -a 0x8 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := */*.dtb */*.dtbo From 4ba5026a0fb4a4a3825e250d8e76f07b5a5e4609 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:14:59 +0100 Subject: [PATCH 11/12] MIPS: boston: Migrate to OF_UPSTREAM We can now boot with upstream devicetree. Reviewed-by: Sumit Garg Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- arch/mips/Kconfig | 1 + arch/mips/dts/Makefile | 1 - arch/mips/dts/boston-u-boot.dtsi | 10 ++ arch/mips/dts/img,boston.dts | 222 ------------------------------- board/imgtec/boston/MAINTAINERS | 1 + configs/boston32r2_defconfig | 2 +- configs/boston32r2el_defconfig | 2 +- configs/boston32r6_defconfig | 2 +- configs/boston32r6el_defconfig | 2 +- configs/boston64r2_defconfig | 2 +- configs/boston64r2el_defconfig | 2 +- configs/boston64r6_defconfig | 2 +- configs/boston64r6el_defconfig | 2 +- 13 files changed, 20 insertions(+), 231 deletions(-) create mode 100644 arch/mips/dts/boston-u-boot.dtsi delete mode 100644 arch/mips/dts/img,boston.dts diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 748b5175b2e..733a8de4fb8 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -146,6 +146,7 @@ config TARGET_BOSTON select SUPPORTS_CPU_MIPS64_R2 select SUPPORTS_CPU_MIPS64_R6 select SUPPORTS_LITTLE_ENDIAN + imply OF_UPSTREAM imply BOOTSTD_FULL imply CLK imply CLK_BOSTON diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 14fbce597b9..5478dcd8d02 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -3,7 +3,6 @@ dtb-$(CONFIG_TARGET_AP121) += ap121.dtb dtb-$(CONFIG_TARGET_AP143) += ap143.dtb dtb-$(CONFIG_TARGET_AP152) += ap152.dtb -dtb-$(CONFIG_TARGET_BOSTON) += img,boston.dtb dtb-$(CONFIG_TARGET_MALTA) += mti,malta.dtb dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb dtb-$(CONFIG_TARGET_XILFPGA) += nexys4ddr.dtb diff --git a/arch/mips/dts/boston-u-boot.dtsi b/arch/mips/dts/boston-u-boot.dtsi new file mode 100644 index 00000000000..1b0c0a28961 --- /dev/null +++ b/arch/mips/dts/boston-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&plat_regs { + compatible = "img,boston-platform-regs", "syscon", "simple-mfd"; + bootph-all; +}; + +&clk_boston { + bootph-all; +}; diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts deleted file mode 100644 index c1a73963037..00000000000 --- a/arch/mips/dts/img,boston.dts +++ /dev/null @@ -1,222 +0,0 @@ -/dts-v1/; - -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - compatible = "img,boston"; - - chosen { - stdout-path = &uart0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "img,mips"; - reg = <0>; - clocks = <&clk_boston BOSTON_CLK_CPU>; - }; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x10000000>; - }; - - gic: interrupt-controller { - compatible = "mti,gic"; - - interrupt-controller; - #interrupt-cells = <3>; - - timer { - compatible = "mti,gic-timer"; - interrupts = ; - clocks = <&clk_boston BOSTON_CLK_CPU>; - }; - }; - - pci0: pci@10000000 { - status = "disabled"; - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - reg = <0x10000000 0x2000000>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - interrupt-parent = <&gic>; - interrupts = ; - - ranges = <0x02000000 0 0x40000000 - 0x40000000 0 0x40000000>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pci0_intc 0>, - <0 0 0 2 &pci0_intc 1>, - <0 0 0 3 &pci0_intc 2>, - <0 0 0 4 &pci0_intc 3>; - - pci0_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pci1: pci@12000000 { - status = "disabled"; - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - reg = <0x12000000 0x2000000>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - interrupt-parent = <&gic>; - interrupts = ; - - ranges = <0x02000000 0 0x20000000 - 0x20000000 0 0x20000000>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pci1_intc 0>, - <0 0 0 2 &pci1_intc 1>, - <0 0 0 3 &pci1_intc 2>, - <0 0 0 4 &pci1_intc 3>; - - pci1_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - pci2: pci@14000000 { - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - reg = <0x14000000 0x2000000>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - interrupt-parent = <&gic>; - interrupts = ; - - ranges = <0x02000000 0 0x16000000 - 0x16000000 0 0x100000>; - - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pci2_intc 0>, - <0 0 0 2 &pci2_intc 1>, - <0 0 0 3 &pci2_intc 2>, - <0 0 0 4 &pci2_intc 3>; - - pci2_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - pci2_root@0,0,0 { - compatible = "pci10ee,7021"; - reg = <0x00000000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - eg20t_bridge@1,0,0 { - compatible = "pci8086,8800"; - reg = <0x00010000 0 0 0 0>; - - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - - eg20t_mac@2,0,1 { - compatible = "pci8086,8802"; - reg = <0x00020100 0 0 0 0>; - phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>; - }; - - eg20t_gpio: eg20t_gpio@2,0,2 { - compatible = "pci8086,8803"; - reg = <0x00020200 0 0 0 0>; - - gpio-controller; - #gpio-cells = <2>; - }; - - eg20t_i2c@2,12,2 { - compatible = "pci8086,8817"; - reg = <0x00026200 0 0 0 0>; - - #address-cells = <1>; - #size-cells = <0>; - - rtc@0x68 { - compatible = "st,m41t81s"; - reg = <0x68>; - }; - }; - }; - }; - }; - - plat_regs: system-controller@17ffd000 { - compatible = "img,boston-platform-regs", "syscon"; - reg = <0x17ffd000 0x1000>; - bootph-all; - }; - - clk_boston: clock { - compatible = "img,boston-clock"; - #clock-cells = <1>; - regmap = <&plat_regs>; - bootph-all; - }; - - reboot: syscon-reboot { - compatible = "syscon-reboot"; - regmap = <&plat_regs>; - offset = <0x10>; - mask = <0x10>; - }; - - uart0: uart@17ffe000 { - compatible = "ns16550a"; - reg = <0x17ffe000 0x1000>; - reg-shift = <2>; - reg-io-width = <4>; - - interrupt-parent = <&gic>; - interrupts = ; - - clocks = <&clk_boston BOSTON_CLK_SYS>; - - bootph-all; - }; - - lcd: lcd@17fff000 { - compatible = "img,boston-lcd"; - reg = <0x17fff000 0x8>; - }; - - flash@18000000 { - compatible = "cfi-flash"; - reg = <0x18000000 0x8000000>; - bank-width = <2>; - }; -}; diff --git a/board/imgtec/boston/MAINTAINERS b/board/imgtec/boston/MAINTAINERS index 07f6156ffcb..12e1652858b 100644 --- a/board/imgtec/boston/MAINTAINERS +++ b/board/imgtec/boston/MAINTAINERS @@ -1,6 +1,7 @@ BOSTON BOARD M: Paul Burton S: Maintained +F: arch/mips/dts/boston-u-boot.dtsi F: board/imgtec/boston/ F: include/configs/boston.h F: configs/boston32r2_defconfig diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index 6f0024a6663..cb5898c3caf 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_TARGET_BOSTON=y diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index 71926429b05..4c603b69df7 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_TARGET_BOSTON=y diff --git a/configs/boston32r6_defconfig b/configs/boston32r6_defconfig index 4335d04b39e..17f7c4364a0 100644 --- a/configs/boston32r6_defconfig +++ b/configs/boston32r6_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_TARGET_BOSTON=y diff --git a/configs/boston32r6el_defconfig b/configs/boston32r6el_defconfig index b859a4f198b..e662d167fe3 100644 --- a/configs/boston32r6el_defconfig +++ b/configs/boston32r6el_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_LOAD_ADDR=0x88000000 CONFIG_ENV_ADDR=0xBFFE0000 CONFIG_TARGET_BOSTON=y diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index 70354f11716..bf5a3ead364 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_TARGET_BOSTON=y diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index eafb8c67ba7..de22344b5bb 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_TARGET_BOSTON=y diff --git a/configs/boston64r6_defconfig b/configs/boston64r6_defconfig index a6c89278512..bb339cfd5db 100644 --- a/configs/boston64r6_defconfig +++ b/configs/boston64r6_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_TARGET_BOSTON=y diff --git a/configs/boston64r6el_defconfig b/configs/boston64r6el_defconfig index 6cc227600df..260f6dfb358 100644 --- a/configs/boston64r6el_defconfig +++ b/configs/boston64r6el_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0x40000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="img,boston" +CONFIG_DEFAULT_DEVICE_TREE="img/boston" CONFIG_SYS_LOAD_ADDR=0xffffffff88000000 CONFIG_ENV_ADDR=0xFFFFFFFFBFFE0000 CONFIG_TARGET_BOSTON=y From baf4bdcdeda78874efa8e2e7875ab4a91f5aa502 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Fri, 17 May 2024 19:15:00 +0100 Subject: [PATCH 12/12] mailmap: Update email for Paul Burton Paul had left MIPS a couple of years ago, his email address is no longer valid. Replace it with his kenrel.org email, which has been used in kernel and QEMU, in case we still want to reach him. Signed-off-by: Jiaxun Yang Reviewed-by: Daniel Schwierzeck --- .mailmap | 3 ++- board/imgtec/boston/MAINTAINERS | 2 +- board/imgtec/malta/MAINTAINERS | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/.mailmap b/.mailmap index 8049856d41c..bb7c1c3869a 100644 --- a/.mailmap +++ b/.mailmap @@ -87,7 +87,8 @@ This contributor prefers not to receive mails Patrice Chotard Patrick Delaunay -Paul Burton +Paul Burton +Paul Burton Piyush Mehta Prabhakar Kushwaha Punnaiah Choudary Kalluri diff --git a/board/imgtec/boston/MAINTAINERS b/board/imgtec/boston/MAINTAINERS index 12e1652858b..b03a6487db2 100644 --- a/board/imgtec/boston/MAINTAINERS +++ b/board/imgtec/boston/MAINTAINERS @@ -1,5 +1,5 @@ BOSTON BOARD -M: Paul Burton +M: Paul Burton S: Maintained F: arch/mips/dts/boston-u-boot.dtsi F: board/imgtec/boston/ diff --git a/board/imgtec/malta/MAINTAINERS b/board/imgtec/malta/MAINTAINERS index b1cf297f4fa..252c5e45ab5 100644 --- a/board/imgtec/malta/MAINTAINERS +++ b/board/imgtec/malta/MAINTAINERS @@ -1,5 +1,5 @@ MALTA BOARD -M: Paul Burton +M: Paul Burton S: Maintained F: board/imgtec/malta/ F: include/configs/malta.h