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clock-snapdragon: Add clk_rcg_set_rate() with mnd_width=0

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Add clk_rcg_set_rate() which allows to configure clocks without programming
MND values. This is required for configuring I2C clocks on QCS404.

Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
This commit is contained in:
Sumit Garg
2023-02-01 19:28:57 +05:30
committed by Tom Rini
parent de8f42c93a
commit 22d3fcd337
2 changed files with 26 additions and 0 deletions
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24
arch/arm/mach-snapdragon/clock-snapdragon.c
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@@ -111,6 +111,30 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
clk_bcr_update(base + regs->cmd_rcgr); clk_bcr_update(base + regs->cmd_rcgr);
} }
/* root set rate for clocks with half integer and mnd_width=0 */
void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
int source)
{
u32 cfg;
/* setup src select and divider */
cfg = readl(base + regs->cfg_rcgr);
cfg &= ~CFG_MASK;
cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
/*
* Set the divider; HW permits fraction dividers (+0.5), but
* for simplicity, we will support integers only
*/
if (div)
cfg |= (2 * div - 1) & CFG_DIVIDER_MASK;
writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
/* Inform h/w to start using the new config. */
clk_bcr_update(base + regs->cmd_rcgr);
}
static int msm_clk_probe(struct udevice *dev) static int msm_clk_probe(struct udevice *dev)
{ {
struct msm_clk_priv *priv = dev_get_priv(dev); struct msm_clk_priv *priv = dev_get_priv(dev);

2
arch/arm/mach-snapdragon/clock-snapdragon.h
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@@ -42,5 +42,7 @@ void clk_enable_cbc(phys_addr_t cbcr);
void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk);
void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
int div, int m, int n, int source); int div, int m, int n, int source);
void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
int source);
#endif #endif