colin/u-boot
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arm: socfpga: spl: Notify SDM on FSBL execution

Browse Source 
Send out "HPS_STAGE_NOTIFY" mailbox command to the
Secure Device Manager (SDM) in SPL to inform SDM on
FSBL execution.

This is necessary for the SDM to recognize that the
FSBL stage has begun its execution and should be
made as early as possible in the FSBL process.

Therefore, the mailbox will initialize and send out
the notification right after the completion of timer
initialization.

Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
This commit is contained in:
Alif Zakuan Yuslaimi
2025-03-10 23:38:52 -07:00
committed by Tien Fong Chee
parent cf5b58ef6e
commit 2ab78d1dbd
4 changed files with 16 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/mach-socfpga/spl_agilex.c
View File

@@ -50,6 +50,10 @@ void board_init_f(ulong dummy)
timer_init(); timer_init();
mbox_init();
mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
sysmgr_pinmux_init(); sysmgr_pinmux_init();
ret = uclass_get_device(UCLASS_CLK, 0, &dev); ret = uclass_get_device(UCLASS_CLK, 0, &dev);
@@ -77,8 +81,6 @@ void board_init_f(ulong dummy)
} }
#endif #endif
mbox_init();
#ifdef CONFIG_CADENCE_QSPI #ifdef CONFIG_CADENCE_QSPI
mbox_qspi_open(); mbox_qspi_open();
#endif #endif

6
arch/arm/mach-socfpga/spl_agilex5.c
View File

@@ -62,6 +62,10 @@ void board_init_f(ulong dummy)
timer_init(); timer_init();
mbox_init();
mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
ret = uclass_get_device(UCLASS_CLK, 0, &dev); ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) { if (ret) {
debug("Clock init failed: %d\n", ret); debug("Clock init failed: %d\n", ret);
@@ -100,8 +104,6 @@ void board_init_f(ulong dummy)
} }
} }
mbox_init();
if (IS_ENABLED(CONFIG_CADENCE_QSPI)) if (IS_ENABLED(CONFIG_CADENCE_QSPI))
mbox_qspi_open(); mbox_qspi_open();

6
arch/arm/mach-socfpga/spl_n5x.c
View File

@@ -49,6 +49,10 @@ void board_init_f(ulong dummy)
timer_init(); timer_init();
mbox_init();
mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
sysmgr_pinmux_init(); sysmgr_pinmux_init();
preloader_console_init(); preloader_console_init();
@@ -84,8 +88,6 @@ void board_init_f(ulong dummy)
} }
#endif #endif
mbox_init();
#ifdef CONFIG_CADENCE_QSPI #ifdef CONFIG_CADENCE_QSPI
mbox_qspi_open(); mbox_qspi_open();
#endif #endif

6
arch/arm/mach-socfpga/spl_s10.c
View File

@@ -52,6 +52,10 @@ void board_init_f(ulong dummy)
socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
timer_init(); timer_init();
mbox_init();
mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
sysmgr_pinmux_init(); sysmgr_pinmux_init();
/* configuring the HPS clocks */ /* configuring the HPS clocks */
@@ -84,8 +88,6 @@ void board_init_f(ulong dummy)
} }
#endif #endif
mbox_init();
#ifdef CONFIG_CADENCE_QSPI #ifdef CONFIG_CADENCE_QSPI
mbox_qspi_open(); mbox_qspi_open();
#endif #endif