x86: Add basic support for broadwell
This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
48
arch/x86/include/asm/arch-broadwell/cpu.h
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48
arch/x86/include/asm/arch-broadwell/cpu.h
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __asm_arch_cpu_h
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#define __asm_arch_cpu_h
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/* CPU types */
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#define HASWELL_FAMILY_ULT 0x40650
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#define BROADWELL_FAMILY_ULT 0x306d0
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/* Supported CPUIDs */
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#define CPUID_HASWELL_A0 0x306c1
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#define CPUID_HASWELL_B0 0x306c2
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#define CPUID_HASWELL_C0 0x306c3
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#define CPUID_HASWELL_ULT_B0 0x40650
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#define CPUID_HASWELL_ULT 0x40651
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#define CPUID_HASWELL_HALO 0x40661
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#define CPUID_BROADWELL_C0 0x306d2
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#define CPUID_BROADWELL_D0 0x306d3
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#define CPUID_BROADWELL_E0 0x306d4
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/* Broadwell bus clock is fixed at 100MHz */
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#define BROADWELL_BCLK 100
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#define BROADWELL_FAMILY_ULT 0x306d0
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#define CORE_THREAD_COUNT_MSR 0x35
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#define MSR_VR_CURRENT_CONFIG 0x601
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#define MSR_VR_MISC_CONFIG 0x603
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#define MSR_PKG_POWER_SKU 0x614
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#define MSR_DDR_RAPL_LIMIT 0x618
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#define MSR_VR_MISC_CONFIG2 0x636
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/* Latency times in units of 1024ns. */
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#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
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#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
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#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
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#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
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#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
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#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
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void cpu_set_power_limits(int power_limit_1_time);
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#endif
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53
arch/x86/include/asm/arch-broadwell/iomap.h
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53
arch/x86/include/asm/arch-broadwell/iomap.h
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/*
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* From Coreboot soc/intel/broadwell/include/soc/iomap.h
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*
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* Copyright (C) 2016 Google Inc.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __asm_arch_iomap_h
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#define __asm_arch_iomap_h
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#define MCFG_BASE_ADDRESS 0xf0000000
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#define MCFG_BASE_SIZE 0x4000000
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#define HPET_BASE_ADDRESS 0xfed00000
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#define MCH_BASE_ADDRESS 0xfed10000
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#define MCH_BASE_SIZE 0x8000
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#define DMI_BASE_ADDRESS 0xfed18000
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#define DMI_BASE_SIZE 0x1000
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#define EP_BASE_ADDRESS 0xfed19000
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#define EP_BASE_SIZE 0x1000
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#define EDRAM_BASE_ADDRESS 0xfed80000
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#define EDRAM_BASE_SIZE 0x4000
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#define GDXC_BASE_ADDRESS 0xfed84000
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#define GDXC_BASE_SIZE 0x1000
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#define RCBA_BASE_ADDRESS 0xfed1c000
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#define RCBA_BASE_SIZE 0x4000
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#define HPET_BASE_ADDRESS 0xfed00000
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#define ACPI_BASE_ADDRESS 0x1000
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#define ACPI_BASE_SIZE 0x100
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#define GPIO_BASE_ADDRESS 0x1400
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#define GPIO_BASE_SIZE 0x400
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#define SMBUS_BASE_ADDRESS 0x0400
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#define SMBUS_BASE_SIZE 0x10
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/* Temporary addresses used before relocation */
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#define EARLY_GTT_BAR 0xe0000000
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#define EARLY_XHCI_BAR 0xd7000000
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#define EARLY_EHCI_BAR 0xd8000000
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#define EARLY_UART_BAR 0x3f8
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#define EARLY_TEMP_MMIO 0xfed08000
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#endif
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200
arch/x86/include/asm/arch-broadwell/me.h
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200
arch/x86/include/asm/arch-broadwell/me.h
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/*
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* From coreboot soc/intel/broadwell/include/soc/me.h
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*
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* Copyright (C) 2014 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _asm_arch_me_h
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#define _asm_arch_me_h
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#include <asm/me_common.h>
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#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
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#define ME_HSIO_MESSAGE (7 << 28)
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#define ME_HSIO_CMD_GETHSIOVER 1
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#define ME_HSIO_CMD_CLOSE 0
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/*
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* Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
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* to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature.
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*/
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#define PCI_ME_HFS2 0x48
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/* Infrastructure Progress Values */
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#define ME_HFS2_PHASE_ROM 0
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#define ME_HFS2_PHASE_BUP 1
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#define ME_HFS2_PHASE_UKERNEL 2
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#define ME_HFS2_PHASE_POLICY 3
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#define ME_HFS2_PHASE_MODULE_LOAD 4
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#define ME_HFS2_PHASE_UNKNOWN 5
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#define ME_HFS2_PHASE_HOST_COMM 6
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/* Current State - Based on Infra Progress values. */
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/* ROM State */
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#define ME_HFS2_STATE_ROM_BEGIN 0
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#define ME_HFS2_STATE_ROM_DISABLE 6
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/* BUP State */
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#define ME_HFS2_STATE_BUP_INIT 0
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#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
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#define ME_HFS2_STATE_BUP_FLOW_DET 4
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#define ME_HFS2_STATE_BUP_VSCC_ERR 8
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#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
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#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
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#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
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#define ME_HFS2_STATE_BUP_M3 0x11
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#define ME_HFS2_STATE_BUP_M0 0x12
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#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
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#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
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#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
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#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
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#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c
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#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f
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#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
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#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
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#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
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#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
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#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
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#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
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#define ME_HFS2_STATE_BUP_M0_CLK 0x26
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#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
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#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28
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#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
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/* Policy Module State */
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#define ME_HFS2_STATE_POLICY_ENTRY 0
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#define ME_HFS2_STATE_POLICY_RCVD_S3 3
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#define ME_HFS2_STATE_POLICY_RCVD_S4 4
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#define ME_HFS2_STATE_POLICY_RCVD_S5 5
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#define ME_HFS2_STATE_POLICY_RCVD_UPD 6
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#define ME_HFS2_STATE_POLICY_RCVD_PCR 7
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#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8
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#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
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#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
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#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb
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#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
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#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
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#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe
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#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
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#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
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/* Current PM Event Values */
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#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
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#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
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#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
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#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
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#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
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#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
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#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
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#define ME_HFS2_PMEVENT_S0MO_SXM3 7
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#define ME_HFS2_PMEVENT_SXM3_S0M0 8
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#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
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#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
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#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
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#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
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struct me_hfs2 {
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u32 bist_in_progress:1;
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u32 reserved1:2;
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u32 invoke_mebx:1;
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u32 cpu_replaced_sts:1;
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u32 mbp_rdy:1;
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u32 mfs_failure:1;
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u32 warm_reset_request:1;
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u32 cpu_replaced_valid:1;
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u32 reserved2:4;
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u32 mbp_cleared:1;
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u32 reserved3:2;
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u32 current_state:8;
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u32 current_pmevent:4;
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u32 progress_code:4;
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} __packed;
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#define PCI_ME_HFS5 0x68
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#define PCI_ME_H_GS2 0x70
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#define PCI_ME_MBP_GIVE_UP 0x01
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/* ICC Messages */
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#define ICC_SET_CLOCK_ENABLES 0x3
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#define ICC_API_VERSION_LYNXPOINT 0x00030000
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struct icc_header {
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u32 api_version;
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u32 icc_command;
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u32 icc_status;
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u32 length;
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u32 reserved;
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} __packed;
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struct icc_clock_enables_msg {
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u32 clock_enables;
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u32 clock_mask;
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u32 no_response:1;
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u32 reserved:31;
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} __packed;
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/*
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* ME to BIOS Payload Datastructures and definitions. The ordering of the
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* structures follows the ordering in the ME9 BWG.
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*/
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#define MBP_APPID_KERNEL 1
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#define MBP_APPID_INTEL_AT 3
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#define MBP_APPID_HWA 4
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#define MBP_APPID_ICC 5
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#define MBP_APPID_NFC 6
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/* Kernel items: */
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#define MBP_KERNEL_FW_VER_ITEM 1
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#define MBP_KERNEL_FW_CAP_ITEM 2
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#define MBP_KERNEL_ROM_BIST_ITEM 3
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#define MBP_KERNEL_PLAT_KEY_ITEM 4
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#define MBP_KERNEL_FW_TYPE_ITEM 5
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#define MBP_KERNEL_MFS_FAILURE_ITEM 6
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#define MBP_KERNEL_PLAT_TIME_ITEM 7
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/* Intel AT items: */
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#define MBP_INTEL_AT_STATE_ITEM 1
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/* ICC Items: */
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#define MBP_ICC_PROFILE_ITEM 1
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/* HWA Items: */
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#define MBP_HWA_REQUEST_ITEM 1
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/* NFC Items: */
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#define MBP_NFC_SUPPORT_DATA_ITEM 1
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#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
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#define MBP_IDENT(appid, item) \
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MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
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struct mbp_fw_version_name {
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u32 major_version:16;
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u32 minor_version:16;
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u32 hotfix_version:16;
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u32 build_version:16;
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} __packed;
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struct icc_address_mask {
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u16 icc_start_address;
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u16 mask;
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} __packed;
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struct mbp_icc_profile {
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u8 num_icc_profiles;
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u8 icc_profile_soft_strap;
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u8 icc_profile_index;
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u8 reserved;
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u32 icc_reg_bundles;
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struct icc_address_mask icc_address_mask[0];
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} __packed;
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struct me_bios_payload {
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struct mbp_fw_version_name *fw_version_name;
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struct mbp_mefwcaps *fw_capabilities;
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struct mbp_rom_bist_data *rom_bist_data;
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struct mbp_platform_key *platform_key;
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struct mbp_plat_type *fw_plat_type;
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struct mbp_icc_profile *icc_profile;
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struct mbp_at_state *at_state;
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u32 *mfsintegrity;
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struct mbp_plat_time *plat_time;
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struct mbp_nfc_data *nfc_data;
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};
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#endif
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58
arch/x86/include/asm/arch-broadwell/rcb.h
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58
arch/x86/include/asm/arch-broadwell/rcb.h
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __asm_arch_rcba_h
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#define __asm_arch_rcba_h
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#define PMSYNC_CONFIG 0x33c4 /* 32bit */
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#define PMSYNC_CONFIG2 0x33cc /* 32bit */
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#define DEEP_S3_POL 0x3328 /* 32bit */
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#define DEEP_S3_EN_AC (1 << 0)
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#define DEEP_S3_EN_DC (1 << 1)
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#define DEEP_S5_POL 0x3330 /* 32bit */
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#define DEEP_S5_EN_AC (1 << 14)
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#define DEEP_S5_EN_DC (1 << 15)
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#define DEEP_SX_CONFIG 0x3334 /* 32bit */
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#define DEEP_SX_WAKE_PIN_EN (1 << 2)
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#define DEEP_SX_ACPRESENT_PD (1 << 1)
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#define DEEP_SX_GP27_PIN_EN (1 << 0)
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#define PMSYNC_CONFIG 0x33c4 /* 32bit */
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#define PMSYNC_CONFIG2 0x33cc /* 32bit */
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#define RC 0x3400 /* 32bit */
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#define HPTC 0x3404 /* 32bit */
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#define GCS 0x3410 /* 32bit */
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#define BUC 0x3414 /* 32bit */
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#define PCH_DISABLE_GBE (1 << 5)
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#define FD 0x3418 /* 32bit */
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#define FDSW 0x3420 /* 8bit */
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#define DISPBDF 0x3424 /* 16bit */
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#define FD2 0x3428 /* 32bit */
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#define CG 0x341c /* 32bit */
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/* Function Disable 1 RCBA 0x3418 */
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#define PCH_DISABLE_ALWAYS (1 << 0)
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#define PCH_DISABLE_ADSPD (1 << 1)
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#define PCH_DISABLE_SATA1 (1 << 2)
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#define PCH_DISABLE_SMBUS (1 << 3)
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#define PCH_DISABLE_HD_AUDIO (1 << 4)
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#define PCH_DISABLE_EHCI2 (1 << 13)
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#define PCH_DISABLE_LPC (1 << 14)
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#define PCH_DISABLE_EHCI1 (1 << 15)
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#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
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#define PCH_DISABLE_THERMAL (1 << 24)
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#define PCH_DISABLE_SATA2 (1 << 25)
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#define PCH_DISABLE_XHCI (1 << 27)
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/* Function Disable 2 RCBA 0x3428 */
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#define PCH_DISABLE_KT (1 << 4)
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#define PCH_DISABLE_IDER (1 << 3)
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#define PCH_DISABLE_MEI2 (1 << 2)
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#define PCH_DISABLE_MEI1 (1 << 1)
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#define PCH_ENABLE_DBDF (1 << 0)
|
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|
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#endif
|
87
arch/x86/include/asm/arch-broadwell/spi.h
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87
arch/x86/include/asm/arch-broadwell/spi.h
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@@ -0,0 +1,87 @@
|
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/*
|
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* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This file is from coreboot soc/intel/broadwell/include/soc/spi.h
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
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*/
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#ifndef _BROADWELL_SPI_H_
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#define _BROADWELL_SPI_H_
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|
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/*
|
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* SPI Opcode Menu setup for SPIBAR lockdown
|
||||
* should support most common flash chips.
|
||||
*/
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||||
|
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#define SPIBAR_OFFSET 0x3800
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#define SPI_REG(x) (RCB_REG(SPIBAR_OFFSET + (x)))
|
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|
||||
/* Reigsters within the SPIBAR */
|
||||
#define SPIBAR_SSFC 0x91
|
||||
#define SPIBAR_FDOC 0xb0
|
||||
#define SPIBAR_FDOD 0xb4
|
||||
|
||||
#define SPIBAR_PREOP 0x94
|
||||
#define SPIBAR_OPTYPE 0x96
|
||||
#define SPIBAR_OPMENU_LOWER 0x98
|
||||
#define SPIBAR_OPMENU_UPPER 0x9c
|
||||
|
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#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
|
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#define SPI_OPTYPE_0 0x01 /* Write, no address */
|
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|
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#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
|
||||
#define SPI_OPTYPE_1 0x03 /* Write, address required */
|
||||
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#define SPI_OPMENU_2 0x03 /* READ: Read Data */
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#define SPI_OPTYPE_2 0x02 /* Read, address required */
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#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
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#define SPI_OPTYPE_3 0x00 /* Read, no address */
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#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
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#define SPI_OPTYPE_4 0x03 /* Write, address required */
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#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
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#define SPI_OPTYPE_5 0x00 /* Read, no address */
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||||
#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
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#define SPI_OPTYPE_6 0x03 /* Write, address required */
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||||
#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
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#define SPI_OPTYPE_7 0x02 /* Read, address required */
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||||
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
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(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
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||||
#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
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(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
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||||
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||||
#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
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(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
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(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
|
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(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
|
||||
|
||||
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
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||||
|
||||
#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
|
||||
#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
|
||||
#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
|
||||
#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
|
||||
#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
|
||||
#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
|
||||
#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
|
||||
#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
|
||||
#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
|
||||
#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
|
||||
#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
|
||||
#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
|
||||
#define SPIBAR_FADDR 0x08 /* SPI flash address */
|
||||
#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
|
||||
#define SPIBAR_SSFS 0x90
|
||||
#define SPIBAR_SSFS_ERROR (1 << 3)
|
||||
#define SPIBAR_SSFS_DONE (1 << 2)
|
||||
#define SPIBAR_SSFC 0x91
|
||||
#define SPIBAR_SSFC_DATA (1 << 14)
|
||||
#define SPIBAR_SSFC_GO (1 << 1)
|
||||
|
||||
#endif
|
Reference in New Issue
Block a user