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clk: meson: fix clk81 divider calculation

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clk81 divider is 0 based (meaning that 0 value in the register means
divide by 1). Fix clk81 rate calculation for this.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Jerome Brunet
2018-11-13 11:38:38 +01:00
committed by Tom Rini
parent 61927d286d
commit 2fa77bd125
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/clk_meson.c
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@@ -600,7 +600,8 @@ static unsigned long meson_clk81_get_rate(struct clk *clk)
reg = readl(priv->addr + HHI_MPEG_CLK_CNTL); reg = readl(priv->addr + HHI_MPEG_CLK_CNTL);
reg = reg & ((1 << 7) - 1); reg = reg & ((1 << 7) - 1);
return parent_rate / reg; /* clk81 divider is zero based */
return parent_rate / (reg + 1);
} }
static long mpll_rate_from_params(unsigned long parent_rate, static long mpll_rate_from_params(unsigned long parent_rate,