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Revert "riscv: image: Add new image type for RV64"

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This reverts commit 14a4792a71 as
discussed in [1].

[1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Mayuresh Chitale
2025-05-29 03:30:51 +00:00
committed by Leo Yu-Chi Liang
parent 29a2025d77
commit 31e215fde8
2 changed files with 2 additions and 4 deletions
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3
boot/image.c
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@@ -92,8 +92,7 @@ static const table_entry_t uimage_arch[] = {
{ IH_ARCH_ARC, "arc", "ARC", }, { IH_ARCH_ARC, "arc", "ARC", },
{ IH_ARCH_X86_64, "x86_64", "AMD x86_64", }, { IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
{ IH_ARCH_XTENSA, "xtensa", "Xtensa", }, { IH_ARCH_XTENSA, "xtensa", "Xtensa", },
{ IH_ARCH_RISCV, "riscv", "RISC-V 32 Bit",}, { IH_ARCH_RISCV, "riscv", "RISC-V", },
{ IH_ARCH_RISCV64, "riscv64", "RISC-V 64 Bit",},
{ -1, "", "", }, { -1, "", "", },
}; };

3
include/image.h
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@@ -138,8 +138,7 @@ enum {
IH_ARCH_ARC, /* Synopsys DesignWare ARC */ IH_ARCH_ARC, /* Synopsys DesignWare ARC */
IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */
IH_ARCH_XTENSA, /* Xtensa */ IH_ARCH_XTENSA, /* Xtensa */
IH_ARCH_RISCV, /* RISC-V 32 bit*/ IH_ARCH_RISCV, /* RISC-V */
IH_ARCH_RISCV64, /* RISC-V 64 bit*/
IH_ARCH_COUNT, IH_ARCH_COUNT,
}; };