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dra7xx: Enable USB_PHY3 32KHz clock

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DRA7xx has a 32KHz PHY clock for USB_PHY3 that must be enabled
for USB1 instance in Super-Speed.

Signed-off-by: Roger Quadros <rogerq@ti.com>
This commit is contained in:
Roger Quadros
2016-05-23 17:37:49 +03:00
committed by Tom Rini
parent 55efadde7e
commit 3599774eec
3 changed files with 14 additions and 2 deletions
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1
arch/arm/include/asm/omap_common.h
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@@ -145,6 +145,7 @@ struct prcm_regs {
u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
u32 cm_coreaon_usb_phy3_core_clkctrl;
u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */