clk: aspeed: Add support for SD clock
Add code to enable the SD clock on the ast2500 SoC. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Eddie James <eajames@linux.ibm.com>
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@@ -22,6 +22,8 @@
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#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
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#define SCU_PCLK_DIV_SHIFT 23
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#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
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#define SCU_SDCLK_DIV_SHIFT 12
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#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT)
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#define SCU_HPLL_DENUM_SHIFT 0
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#define SCU_HPLL_DENUM_MASK 0x1f
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#define SCU_HPLL_NUM_SHIFT 5
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@@ -107,6 +109,7 @@
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#define SCU_CLKSTOP_MAC1 (1 << 20)
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#define SCU_CLKSTOP_MAC2 (1 << 21)
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#define SCU_CLKSTOP_SDCLK (1 << 27)
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#define SCU_D2PLL_EXT1_OFF (1 << 0)
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#define SCU_D2PLL_EXT1_BYPASS (1 << 1)
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