From 6bbe348bfccea3b967aa398a6d46bcb8439d093f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 26 Jan 2025 19:48:22 +0200 Subject: [PATCH 01/24] spi: tegra20_slink: fix CS polarity setup Add missing configuration of chip select polarity. Default polarity is LOW, which satisfies most cases but some devices require HIGH polarity and will not work. Signed-off-by: Svyatoslav Ryhel --- drivers/spi/tegra20_slink.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/spi/tegra20_slink.c b/drivers/spi/tegra20_slink.c index d54a5049205..097d9164175 100644 --- a/drivers/spi/tegra20_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -29,7 +29,10 @@ DECLARE_GLOBAL_DATA_PTR; #define SLINK_CMD_IDLE_SCLK_PULL_LOW (2 << 24) #define SLINK_CMD_IDLE_SCLK_PULL_HIGH (3 << 24) #define SLINK_CMD_IDLE_SCLK_MASK (3 << 24) +#define SLINK_CMD_CS_POL3 BIT(23) +#define SLINK_CMD_CS_POL2 BIT(22) #define SLINK_CMD_CK_SDA BIT(21) +#define SLINK_CMD_CS_POL1 BIT(20) #define SLINK_CMD_CS_POL BIT(13) #define SLINK_CMD_CS_VAL BIT(12) #define SLINK_CMD_CS_SOFT BIT(11) @@ -64,6 +67,13 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_TIMEOUT 1000 #define TEGRA_SPI_MAX_FREQ 52000000 +unsigned int cmd_cs_pol_bit[] = { + SLINK_CMD_CS_POL, + SLINK_CMD_CS_POL1, + SLINK_CMD_CS_POL2, + SLINK_CMD_CS_POL3, +}; + struct spi_regs { u32 command; /* SLINK_COMMAND_0 register */ u32 command2; /* SLINK_COMMAND2_0 reg */ @@ -155,6 +165,14 @@ static int tegra30_spi_claim_bus(struct udevice *dev) writel(reg, ®s->status); debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); + /* Update the polarity bits */ + if (priv->mode & SPI_CS_HIGH) + setbits_le32(&priv->regs->command, + cmd_cs_pol_bit[spi_chip_select(dev)]); + else + clrbits_le32(&priv->regs->command, + cmd_cs_pol_bit[spi_chip_select(dev)]); + /* Set master mode and sw controlled CS */ reg = readl(®s->command); reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT; From 0edc47ba7332c72ae1d18003a18c717143cab78b Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 24 Mar 2025 21:24:45 +0200 Subject: [PATCH 02/24] ARM: tegra: clock: take in account PLLD/D2 enable bit on clock_set_rate PLLD and PLLD2 clocks possess a unique enable bit within their miscellaneous register. Take this into account when using clock_set_rate function. Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/clock.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index a375693481e..4f0cc19df50 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -703,6 +703,12 @@ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) else writel(base_reg, &simple_pll->pll_base); + /* PLLD and PLLD2 are only clocks which have ENABLE bit */ + if (clkid == CLOCK_ID_DISPLAY) + setbits_le32(&pll->pll_misc, BIT(PLLD_CLKENABLE)); + if (clkid == CLOCK_ID_DISPLAY2) + setbits_le32(&simple_pll->pll_misc, BIT(PLLD_CLKENABLE)); + /* * Changing clocks was never intended in the U-Boot for Tegra. * If a clock is changed after clock_init() the parent rate is wrong. From 212757af3a3b53ee4ab5aa48ce9a1192aab4d2df Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 25 Mar 2025 09:51:47 +0200 Subject: [PATCH 03/24] ARM: tegra: clock: fix PLLD2 info table entry on Tegra124 and Tegra210 Historically, PLLD2 mirrored PLLD's layout on Tegra30 and 114. However, with the introduction of Tegra124, this changed. This layout alteration was not considered, and it now requires a corrective action to prevent future complications. Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/tegra124/clock.c | 4 ++-- arch/arm/mach-tegra/tegra210/clock.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index 0ea212f80e2..8a6735d71af 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -598,8 +598,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */ - { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, - .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, + .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 04708f97144..d1ede5238dd 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -668,8 +668,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = { .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */ { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0, .lock_ena = 0, .lock_det = 0, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLS (gone)*/ - { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07, - .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */ + { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, + .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLD2 */ { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F, .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */ }; From 782bd104b696d9a10999f285a68d87e4fc85acb6 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 29 Mar 2025 13:02:03 +0200 Subject: [PATCH 04/24] sysreset: diverge GPIO reset and poweroff configs per-phase GPIO reset and power-off functionality depends on device tree data, which is often absent in SPL or TPL. To address this, incorporate PHASE_ into the config option and add Kconfig option or each phase. Adjust SYSRESET_GPIO and POWEROFF_GPIO uses to address possible regressions. Signed-off-by: Svyatoslav Ryhel --- board/sifive/unleashed/Kconfig | 1 + board/sifive/unmatched/Kconfig | 1 + configs/ge_b1x5v2_defconfig | 1 + configs/microblaze-generic_defconfig | 1 + drivers/sysreset/Kconfig | 45 ++++++++++++++++++++++++++++ drivers/sysreset/Makefile | 4 +-- 6 files changed, 51 insertions(+), 2 deletions(-) diff --git a/board/sifive/unleashed/Kconfig b/board/sifive/unleashed/Kconfig index 5d842c36cfc..bf4a00d6f7f 100644 --- a/board/sifive/unleashed/Kconfig +++ b/board/sifive/unleashed/Kconfig @@ -49,6 +49,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply SPI_FLASH_ISSI imply SYSRESET imply SYSRESET_GPIO + imply SPL_SYSRESET_GPIO if SPL imply CMD_I2C endif diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig index bc1f33bde30..991dd23f1d4 100644 --- a/board/sifive/unmatched/Kconfig +++ b/board/sifive/unmatched/Kconfig @@ -48,6 +48,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply PHY_MSCC imply SYSRESET imply SYSRESET_GPIO + imply SPL_SYSRESET_GPIO if SPL imply CMD_I2C endif diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index fec4b67aee2..b8cca3c74df 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -116,6 +116,7 @@ CONFIG_MXC_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_CMD_POWEROFF=y CONFIG_POWEROFF_GPIO=y +CONFIG_SPL_POWEROFF_GPIO=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 08f8bdb4240..7497d20ee64 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -97,6 +97,7 @@ CONFIG_SYS_NS16550=y CONFIG_XILINX_UARTLITE=y CONFIG_XILINX_SPI=y CONFIG_SYSRESET_GPIO=y +CONFIG_SPL_SYSRESET_GPIO=y CONFIG_SYSRESET_MICROBLAZE=y CONFIG_WDT=y CONFIG_XILINX_TB_WATCHDOG=y diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 475540ffac7..4972905482a 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -71,6 +71,27 @@ config POWEROFF_GPIO Support for system poweroff using a GPIO pin. This can be used for systems having a single GPIO to trigger a system poweroff. +config SPL_POWEROFF_GPIO + bool "Enable support for GPIO poweroff driver in SPL" + depends on DM_GPIO && SPL + help + Support for system poweroff using a GPIO pin in SPL. This can be used + for systems having a single GPIO to trigger a system poweroff. + +config TPL_POWEROFF_GPIO + bool "Enable support for GPIO poweroff driver in TPL" + depends on DM_GPIO && TPL + help + Support for system poweroff using a GPIO pin in TPL. This can be used + for systems having a single GPIO to trigger a system poweroff. + +config VPL_POWEROFF_GPIO + bool "Enable support for GPIO poweroff driver in VPL" + depends on DM_GPIO && VPL + help + Support for system poweroff using a GPIO pin in VPL. This can be used + for systems having a single GPIO to trigger a system poweroff. + config SYSRESET_GPIO bool "Enable support for GPIO reset driver" depends on DM_GPIO @@ -79,6 +100,30 @@ config SYSRESET_GPIO example on Microblaze where reset logic can be controlled via GPIO pin which triggers cpu reset. +config SPL_SYSRESET_GPIO + bool "Enable support for GPIO reset driver in SPL" + depends on DM_GPIO && SPL + help + Reset support via GPIO pin connected reset logic in SPL. This is used + for example on Microblaze where reset logic can be controlled via + GPIO pin which triggers cpu reset. + +config TPL_SYSRESET_GPIO + bool "Enable support for GPIO reset driver in TPL" + depends on DM_GPIO && TPL + help + Reset support via GPIO pin connected reset logic in TPL. This is used + for example on Microblaze where reset logic can be controlled via + GPIO pin which triggers cpu reset. + +config VPL_SYSRESET_GPIO + bool "Enable support for GPIO reset driver in VPL" + depends on DM_GPIO && VPL + help + Reset support via GPIO pin connected reset logic in VPL. This is used + for example on Microblaze where reset logic can be controlled via + GPIO pin which triggers cpu reset. + config SYSRESET_MAX77663 bool "Enable support for MAX77663 PMIC System Reset" depends on DM_PMIC_MAX77663 diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 796fc9effa5..ded91a4d325 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -8,8 +8,8 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o obj-$(CONFIG_ARCH_STI) += sysreset_sti.o obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o obj-$(CONFIG_SYSRESET_CV1800B) += sysreset_cv1800b.o -obj-$(CONFIG_POWEROFF_GPIO) += poweroff_gpio.o -obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o +obj-$(CONFIG_$(PHASE_)POWEROFF_GPIO) += poweroff_gpio.o +obj-$(CONFIG_$(PHASE_)SYSRESET_GPIO) += sysreset_gpio.o obj-$(CONFIG_$(PHASE_)SYSRESET_MAX77663) += sysreset_max77663.o obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o From e69eeffb59c9cc338dcc518450f370aebe5a7374 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 24 Mar 2025 21:25:17 +0200 Subject: [PATCH 05/24] video: tegra20: dsi: add Tegra20 support Existing Tegra30 DSI configuration is fully compatible with Tegra20. Signed-off-by: Svyatoslav Ryhel --- drivers/video/tegra20/tegra-dsi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra20/tegra-dsi.c index a2a22fa0fe2..a96fba01ee4 100644 --- a/drivers/video/tegra20/tegra-dsi.c +++ b/drivers/video/tegra20/tegra-dsi.c @@ -1129,6 +1129,7 @@ static const struct video_bridge_ops tegra_dsi_bridge_ops = { }; static const struct udevice_id tegra_dsi_bridge_ids[] = { + { .compatible = "nvidia,tegra20-dsi", .data = DSI_V0 }, { .compatible = "nvidia,tegra30-dsi", .data = DSI_V0 }, { .compatible = "nvidia,tegra114-dsi", .data = DSI_V1 }, { .compatible = "nvidia,tegra124-dsi", .data = DSI_V1 }, From 901f249fdb6b0ab287ac23dbdcada44c4c697dca Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 29 Mar 2025 16:49:53 +0200 Subject: [PATCH 06/24] video: rename tegra20 to tegra Since this set of drivers suports four Tegra SoC generations, lets name it just 'tegra'. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Peter Robinson --- drivers/video/Kconfig | 2 +- drivers/video/Makefile | 2 +- drivers/video/{tegra20 => tegra}/Kconfig | 0 drivers/video/{tegra20 => tegra}/Makefile | 0 drivers/video/{tegra20 => tegra}/mipi-phy.c | 0 drivers/video/{tegra20 => tegra}/mipi-phy.h | 0 drivers/video/{tegra20 => tegra}/tegra-dc.c | 0 drivers/video/{tegra20 => tegra}/tegra-dc.h | 0 drivers/video/{tegra20 => tegra}/tegra-dsi.c | 0 drivers/video/{tegra20 => tegra}/tegra-dsi.h | 0 drivers/video/{tegra20 => tegra}/tegra-hdmi.c | 0 drivers/video/{tegra20 => tegra}/tegra-hdmi.h | 0 drivers/video/{tegra20 => tegra}/tegra-host1x.c | 0 drivers/video/{tegra20 => tegra}/tegra-mipi.c | 0 drivers/video/{tegra20 => tegra}/tegra-pwm-backlight.c | 0 15 files changed, 2 insertions(+), 2 deletions(-) rename drivers/video/{tegra20 => tegra}/Kconfig (100%) rename drivers/video/{tegra20 => tegra}/Makefile (100%) rename drivers/video/{tegra20 => tegra}/mipi-phy.c (100%) rename drivers/video/{tegra20 => tegra}/mipi-phy.h (100%) rename drivers/video/{tegra20 => tegra}/tegra-dc.c (100%) rename drivers/video/{tegra20 => tegra}/tegra-dc.h (100%) rename drivers/video/{tegra20 => tegra}/tegra-dsi.c (100%) rename drivers/video/{tegra20 => tegra}/tegra-dsi.h (100%) rename drivers/video/{tegra20 => tegra}/tegra-hdmi.c (100%) rename drivers/video/{tegra20 => tegra}/tegra-hdmi.h (100%) rename drivers/video/{tegra20 => tegra}/tegra-host1x.c (100%) rename drivers/video/{tegra20 => tegra}/tegra-mipi.c (100%) rename drivers/video/{tegra20 => tegra}/tegra-pwm-backlight.c (100%) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index df607303616..afcdb16c599 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -819,7 +819,7 @@ config VIDEO_TEGRA124 source "drivers/video/bridge/Kconfig" -source "drivers/video/tegra20/Kconfig" +source "drivers/video/tegra/Kconfig" source "drivers/video/imx/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index bbd5db46553..a4896c0dfce 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -85,4 +85,4 @@ obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp/ obj-y += bridge/ obj-y += sunxi/ -obj-y += tegra20/ +obj-y += tegra/ diff --git a/drivers/video/tegra20/Kconfig b/drivers/video/tegra/Kconfig similarity index 100% rename from drivers/video/tegra20/Kconfig rename to drivers/video/tegra/Kconfig diff --git a/drivers/video/tegra20/Makefile b/drivers/video/tegra/Makefile similarity index 100% rename from drivers/video/tegra20/Makefile rename to drivers/video/tegra/Makefile diff --git a/drivers/video/tegra20/mipi-phy.c b/drivers/video/tegra/mipi-phy.c similarity index 100% rename from drivers/video/tegra20/mipi-phy.c rename to drivers/video/tegra/mipi-phy.c diff --git a/drivers/video/tegra20/mipi-phy.h b/drivers/video/tegra/mipi-phy.h similarity index 100% rename from drivers/video/tegra20/mipi-phy.h rename to drivers/video/tegra/mipi-phy.h diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra/tegra-dc.c similarity index 100% rename from drivers/video/tegra20/tegra-dc.c rename to drivers/video/tegra/tegra-dc.c diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra/tegra-dc.h similarity index 100% rename from drivers/video/tegra20/tegra-dc.h rename to drivers/video/tegra/tegra-dc.h diff --git a/drivers/video/tegra20/tegra-dsi.c b/drivers/video/tegra/tegra-dsi.c similarity index 100% rename from drivers/video/tegra20/tegra-dsi.c rename to drivers/video/tegra/tegra-dsi.c diff --git a/drivers/video/tegra20/tegra-dsi.h b/drivers/video/tegra/tegra-dsi.h similarity index 100% rename from drivers/video/tegra20/tegra-dsi.h rename to drivers/video/tegra/tegra-dsi.h diff --git a/drivers/video/tegra20/tegra-hdmi.c b/drivers/video/tegra/tegra-hdmi.c similarity index 100% rename from drivers/video/tegra20/tegra-hdmi.c rename to drivers/video/tegra/tegra-hdmi.c diff --git a/drivers/video/tegra20/tegra-hdmi.h b/drivers/video/tegra/tegra-hdmi.h similarity index 100% rename from drivers/video/tegra20/tegra-hdmi.h rename to drivers/video/tegra/tegra-hdmi.h diff --git a/drivers/video/tegra20/tegra-host1x.c b/drivers/video/tegra/tegra-host1x.c similarity index 100% rename from drivers/video/tegra20/tegra-host1x.c rename to drivers/video/tegra/tegra-host1x.c diff --git a/drivers/video/tegra20/tegra-mipi.c b/drivers/video/tegra/tegra-mipi.c similarity index 100% rename from drivers/video/tegra20/tegra-mipi.c rename to drivers/video/tegra/tegra-mipi.c diff --git a/drivers/video/tegra20/tegra-pwm-backlight.c b/drivers/video/tegra/tegra-pwm-backlight.c similarity index 100% rename from drivers/video/tegra20/tegra-pwm-backlight.c rename to drivers/video/tegra/tegra-pwm-backlight.c From 6255eb30a186191734efc472c35d187fe5dcd101 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 29 Mar 2025 16:53:24 +0200 Subject: [PATCH 07/24] video: move tegra124 into common tegra dir Place Tegra124 SOR and eDP implenetation into common Tegra driver folder until it is integrated into existing setup. Signed-off-by: Svyatoslav Ryhel --- drivers/video/Kconfig | 8 -------- drivers/video/Makefile | 1 - drivers/video/tegra/Kconfig | 8 ++++++++ drivers/video/tegra/Makefile | 2 ++ drivers/video/tegra/TODO | 5 +++++ drivers/video/{ => tegra}/tegra124/Makefile | 0 drivers/video/{ => tegra}/tegra124/display.c | 0 drivers/video/{ => tegra}/tegra124/displayport.h | 0 drivers/video/{ => tegra}/tegra124/dp.c | 0 drivers/video/{ => tegra}/tegra124/sor.c | 0 drivers/video/{ => tegra}/tegra124/sor.h | 0 11 files changed, 15 insertions(+), 9 deletions(-) create mode 100644 drivers/video/tegra/TODO rename drivers/video/{ => tegra}/tegra124/Makefile (100%) rename drivers/video/{ => tegra}/tegra124/display.c (100%) rename drivers/video/{ => tegra}/tegra124/displayport.h (100%) rename drivers/video/{ => tegra}/tegra124/dp.c (100%) rename drivers/video/{ => tegra}/tegra124/sor.c (100%) rename drivers/video/{ => tegra}/tegra124/sor.h (100%) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index afcdb16c599..d343dfb061b 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -809,14 +809,6 @@ source "drivers/video/stm32/Kconfig" source "drivers/video/tidss/Kconfig" -config VIDEO_TEGRA124 - bool "Enable video support on Tegra124" - help - Tegra124 supports many video output options including eDP and - HDMI. At present only eDP is supported by U-Boot. This option - enables this support which can be used on devices which - have an eDP display connected. - source "drivers/video/bridge/Kconfig" source "drivers/video/tegra/Kconfig" diff --git a/drivers/video/Makefile b/drivers/video/Makefile index a4896c0dfce..74df5711d18 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -34,7 +34,6 @@ obj-$(CONFIG_BACKLIGHT_LP855x) += lp855x_backlight.o obj-${CONFIG_EXYNOS_FB} += exynos/ obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/ obj-${CONFIG_VIDEO_STM32} += stm32/ -obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ obj-${CONFIG_$(PHASE_)VIDEO_TIDSS} += tidss/ obj-y += ti/ diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig index 598f9ea1f21..3d610036a1f 100644 --- a/drivers/video/tegra/Kconfig +++ b/drivers/video/tegra/Kconfig @@ -36,3 +36,11 @@ config TEGRA_BACKLIGHT_PWM select VIDEO_TEGRA20 help Tegra DC dependent backlight. + +config VIDEO_TEGRA124 + bool "Enable video support on Tegra124" + help + Tegra124 supports many video output options including eDP and + HDMI. At present only eDP is supported by U-Boot. This option + enables this support which can be used on devices which + have an eDP display connected. diff --git a/drivers/video/tegra/Makefile b/drivers/video/tegra/Makefile index 78521405749..cd4cf72b3e5 100644 --- a/drivers/video/tegra/Makefile +++ b/drivers/video/tegra/Makefile @@ -5,3 +5,5 @@ obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o obj-$(CONFIG_VIDEO_HDMI_TEGRA) += tegra-hdmi.o obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o + +obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ diff --git a/drivers/video/tegra/TODO b/drivers/video/tegra/TODO new file mode 100644 index 00000000000..1c8c2389a18 --- /dev/null +++ b/drivers/video/tegra/TODO @@ -0,0 +1,5 @@ +Existence of separate Tegra124 video implementations is not an ideal solution +since generic video setup for Tegra already has Tegra124 support of some degree. +It is not possible at the time of this note is written to integrate T124 SOR +and DP without possible regressions. Tegra124 setup for SOR and DP should be +incorporated into existing setup once such opportunity occurs. diff --git a/drivers/video/tegra124/Makefile b/drivers/video/tegra/tegra124/Makefile similarity index 100% rename from drivers/video/tegra124/Makefile rename to drivers/video/tegra/tegra124/Makefile diff --git a/drivers/video/tegra124/display.c b/drivers/video/tegra/tegra124/display.c similarity index 100% rename from drivers/video/tegra124/display.c rename to drivers/video/tegra/tegra124/display.c diff --git a/drivers/video/tegra124/displayport.h b/drivers/video/tegra/tegra124/displayport.h similarity index 100% rename from drivers/video/tegra124/displayport.h rename to drivers/video/tegra/tegra124/displayport.h diff --git a/drivers/video/tegra124/dp.c b/drivers/video/tegra/tegra124/dp.c similarity index 100% rename from drivers/video/tegra124/dp.c rename to drivers/video/tegra/tegra124/dp.c diff --git a/drivers/video/tegra124/sor.c b/drivers/video/tegra/tegra124/sor.c similarity index 100% rename from drivers/video/tegra124/sor.c rename to drivers/video/tegra/tegra124/sor.c diff --git a/drivers/video/tegra124/sor.h b/drivers/video/tegra/tegra124/sor.h similarity index 100% rename from drivers/video/tegra124/sor.h rename to drivers/video/tegra/tegra124/sor.h From 59701a489149bc2dfec4cbf1e99c5d701c40903b Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 29 Mar 2025 17:00:20 +0200 Subject: [PATCH 08/24] video: tegra: drop prefix from file names Dir name is enough. Signed-off-by: Svyatoslav Ryhel --- drivers/video/tegra/Makefile | 10 +++++----- .../{tegra-pwm-backlight.c => dc-pwm-backlight.c} | 2 +- drivers/video/tegra/{tegra-dc.c => dc.c} | 2 +- drivers/video/tegra/{tegra-dc.h => dc.h} | 0 drivers/video/tegra/{tegra-dsi.c => dsi.c} | 4 ++-- drivers/video/tegra/{tegra-dsi.h => dsi.h} | 0 drivers/video/tegra/{tegra-hdmi.c => hdmi.c} | 4 ++-- drivers/video/tegra/{tegra-hdmi.h => hdmi.h} | 0 drivers/video/tegra/{tegra-host1x.c => host1x.c} | 0 drivers/video/tegra/{tegra-mipi.c => mipi.c} | 0 10 files changed, 11 insertions(+), 11 deletions(-) rename drivers/video/tegra/{tegra-pwm-backlight.c => dc-pwm-backlight.c} (99%) rename drivers/video/tegra/{tegra-dc.c => dc.c} (99%) rename drivers/video/tegra/{tegra-dc.h => dc.h} (100%) rename drivers/video/tegra/{tegra-dsi.c => dsi.c} (99%) rename drivers/video/tegra/{tegra-dsi.h => dsi.h} (100%) rename drivers/video/tegra/{tegra-hdmi.c => hdmi.c} (99%) rename drivers/video/tegra/{tegra-hdmi.h => hdmi.h} (100%) rename drivers/video/tegra/{tegra-host1x.c => host1x.c} (100%) rename drivers/video/tegra/{tegra-mipi.c => mipi.c} (100%) diff --git a/drivers/video/tegra/Makefile b/drivers/video/tegra/Makefile index cd4cf72b3e5..4602b49ee73 100644 --- a/drivers/video/tegra/Makefile +++ b/drivers/video/tegra/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-$(CONFIG_HOST1X_TEGRA) += tegra-host1x.o -obj-$(CONFIG_VIDEO_TEGRA20) += tegra-dc.o -obj-$(CONFIG_VIDEO_DSI_TEGRA30) += tegra-dsi.o tegra-mipi.o mipi-phy.o -obj-$(CONFIG_VIDEO_HDMI_TEGRA) += tegra-hdmi.o -obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += tegra-pwm-backlight.o +obj-$(CONFIG_HOST1X_TEGRA) += host1x.o +obj-$(CONFIG_VIDEO_TEGRA20) += dc.o +obj-$(CONFIG_VIDEO_DSI_TEGRA30) += dsi.o mipi.o mipi-phy.o +obj-$(CONFIG_VIDEO_HDMI_TEGRA) += hdmi.o +obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += dc-pwm-backlight.o obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ diff --git a/drivers/video/tegra/tegra-pwm-backlight.c b/drivers/video/tegra/dc-pwm-backlight.c similarity index 99% rename from drivers/video/tegra/tegra-pwm-backlight.c rename to drivers/video/tegra/dc-pwm-backlight.c index 998f0df1991..eff10b5563e 100644 --- a/drivers/video/tegra/tegra-pwm-backlight.c +++ b/drivers/video/tegra/dc-pwm-backlight.c @@ -15,7 +15,7 @@ #include #include -#include "tegra-dc.h" +#include "dc.h" #define TEGRA_PWM_BL_MIN_BRIGHTNESS 0x10 #define TEGRA_PWM_BL_MAX_BRIGHTNESS 0xFF diff --git a/drivers/video/tegra/tegra-dc.c b/drivers/video/tegra/dc.c similarity index 99% rename from drivers/video/tegra/tegra-dc.c rename to drivers/video/tegra/dc.c index 1f43153ff27..f0e3d2c993f 100644 --- a/drivers/video/tegra/tegra-dc.c +++ b/drivers/video/tegra/dc.c @@ -19,7 +19,7 @@ #include #include -#include "tegra-dc.h" +#include "dc.h" /* Holder of Tegra per-SOC DC differences */ struct tegra_dc_soc_info { diff --git a/drivers/video/tegra/tegra-dc.h b/drivers/video/tegra/dc.h similarity index 100% rename from drivers/video/tegra/tegra-dc.h rename to drivers/video/tegra/dc.h diff --git a/drivers/video/tegra/tegra-dsi.c b/drivers/video/tegra/dsi.c similarity index 99% rename from drivers/video/tegra/tegra-dsi.c rename to drivers/video/tegra/dsi.c index a96fba01ee4..bc308869f4e 100644 --- a/drivers/video/tegra/tegra-dsi.c +++ b/drivers/video/tegra/dsi.c @@ -24,8 +24,8 @@ #include #include -#include "tegra-dc.h" -#include "tegra-dsi.h" +#include "dc.h" +#include "dsi.h" #include "mipi-phy.h" /* List of supported DSI bridges */ diff --git a/drivers/video/tegra/tegra-dsi.h b/drivers/video/tegra/dsi.h similarity index 100% rename from drivers/video/tegra/tegra-dsi.h rename to drivers/video/tegra/dsi.h diff --git a/drivers/video/tegra/tegra-hdmi.c b/drivers/video/tegra/hdmi.c similarity index 99% rename from drivers/video/tegra/tegra-hdmi.c rename to drivers/video/tegra/hdmi.c index bda69919d92..bfb48b25187 100644 --- a/drivers/video/tegra/tegra-hdmi.c +++ b/drivers/video/tegra/hdmi.c @@ -22,8 +22,8 @@ #include #include -#include "tegra-dc.h" -#include "tegra-hdmi.h" +#include "dc.h" +#include "hdmi.h" #define DDCCI_ENTRY_ADDR 0x37 #define DDCCI_SOURSE_ADDR 0x51 diff --git a/drivers/video/tegra/tegra-hdmi.h b/drivers/video/tegra/hdmi.h similarity index 100% rename from drivers/video/tegra/tegra-hdmi.h rename to drivers/video/tegra/hdmi.h diff --git a/drivers/video/tegra/tegra-host1x.c b/drivers/video/tegra/host1x.c similarity index 100% rename from drivers/video/tegra/tegra-host1x.c rename to drivers/video/tegra/host1x.c diff --git a/drivers/video/tegra/tegra-mipi.c b/drivers/video/tegra/mipi.c similarity index 100% rename from drivers/video/tegra/tegra-mipi.c rename to drivers/video/tegra/mipi.c From 3b929a1b7bb284a97d3af7ab23d1eff736a274c1 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 29 Mar 2025 17:18:12 +0200 Subject: [PATCH 09/24] video: tegra: adjust DC and DSI config names Fix DC and DSI config names to reflect more generic nature of existing Tegra video drivers. Signed-off-by: Svyatoslav Ryhel --- board/toradex/colibri_t20/colibri_t20.c | 2 +- configs/endeavoru_defconfig | 2 +- configs/grouper_defconfig | 2 +- configs/harmony_defconfig | 2 +- configs/ideapad-yoga-11_defconfig | 2 +- configs/medcom-wide_defconfig | 2 +- configs/mocha_defconfig | 2 +- configs/paz00_defconfig | 2 +- configs/picasso_defconfig | 2 +- configs/qc750_defconfig | 2 +- configs/seaboard_defconfig | 2 +- configs/surface-rt_defconfig | 2 +- configs/tec_defconfig | 2 +- configs/transformer_t20_defconfig | 2 +- configs/transformer_t30_defconfig | 2 +- configs/ventana_defconfig | 2 +- configs/x3_t30_defconfig | 2 +- drivers/video/tegra/Kconfig | 39 ++++++++++++++----------- drivers/video/tegra/Makefile | 4 +-- 19 files changed, 41 insertions(+), 36 deletions(-) diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 6425fa881ea..d432fd2b843 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -147,7 +147,7 @@ void pin_mux_usb(void) } #endif -#ifdef CONFIG_VIDEO_TEGRA20 +#ifdef CONFIG_VIDEO_TEGRA /* * Routine: pin_mux_display * Description: setup the pin muxes/tristate values for the LCD interface) diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig index fb3d7fc6238..c85994b44b8 100644 --- a/configs/endeavoru_defconfig +++ b/configs/endeavoru_defconfig @@ -83,5 +83,5 @@ CONFIG_VIDEO=y CONFIG_VIDEO_BRIDGE=y # CONFIG_VIDEO_LOGO is not set CONFIG_VIDEO_LCD_ENDEAVORU=y -CONFIG_VIDEO_DSI_TEGRA30=y +CONFIG_VIDEO_DSI_TEGRA=y CONFIG_TEGRA_BACKLIGHT_PWM=y diff --git a/configs/grouper_defconfig b/configs/grouper_defconfig index b98f23a4baf..016fc60b41a 100644 --- a/configs/grouper_defconfig +++ b/configs/grouper_defconfig @@ -88,4 +88,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4e41 CONFIG_CI_UDC=y CONFIG_VIDEO=y # CONFIG_VIDEO_LOGO is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index fa8fe24ca38..9fa9c12918b 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -64,5 +64,5 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y # CONFIG_VIDEO_BPP8 is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y CONFIG_CONSOLE_SCROLL_LINES=10 diff --git a/configs/ideapad-yoga-11_defconfig b/configs/ideapad-yoga-11_defconfig index bc7f615cdf0..b77110ed840 100644 --- a/configs/ideapad-yoga-11_defconfig +++ b/configs/ideapad-yoga-11_defconfig @@ -83,4 +83,4 @@ CONFIG_CI_UDC=y CONFIG_VIDEO=y # CONFIG_VIDEO_LOGO is not set CONFIG_VIDEO_BRIDGE_PARADE_DP501=y -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index 737a0613ce1..d99addadf86 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -53,4 +53,4 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y # CONFIG_VIDEO_BPP8 is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/mocha_defconfig b/configs/mocha_defconfig index dfeb16ac08e..66cf81d3c79 100644 --- a/configs/mocha_defconfig +++ b/configs/mocha_defconfig @@ -89,4 +89,4 @@ CONFIG_VIDEO_FONT_16X32=y # CONFIG_VIDEO_LOGO is not set CONFIG_VIDEO_LCD_SHARP_LQ079L1SX01=y CONFIG_BACKLIGHT_LP855x=y -CONFIG_VIDEO_DSI_TEGRA30=y +CONFIG_VIDEO_DSI_TEGRA=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index b8645d66619..af2cb712e06 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -53,5 +53,5 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y # CONFIG_VIDEO_BPP8 is not set CONFIG_I2C_EDID=y -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y CONFIG_CONSOLE_SCROLL_LINES=10 diff --git a/configs/picasso_defconfig b/configs/picasso_defconfig index fe1eeb6ed10..6a83df919b5 100644 --- a/configs/picasso_defconfig +++ b/configs/picasso_defconfig @@ -81,4 +81,4 @@ CONFIG_CI_UDC=y CONFIG_VIDEO=y # CONFIG_VIDEO_LOGO is not set # CONFIG_VIDEO_BPP8 is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/qc750_defconfig b/configs/qc750_defconfig index a42860dc9ba..9104cc084be 100644 --- a/configs/qc750_defconfig +++ b/configs/qc750_defconfig @@ -80,4 +80,4 @@ CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_VIDEO=y # CONFIG_VIDEO_LOGO is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index eeb911a7805..21375f233f0 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -60,5 +60,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y # CONFIG_VIDEO_BPP8 is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y CONFIG_CONSOLE_SCROLL_LINES=10 diff --git a/configs/surface-rt_defconfig b/configs/surface-rt_defconfig index 24fca755dc5..da19b34e64a 100644 --- a/configs/surface-rt_defconfig +++ b/configs/surface-rt_defconfig @@ -79,4 +79,4 @@ CONFIG_USB_GADGET=y CONFIG_CI_UDC=y CONFIG_VIDEO=y # CONFIG_VIDEO_LOGO is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 2f686105700..7cb13f9f5af 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -53,4 +53,4 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_SMSC95XX=y CONFIG_VIDEO=y # CONFIG_VIDEO_BPP8 is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/transformer_t20_defconfig b/configs/transformer_t20_defconfig index 50b5885bb09..c934e1a2410 100644 --- a/configs/transformer_t20_defconfig +++ b/configs/transformer_t20_defconfig @@ -81,4 +81,4 @@ CONFIG_CI_UDC=y CONFIG_VIDEO=y # CONFIG_VIDEO_LOGO is not set # CONFIG_VIDEO_BPP8 is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig index 3e2db0cb7d0..828634dc590 100644 --- a/configs/transformer_t30_defconfig +++ b/configs/transformer_t30_defconfig @@ -93,5 +93,5 @@ CONFIG_VIDEO=y CONFIG_VIDEO_BRIDGE=y # CONFIG_VIDEO_LOGO is not set CONFIG_VIDEO_BRIDGE_TOSHIBA_TC358768=y -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y CONFIG_VIDEO_HDMI_TEGRA=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index c24fdcad533..3afa04dd10a 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -53,5 +53,5 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_VIDEO=y # CONFIG_VIDEO_BPP8 is not set -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y CONFIG_CONSOLE_SCROLL_LINES=10 diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig index e738bd232d0..4252526992d 100644 --- a/configs/x3_t30_defconfig +++ b/configs/x3_t30_defconfig @@ -87,4 +87,4 @@ CONFIG_VIDEO_BRIDGE=y # CONFIG_VIDEO_LOGO is not set CONFIG_BACKLIGHT_LM3533=y CONFIG_VIDEO_BRIDGE_SOLOMON_SSD2825=y -CONFIG_VIDEO_TEGRA20=y +CONFIG_VIDEO_TEGRA=y diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig index 3d610036a1f..d3b8dbb2826 100644 --- a/drivers/video/tegra/Kconfig +++ b/drivers/video/tegra/Kconfig @@ -2,40 +2,45 @@ config HOST1X_TEGRA bool "NVIDIA Tegra host1x BUS support" depends on SIMPLE_BUS -config VIDEO_TEGRA20 - bool "Enable Display Controller support on Tegra20 and Tegra 30" +config VIDEO_TEGRA + bool "Enable Display Controller support on Tegra devices" depends on OF_CONTROL select HOST1X_TEGRA help - T20/T30 support video output to an attached LCD panel as well as - other options such as HDMI. Only the LCD is supported in U-Boot. - This option enables this support which can be used on devices which - have an LCD display connected. + Enable support for Display Controller found in Tegra SoC. The + Display Controller Complex integrates two independent display + controllers. Each display controller is capable of interfacing + to an external display device, which can be a parallel interface + or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD. + Direct interface is supported directly to most LCD displays with + TFT or TFT-like interface. -config VIDEO_DSI_TEGRA30 - bool "Enable Tegra 30 DSI support" +config VIDEO_DSI_TEGRA + bool "Enable DSI controller support on Tegra devices" depends on VIDEO_BRIDGE && PANEL && DM_GPIO - select VIDEO_TEGRA20 + select VIDEO_TEGRA select VIDEO_MIPI_DSI help - T30 has native support for DSI panels. This option enables support - for such panels which can be used on endeavoru and tf600t. + Enable support for the Display Serial Interface (DSI) found in + Tegra SoC. It is a MIPI standard serial bitstream, intended to + provide a low pin count interface to a display panel. config VIDEO_HDMI_TEGRA - bool "Enable Tegra HDMI support" + bool "Enable HDMI support on Tegra devices" depends on VIDEO_BRIDGE && DM_I2C select I2C_EDID - select VIDEO_TEGRA20 + select VIDEO_TEGRA help - Tegra has native support for HDMI. This option enables support - for such connection and can be used for any supported device. + Enable support for the High-Definition Multimedia Interface (HDMI) + found in Tegra SoC. config TEGRA_BACKLIGHT_PWM bool "Enable Tegra DC PWM backlight support" depends on BACKLIGHT - select VIDEO_TEGRA20 + select VIDEO_TEGRA help - Tegra DC dependent backlight. + Enable support for the Display Controller dependent PWM backlight + found in the Tegra SoC and usually used with DSI panels. config VIDEO_TEGRA124 bool "Enable video support on Tegra124" diff --git a/drivers/video/tegra/Makefile b/drivers/video/tegra/Makefile index 4602b49ee73..3c50a0ba3c3 100644 --- a/drivers/video/tegra/Makefile +++ b/drivers/video/tegra/Makefile @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0+ obj-$(CONFIG_HOST1X_TEGRA) += host1x.o -obj-$(CONFIG_VIDEO_TEGRA20) += dc.o -obj-$(CONFIG_VIDEO_DSI_TEGRA30) += dsi.o mipi.o mipi-phy.o +obj-$(CONFIG_VIDEO_TEGRA) += dc.o +obj-$(CONFIG_VIDEO_DSI_TEGRA) += dsi.o mipi.o mipi-phy.o obj-$(CONFIG_VIDEO_HDMI_TEGRA) += hdmi.o obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += dc-pwm-backlight.o From 0d12f77ce5307956b13a568e6848a91d4d9d48eb Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sat, 1 Feb 2025 16:02:45 +0200 Subject: [PATCH 10/24] power: pmic: add the basic CPCAP PMIC support The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC whose main purpose was power control. It was used in a wide variety of Motorola products, both Tegra and OMAP based. The most notable devices using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2. Signed-off-by: Svyatoslav Ryhel --- drivers/power/pmic/Kconfig | 10 ++ drivers/power/pmic/Makefile | 1 + drivers/power/pmic/cpcap.c | 90 ++++++++++++++ include/power/cpcap.h | 238 ++++++++++++++++++++++++++++++++++++ 4 files changed, 339 insertions(+) create mode 100644 drivers/power/pmic/cpcap.c create mode 100644 include/power/cpcap.h diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index bbcbcee4c35..5a61cd45b8c 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -295,6 +295,16 @@ config DM_PMIC_SANDBOX Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt +config DM_PMIC_CPCAP + bool "Enable Driver Model for Motorola CPCAP" + help + The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC + whose main purpose is power control. It was used in a wide variety of + Motorola products, both Tegra and OMAP based. The most notable devices + using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2. + Unlike most PMICs, this one is not I2C based; it uses the SPI bus. The + core driver provides both read and write access to the device registers. + config PMIC_S5M8767 bool "Enable Driver Model for the Samsung S5M8767 PMIC" ---help--- diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 4232cb4f5f9..2210b1a64ae 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_PMIC_TPS65219) += tps65219.o obj-$(CONFIG_PMIC_TPS65941) += tps65941.o obj-$(CONFIG_PMIC_RAA215300) += raa215300.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o +obj-$(CONFIG_$(PHASE_)DM_PMIC_CPCAP) += cpcap.o ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y) obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o diff --git a/drivers/power/pmic/cpcap.c b/drivers/power/pmic/cpcap.c new file mode 100644 index 00000000000..4923255f0a7 --- /dev/null +++ b/drivers/power/pmic/cpcap.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int cpcap_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) +{ + u8 buf[4]; + u16 data = *(u16 *)buff; + int ret; + + buf[0] = ((reg >> 8) & 0xff) | 0x80; + buf[1] = reg & 0xff; + buf[2] = data >> 8 & 0xff; + buf[3] = data & 0xff; + + ret = dm_spi_xfer(dev, 32, buf, NULL, SPI_XFER_ONCE); + + log_debug("%s: reg 0x%x, data 0x%04x, ret %d\n", __func__, reg, data, ret); + + return ret; +} + +static int cpcap_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + u8 buf[4]; + int ret; + + buf[0] = (reg >> 8) & 0xff; + buf[1] = reg & 0xff; + buf[2] = 0; + buf[3] = 0; + + ret = dm_spi_xfer(dev, 32, buf, buf, SPI_XFER_ONCE); + *buff = (buf[2] << 8) | buf[3]; + + log_debug("%s: reg 0x%x, data 0x%04x, ret %d\n", __func__, reg, *buff, ret); + return ret; +} + +static int cpcap_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + int ret; + + ret = spi_claim_bus(slave); + if (ret) { + log_err("SPI bus allocation failed (%d)\n", ret); + return ret; + } + + u16 id = pmic_reg_read(dev, CPCAP_REG_VERSC1); + + u16 ven = (id >> 6) & 0x7; + u16 rev = ((id >> 3) & 0x7) | ((id << 3) & 0x38); + + log_debug("%s: vendor %s rev: %i.%i (%x)\n", __func__, + ven == CPCAP_VENDOR_ST ? "ST" : "TI", + CPCAP_REVISION_MAJOR(rev), CPCAP_REVISION_MINOR(rev), + rev); + return 0; +} + +static struct dm_pmic_ops cpcap_ops = { + .read = cpcap_read, + .write = cpcap_write, +}; + +static const struct udevice_id cpcap_ids[] = { + { .compatible = "motorola,cpcap" }, + { .compatible = "st,6556002" }, + { } +}; + +U_BOOT_DRIVER(pmic_cpcap) = { + .name = "cpcap_pmic", + .id = UCLASS_PMIC, + .of_match = cpcap_ids, + .probe = cpcap_probe, + .ops = &cpcap_ops, +}; diff --git a/include/power/cpcap.h b/include/power/cpcap.h new file mode 100644 index 00000000000..ecc0ece6518 --- /dev/null +++ b/include/power/cpcap.h @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _CPCAP_H_ +#define _CPCAP_H_ + +#define CPCAP_VENDOR_ST 0 +#define CPCAP_VENDOR_TI 1 + +#define CPCAP_REVISION_MAJOR(r) (((r) >> 4) + 1) +#define CPCAP_REVISION_MINOR(r) ((r) & 0xf) + +#define CPCAP_REVISION_1_0 0x08 +#define CPCAP_REVISION_1_1 0x09 +#define CPCAP_REVISION_2_0 0x10 +#define CPCAP_REVISION_2_1 0x11 +#define CPCAP_REVISION_3_1 0x19 + +/* CPCAP registers */ +#define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */ +#define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */ +#define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */ +#define CPCAP_REG_INT4 0x000c /* Interrupt 4 */ +#define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */ +#define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */ +#define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */ +#define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */ +#define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */ +#define CPCAP_REG_INTS2 0x0024 /* Interrupt Sense 2 */ +#define CPCAP_REG_INTS3 0x0028 /* Interrupt Sense 3 */ +#define CPCAP_REG_INTS4 0x002c /* Interrupt Sense 4 */ +#define CPCAP_REG_ASSIGN1 0x0030 /* Resource Assignment 1 */ +#define CPCAP_REG_ASSIGN2 0x0034 /* Resource Assignment 2 */ +#define CPCAP_REG_ASSIGN3 0x0038 /* Resource Assignment 3 */ +#define CPCAP_REG_ASSIGN4 0x003c /* Resource Assignment 4 */ +#define CPCAP_REG_ASSIGN5 0x0040 /* Resource Assignment 5 */ +#define CPCAP_REG_ASSIGN6 0x0044 /* Resource Assignment 6 */ +#define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */ +#define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */ + +#define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */ +#define CPCAP_REG_MIM1 0x0204 /* Macro Interrupt Mask 1 */ +#define CPCAP_REG_MI2 0x0208 /* Macro Interrupt 2 */ +#define CPCAP_REG_MIM2 0x020c /* Macro Interrupt Mask 2 */ +#define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */ +#define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */ + +#define CPCAP_REG_PC1 0x021c /* Power Cut 1 */ +#define CPCAP_REG_PC2 0x0220 /* Power Cut 2 */ +#define CPCAP_REG_BPEOL 0x0224 /* BP and EOL */ +#define CPCAP_REG_PGC 0x0228 /* Power Gate and Control */ +#define CPCAP_REG_MT1 0x022c /* Memory Transfer 1 */ +#define CPCAP_REG_MT2 0x0230 /* Memory Transfer 2 */ +#define CPCAP_REG_MT3 0x0234 /* Memory Transfer 3 */ +#define CPCAP_REG_PF 0x0238 /* Print Format */ + +#define CPCAP_REG_SCC 0x0400 /* System Clock Control */ +#define CPCAP_REG_SW1 0x0404 /* Stop Watch 1 */ +#define CPCAP_REG_SW2 0x0408 /* Stop Watch 2 */ +#define CPCAP_REG_UCTM 0x040c /* UC Turbo Mode */ +#define CPCAP_REG_TOD1 0x0410 /* Time of Day 1 */ +#define CPCAP_REG_TOD2 0x0414 /* Time of Day 2 */ +#define CPCAP_REG_TODA1 0x0418 /* Time of Day Alarm 1 */ +#define CPCAP_REG_TODA2 0x041c /* Time of Day Alarm 2 */ +#define CPCAP_REG_DAY 0x0420 /* Day */ +#define CPCAP_REG_DAYA 0x0424 /* Day Alarm */ +#define CPCAP_REG_VAL1 0x0428 /* Validity 1 */ +#define CPCAP_REG_VAL2 0x042c /* Validity 2 */ + +#define CPCAP_REG_SDVSPLL 0x0600 /* Switcher DVS and PLL */ +#define CPCAP_REG_SI2CC1 0x0604 /* Switcher I2C Control 1 */ +#define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */ +#define CPCAP_REG_S1C1 0x060c /* Switcher 1 Control 1 */ +#define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */ +#define CPCAP_REG_S2C1 0x0614 /* Switcher 2 Control 1 */ +#define CPCAP_REG_S2C2 0x0618 /* Switcher 2 Control 2 */ +#define CPCAP_REG_S3C 0x061c /* Switcher 3 Control */ +#define CPCAP_REG_S4C1 0x0620 /* Switcher 4 Control 1 */ +#define CPCAP_REG_S4C2 0x0624 /* Switcher 4 Control 2 */ +#define CPCAP_REG_S5C 0x0628 /* Switcher 5 Control */ +#define CPCAP_REG_S6C 0x062c /* Switcher 6 Control */ +#define CPCAP_REG_VCAMC 0x0630 /* VCAM Control */ +#define CPCAP_REG_VCSIC 0x0634 /* VCSI Control */ +#define CPCAP_REG_VDACC 0x0638 /* VDAC Control */ +#define CPCAP_REG_VDIGC 0x063c /* VDIG Control */ +#define CPCAP_REG_VFUSEC 0x0640 /* VFUSE Control */ +#define CPCAP_REG_VHVIOC 0x0644 /* VHVIO Control */ +#define CPCAP_REG_VSDIOC 0x0648 /* VSDIO Control */ +#define CPCAP_REG_VPLLC 0x064c /* VPLL Control */ +#define CPCAP_REG_VRF1C 0x0650 /* VRF1 Control */ +#define CPCAP_REG_VRF2C 0x0654 /* VRF2 Control */ +#define CPCAP_REG_VRFREFC 0x0658 /* VRFREF Control */ +#define CPCAP_REG_VWLAN1C 0x065c /* VWLAN1 Control */ +#define CPCAP_REG_VWLAN2C 0x0660 /* VWLAN2 Control */ +#define CPCAP_REG_VSIMC 0x0664 /* VSIM Control */ +#define CPCAP_REG_VVIBC 0x0668 /* VVIB Control */ +#define CPCAP_REG_VUSBC 0x066c /* VUSB Control */ +#define CPCAP_REG_VUSBINT1C 0x0670 /* VUSBINT1 Control */ +#define CPCAP_REG_VUSBINT2C 0x0674 /* VUSBINT2 Control */ +#define CPCAP_REG_URT 0x0678 /* Useroff Regulator Trigger */ +#define CPCAP_REG_URM1 0x067c /* Useroff Regulator Mask 1 */ +#define CPCAP_REG_URM2 0x0680 /* Useroff Regulator Mask 2 */ + +#define CPCAP_REG_VAUDIOC 0x0800 /* VAUDIO Control */ +#define CPCAP_REG_CC 0x0804 /* Codec Control */ +#define CPCAP_REG_CDI 0x0808 /* Codec Digital Interface */ +#define CPCAP_REG_SDAC 0x080c /* Stereo DAC */ +#define CPCAP_REG_SDACDI 0x0810 /* Stereo DAC Digital Interface */ +#define CPCAP_REG_TXI 0x0814 /* TX Inputs */ +#define CPCAP_REG_TXMP 0x0818 /* TX MIC PGA's */ +#define CPCAP_REG_RXOA 0x081c /* RX Output Amplifiers */ +#define CPCAP_REG_RXVC 0x0820 /* RX Volume Control */ +#define CPCAP_REG_RXCOA 0x0824 /* RX Codec to Output Amps */ +#define CPCAP_REG_RXSDOA 0x0828 /* RX Stereo DAC to Output Amps */ +#define CPCAP_REG_RXEPOA 0x082c /* RX External PGA to Output Amps */ +#define CPCAP_REG_RXLL 0x0830 /* RX Low Latency */ +#define CPCAP_REG_A2LA 0x0834 /* A2 Loudspeaker Amplifier */ +#define CPCAP_REG_MIPIS1 0x0838 /* MIPI Slimbus 1 */ +#define CPCAP_REG_MIPIS2 0x083c /* MIPI Slimbus 2 */ +#define CPCAP_REG_MIPIS3 0x0840 /* MIPI Slimbus 3. */ +#define CPCAP_REG_LVAB 0x0844 /* LMR Volume and A4 Balanced. */ + +#define CPCAP_REG_CCC1 0x0a00 /* Coulomb Counter Control 1 */ +#define CPCAP_REG_CRM 0x0a04 /* Charger and Reverse Mode */ +#define CPCAP_REG_CCCC2 0x0a08 /* Coincell and Coulomb Ctr Ctrl 2 */ +#define CPCAP_REG_CCS1 0x0a0c /* Coulomb Counter Sample 1 */ +#define CPCAP_REG_CCS2 0x0a10 /* Coulomb Counter Sample 2 */ +#define CPCAP_REG_CCA1 0x0a14 /* Coulomb Counter Accumulator 1 */ +#define CPCAP_REG_CCA2 0x0a18 /* Coulomb Counter Accumulator 2 */ +#define CPCAP_REG_CCM 0x0a1c /* Coulomb Counter Mode */ +#define CPCAP_REG_CCO 0x0a20 /* Coulomb Counter Offset */ +#define CPCAP_REG_CCI 0x0a24 /* Coulomb Counter Integrator */ + +#define CPCAP_REG_ADCC1 0x0c00 /* A/D Converter Configuration 1 */ +#define CPCAP_REG_ADCC2 0x0c04 /* A/D Converter Configuration 2 */ +#define CPCAP_REG_ADCD0 0x0c08 /* A/D Converter Data 0 */ +#define CPCAP_REG_ADCD1 0x0c0c /* A/D Converter Data 1 */ +#define CPCAP_REG_ADCD2 0x0c10 /* A/D Converter Data 2 */ +#define CPCAP_REG_ADCD3 0x0c14 /* A/D Converter Data 3 */ +#define CPCAP_REG_ADCD4 0x0c18 /* A/D Converter Data 4 */ +#define CPCAP_REG_ADCD5 0x0c1c /* A/D Converter Data 5 */ +#define CPCAP_REG_ADCD6 0x0c20 /* A/D Converter Data 6 */ +#define CPCAP_REG_ADCD7 0x0c24 /* A/D Converter Data 7 */ +#define CPCAP_REG_ADCAL1 0x0c28 /* A/D Converter Calibration 1 */ +#define CPCAP_REG_ADCAL2 0x0c2c /* A/D Converter Calibration 2 */ + +#define CPCAP_REG_USBC1 0x0e00 /* USB Control 1 */ +#define CPCAP_REG_USBC2 0x0e04 /* USB Control 2 */ +#define CPCAP_REG_USBC3 0x0e08 /* USB Control 3 */ +#define CPCAP_REG_UVIDL 0x0e0c /* ULPI Vendor ID Low */ +#define CPCAP_REG_UVIDH 0x0e10 /* ULPI Vendor ID High */ +#define CPCAP_REG_UPIDL 0x0e14 /* ULPI Product ID Low */ +#define CPCAP_REG_UPIDH 0x0e18 /* ULPI Product ID High */ +#define CPCAP_REG_UFC1 0x0e1c /* ULPI Function Control 1 */ +#define CPCAP_REG_UFC2 0x0e20 /* ULPI Function Control 2 */ +#define CPCAP_REG_UFC3 0x0e24 /* ULPI Function Control 3 */ +#define CPCAP_REG_UIC1 0x0e28 /* ULPI Interface Control 1 */ +#define CPCAP_REG_UIC2 0x0e2c /* ULPI Interface Control 2 */ +#define CPCAP_REG_UIC3 0x0e30 /* ULPI Interface Control 3 */ +#define CPCAP_REG_USBOTG1 0x0e34 /* USB OTG Control 1 */ +#define CPCAP_REG_USBOTG2 0x0e38 /* USB OTG Control 2 */ +#define CPCAP_REG_USBOTG3 0x0e3c /* USB OTG Control 3 */ +#define CPCAP_REG_UIER1 0x0e40 /* USB Interrupt Enable Rising 1 */ +#define CPCAP_REG_UIER2 0x0e44 /* USB Interrupt Enable Rising 2 */ +#define CPCAP_REG_UIER3 0x0e48 /* USB Interrupt Enable Rising 3 */ +#define CPCAP_REG_UIEF1 0x0e4c /* USB Interrupt Enable Falling 1 */ +#define CPCAP_REG_UIEF2 0x0e50 /* USB Interrupt Enable Falling 1 */ +#define CPCAP_REG_UIEF3 0x0e54 /* USB Interrupt Enable Falling 1 */ +#define CPCAP_REG_UIS 0x0e58 /* USB Interrupt Status */ +#define CPCAP_REG_UIL 0x0e5c /* USB Interrupt Latch */ +#define CPCAP_REG_USBD 0x0e60 /* USB Debug */ +#define CPCAP_REG_SCR1 0x0e64 /* Scratch 1 */ +#define CPCAP_REG_SCR2 0x0e68 /* Scratch 2 */ +#define CPCAP_REG_SCR3 0x0e6c /* Scratch 3 */ + +#define CPCAP_REG_VMC 0x0eac /* Video Mux Control */ +#define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */ +#define CPCAP_REG_GPIO0 0x0eb4 /* GPIO 0 Control */ + +#define CPCAP_REG_GPIO1 0x0ebc /* GPIO 1 Control */ + +#define CPCAP_REG_GPIO2 0x0ec4 /* GPIO 2 Control */ + +#define CPCAP_REG_GPIO3 0x0ecc /* GPIO 3 Control */ + +#define CPCAP_REG_GPIO4 0x0ed4 /* GPIO 4 Control */ + +#define CPCAP_REG_GPIO5 0x0edc /* GPIO 5 Control */ + +#define CPCAP_REG_GPIO6 0x0ee4 /* GPIO 6 Control */ + +#define CPCAP_REG_MDLC 0x1000 /* Main Display Lighting Control */ +#define CPCAP_REG_KLC 0x1004 /* Keypad Lighting Control */ +#define CPCAP_REG_ADLC 0x1008 /* Aux Display Lighting Control */ +#define CPCAP_REG_REDC 0x100c /* Red Triode Control */ +#define CPCAP_REG_GREENC 0x1010 /* Green Triode Control */ +#define CPCAP_REG_BLUEC 0x1014 /* Blue Triode Control */ +#define CPCAP_REG_CFC 0x1018 /* Camera Flash Control */ +#define CPCAP_REG_ABC 0x101c /* Adaptive Boost Control */ +#define CPCAP_REG_BLEDC 0x1020 /* Bluetooth LED Control */ +#define CPCAP_REG_CLEDC 0x1024 /* Camera Privacy LED Control */ + +#define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */ +#define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */ +#define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */ +#define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */ + +#define CPCAP_REG_OW1 0x1214 /* One Wire 1 Control */ + +#define CPCAP_REG_OW2C 0x1220 /* One Wire 2 Command */ +#define CPCAP_REG_OW2D 0x1224 /* One Wire 2 Data */ +#define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */ +#define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */ + +#define CPCAP_REG_OW2 0x1234 /* One Wire 2 Control */ + +#define CPCAP_REG_OW3C 0x1240 /* One Wire 3 Command */ +#define CPCAP_REG_OW3D 0x1244 /* One Wire 3 Data */ +#define CPCAP_REG_OW3I 0x1248 /* One Wire 3 Interrupt */ +#define CPCAP_REG_OW3IE 0x124c /* One Wire 3 Interrupt Enable */ + +#define CPCAP_REG_OW3 0x1254 /* One Wire 3 Control */ +#define CPCAP_REG_GCAIC 0x1258 /* GCAI Clock Control */ +#define CPCAP_REG_GCAIM 0x125c /* GCAI GPIO Mode */ +#define CPCAP_REG_LGDIR 0x1260 /* LMR GCAI GPIO Direction */ +#define CPCAP_REG_LGPU 0x1264 /* LMR GCAI GPIO Pull-up */ +#define CPCAP_REG_LGPIN 0x1268 /* LMR GCAI GPIO Pin */ +#define CPCAP_REG_LGMASK 0x126c /* LMR GCAI GPIO Mask */ +#define CPCAP_REG_LDEB 0x1270 /* LMR Debounce Settings */ +#define CPCAP_REG_LGDET 0x1274 /* LMR GCAI Detach Detect */ +#define CPCAP_REG_LMISC 0x1278 /* LMR Misc Bits */ +#define CPCAP_REG_LMACE 0x127c /* LMR Mace IC Support */ + +#define CPCAP_REG_TEST 0x7c00 /* Test */ + +#define CPCAP_REG_ST_TEST1 0x7d08 /* ST Test1 */ + +#define CPCAP_REG_ST_TEST2 0x7d18 /* ST Test2 */ + +#endif /* _CPCAP_H_ */ From 4dc27f964403e4e0dcc894d388050dd13503b6d7 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 17 Mar 2025 20:49:22 +0200 Subject: [PATCH 11/24] power: regulator: add regulator support for CPCAP PMIC The driver provides regulator set/get voltage and enable/disable functions for CPCAP PMIC. Signed-off-by: Svyatoslav Ryhel --- drivers/power/pmic/cpcap.c | 35 +++ drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/cpcap_regulator.c | 275 ++++++++++++++++++++++ include/power/cpcap.h | 135 +++++++++++ 5 files changed, 455 insertions(+) create mode 100644 drivers/power/regulator/cpcap_regulator.c diff --git a/drivers/power/pmic/cpcap.c b/drivers/power/pmic/cpcap.c index 4923255f0a7..f2076afff43 100644 --- a/drivers/power/pmic/cpcap.c +++ b/drivers/power/pmic/cpcap.c @@ -12,6 +12,12 @@ #include #include +static const struct pmic_child_info pmic_children_info[] = { + { .prefix = "sw", .driver = CPCAP_SW_DRIVER }, + { .prefix = "v", .driver = CPCAP_LDO_DRIVER }, + { }, +}; + static int cpcap_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { u8 buf[4]; @@ -47,6 +53,34 @@ static int cpcap_read(struct udevice *dev, uint reg, uint8_t *buff, int len) return ret; } +static int cpcap_bind(struct udevice *dev) +{ + ofnode regulators_node; + int children; + + /* Regulator device node of PMIC */ + regulators_node = dev_read_subnode(dev, "regulator"); + if (!ofnode_valid(regulators_node)) { + log_err("%s regulator subnode not found!\n", dev->name); + return -ENXIO; + } + + /* Actual regulators container */ + regulators_node = ofnode_find_subnode(regulators_node, "regulators"); + if (!ofnode_valid(regulators_node)) { + log_err("%s regulators subnode not found!\n", dev->name); + return -ENXIO; + } + + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name); + + children = pmic_bind_children(dev, regulators_node, pmic_children_info); + if (!children) + log_err("%s - no child found\n", dev->name); + + return dm_scan_fdt_dev(dev); +} + static int cpcap_probe(struct udevice *dev) { struct spi_slave *slave = dev_get_parent_priv(dev); @@ -85,6 +119,7 @@ U_BOOT_DRIVER(pmic_cpcap) = { .name = "cpcap_pmic", .id = UCLASS_PMIC, .of_match = cpcap_ids, + .bind = cpcap_bind, .probe = cpcap_probe, .ops = &cpcap_ops, }; diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index bab68317cfa..bec2d2d7d49 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -493,3 +493,12 @@ config REGULATOR_RZG2L_USBPHY Enable this option to support controlling the VBUS supply in the USB PHY peripheral of the Renesas RZ/G2L SoC. This option is required in order to use the USB OTG port. + +config DM_REGULATOR_CPCAP + bool "Enable driver for CPCAP PMIC regulators" + depends on DM_REGULATOR && DM_PMIC_CPCAP + ---help--- + Enable implementation of driver-model regulator uclass features for + REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching + (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP + PMIC and implements get/set api for voltage and state. diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index cb6d5b29986..99affa235f3 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -44,3 +44,4 @@ obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_ANATOP) += anatop_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o +obj-$(CONFIG_$(PHASE_)DM_REGULATOR_CPCAP) += cpcap_regulator.o diff --git a/drivers/power/regulator/cpcap_regulator.c b/drivers/power/regulator/cpcap_regulator.c new file mode 100644 index 00000000000..04cd6651374 --- /dev/null +++ b/drivers/power/regulator/cpcap_regulator.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2025 Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include +#include + +/* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */ +#define CPCAP_BIT_VSDIO_SEL BIT(15) +#define CPCAP_BIT_VDIG_SEL BIT(14) +#define CPCAP_BIT_VCAM_SEL BIT(13) +#define CPCAP_BIT_SW6_SEL BIT(12) +#define CPCAP_BIT_SW5_SEL BIT(11) +#define CPCAP_BIT_SW4_SEL BIT(10) +#define CPCAP_BIT_SW3_SEL BIT(9) +#define CPCAP_BIT_SW2_SEL BIT(8) +#define CPCAP_BIT_SW1_SEL BIT(7) + +/* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */ +#define CPCAP_BIT_VUSBINT2_SEL BIT(15) +#define CPCAP_BIT_VUSBINT1_SEL BIT(14) +#define CPCAP_BIT_VVIB_SEL BIT(13) +#define CPCAP_BIT_VWLAN1_SEL BIT(12) +#define CPCAP_BIT_VRF1_SEL BIT(11) +#define CPCAP_BIT_VHVIO_SEL BIT(10) +#define CPCAP_BIT_VDAC_SEL BIT(9) +#define CPCAP_BIT_VUSB_SEL BIT(8) +#define CPCAP_BIT_VSIM_SEL BIT(7) +#define CPCAP_BIT_VRFREF_SEL BIT(6) +#define CPCAP_BIT_VPLL_SEL BIT(5) +#define CPCAP_BIT_VFUSE_SEL BIT(4) +#define CPCAP_BIT_VCSI_SEL BIT(3) +#define CPCAP_BIT_SPARE_14_2 BIT(2) +#define CPCAP_BIT_VWLAN2_SEL BIT(1) +#define CPCAP_BIT_VRF2_SEL BIT(0) +#define CPCAP_BIT_NONE 0 + +/* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */ +#define CPCAP_BIT_VAUDIO_SEL BIT(0) + +/* + * Off mode configuration bit. Used currently only by SW5 on omap4. There's + * the following comment in Motorola Linux kernel tree for it: + * + * When set in the regulator mode, the regulator assignment will be changed + * to secondary when the regulator is disabled. The mode will be set back to + * primary when the regulator is turned on. + */ +#define CPCAP_REG_OFF_MODE_SEC BIT(15) + +#define CPCAP_REG(_reg, _assignment_reg, _assignment_mask, _mode_mask, \ + _volt_mask, _volt_shft, _mode_val, _off_mode_val, _val_tbl, \ + _mode_cntr, _volt_trans_time, _turn_on_time, _bit_offset) { \ + .reg = CPCAP_REG_##_reg, \ + .assignment_reg = CPCAP_REG_##_assignment_reg, \ + .assignment_mask = CPCAP_BIT_##_assignment_mask, \ + .mode_mask = _mode_mask, \ + .volt_mask = _volt_mask, \ + .volt_shft = _volt_shft, \ + .mode_val = _mode_val, \ + .off_mode_val = _off_mode_val, \ + .val_tbl_sz = ARRAY_SIZE(_val_tbl), \ + .val_tbl = _val_tbl, \ + .mode_cntr = _mode_cntr, \ + .volt_trans_time = _volt_trans_time, \ + .turn_on_time = _turn_on_time, \ + .bit_offset_from_cpcap_lowest_voltage = _bit_offset, \ +} + +static const struct cpcap_regulator_data tegra20_regulators[CPCAP_REGULATORS_COUNT] = { + /* BUCK */ + [CPCAP_SW1] = CPCAP_REG(S1C1, ASSIGN2, SW1_SEL, 0x6f00, 0x007f, + 0, 0x6800, 0, sw1_val_tbl, 0, 0, 1500, 0x0c), + [CPCAP_SW2] = CPCAP_REG(S2C1, ASSIGN2, SW2_SEL, 0x6f00, 0x007f, + 0, 0x4804, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + [CPCAP_SW3] = CPCAP_REG(S3C, ASSIGN2, SW3_SEL, 0x0578, 0x0003, + 0, 0x043c, 0, sw3_val_tbl, 0, 0, 0, 0), + [CPCAP_SW4] = CPCAP_REG(S4C1, ASSIGN2, SW4_SEL, 0x6f00, 0x007f, + 0, 0x4909, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + [CPCAP_SW5] = CPCAP_REG(S5C, ASSIGN2, SW5_SEL, 0x0028, 0x0000, + 0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500, 0), + [CPCAP_SW6] = CPCAP_REG(S6C, ASSIGN2, SW6_SEL, 0x0000, 0x0000, + 0, 0, 0, unknown_val_tbl, 0, 0, 0, 0), + /* LDO */ + [CPCAP_VCAM] = CPCAP_REG(VCAMC, ASSIGN2, VCAM_SEL, 0x0087, 0x0030, + 4, 0x7, 0, vcam_val_tbl, 0, 420, 1000, 0), + [CPCAP_VCSI] = CPCAP_REG(VCSIC, ASSIGN3, VCSI_SEL, 0x0047, 0x0010, + 4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000, 0), + [CPCAP_VDAC] = CPCAP_REG(VDACC, ASSIGN3, VDAC_SEL, 0x0087, 0x0030, + 4, 0x0, 0, vdac_val_tbl, 0, 420, 1000, 0), + [CPCAP_VDIG] = CPCAP_REG(VDIGC, ASSIGN2, VDIG_SEL, 0x0087, 0x0030, + 4, 0x0, 0, vdig_val_tbl, 0, 420, 1000, 0), + [CPCAP_VFUSE] = CPCAP_REG(VFUSEC, ASSIGN3, VFUSE_SEL, 0x00a0, 0x000f, + 0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000, 0), + [CPCAP_VHVIO] = CPCAP_REG(VHVIOC, ASSIGN3, VHVIO_SEL, 0x0017, 0x0000, + 0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000, 0), + [CPCAP_VSDIO] = CPCAP_REG(VSDIOC, ASSIGN2, VSDIO_SEL, 0x0087, 0x0038, + 3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000, 0), + [CPCAP_VPLL] = CPCAP_REG(VPLLC, ASSIGN3, VPLL_SEL, 0x0047, 0x0018, + 3, 0x1, 0, vpll_val_tbl, 0, 420, 100, 0), + [CPCAP_VRF1] = CPCAP_REG(VRF1C, ASSIGN3, VRF1_SEL, 0x00ac, 0x0002, + 1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000, 0), + [CPCAP_VRF2] = CPCAP_REG(VRF2C, ASSIGN3, VRF2_SEL, 0x0023, 0x0008, + 3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000, 0), + [CPCAP_VRFREF] = CPCAP_REG(VRFREFC, ASSIGN3, VRFREF_SEL, 0x0023, 0x0008, + 3, 0x0, 0, vrfref_val_tbl, 0, 420, 100, 0), + [CPCAP_VWLAN1] = CPCAP_REG(VWLAN1C, ASSIGN3, VWLAN1_SEL, 0x0047, 0x0010, + 4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000, 0), + [CPCAP_VWLAN2] = CPCAP_REG(VWLAN2C, ASSIGN3, VWLAN2_SEL, 0x020c, 0x00c0, + 6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000, 0), + [CPCAP_VSIM] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x0023, 0x0008, + 3, 0x0, 0, vsim_val_tbl, 0, 420, 1000, 0), + [CPCAP_VSIMCARD] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x1e80, 0x0008, + 3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000, 0), + [CPCAP_VVIB] = CPCAP_REG(VVIBC, ASSIGN3, VVIB_SEL, 0x0001, 0x000c, + 2, 0x1, 0, vvib_val_tbl, 0, 500, 500, 0), + [CPCAP_VUSB] = CPCAP_REG(VUSBC, ASSIGN3, VUSB_SEL, 0x011c, 0x0040, + 6, 0xc, 0, vusb_val_tbl, 0, 0, 1000, 0), + [CPCAP_VAUDIO] = CPCAP_REG(VAUDIOC, ASSIGN4, VAUDIO_SEL, 0x0016, 0x0001, + 0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000, 0), +}; + +static int cpcap_regulator_get_value(struct udevice *dev) +{ + const struct cpcap_regulator_data *regulator = + &tegra20_regulators[dev->driver_data]; + int value, volt_shift = regulator->volt_shft; + + value = pmic_reg_read(dev->parent, regulator->reg); + if (value < 0) + return value; + + if (!(value & regulator->mode_mask)) + return 0; + + value &= regulator->volt_mask; + value -= regulator->bit_offset_from_cpcap_lowest_voltage; + + return regulator->val_tbl[value >> volt_shift]; +} + +static int cpcap_regulator_set_value(struct udevice *dev, int uV) +{ + const struct cpcap_regulator_data *regulator = + &tegra20_regulators[dev->driver_data]; + int value, ret, volt_shift = regulator->volt_shft; + + if (dev->driver_data == CPCAP_VRF1) { + if (uV > 2500000) + value = 0; + else + value = regulator->volt_mask; + } else { + for (value = 0; value < regulator->val_tbl_sz; value++) + if (regulator->val_tbl[value] >= uV) + break; + + if (value >= regulator->val_tbl_sz) + value = regulator->val_tbl_sz; + + value <<= volt_shift; + value += regulator->bit_offset_from_cpcap_lowest_voltage; + } + + ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->volt_mask, + value); + if (ret) + return ret; + + if (regulator->volt_trans_time) + udelay(regulator->volt_trans_time); + + return 0; +} + +static int cpcap_regulator_get_enable(struct udevice *dev) +{ + const struct cpcap_regulator_data *regulator = + &tegra20_regulators[dev->driver_data]; + int value; + + value = pmic_reg_read(dev->parent, regulator->reg); + if (value < 0) + return value; + + return (value & regulator->mode_mask) ? 1 : 0; +} + +static int cpcap_regulator_set_enable(struct udevice *dev, bool enable) +{ + const struct cpcap_regulator_data *regulator = + &tegra20_regulators[dev->driver_data]; + int ret; + + if (enable) { + ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->mode_mask, + regulator->mode_val); + if (ret) + return ret; + } + + if (regulator->mode_val & CPCAP_REG_OFF_MODE_SEC) { + ret = pmic_clrsetbits(dev->parent, regulator->assignment_reg, + regulator->assignment_mask, + enable ? 0 : regulator->assignment_mask); + if (ret) + return ret; + } + + if (!enable) { + ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->mode_mask, + regulator->off_mode_val); + if (ret) + return ret; + } + + if (regulator->turn_on_time) + udelay(regulator->turn_on_time); + + return 0; +} + +static int cpcap_regulator_probe(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); + int id; + + for (id = 0; id < CPCAP_REGULATORS_COUNT; id++) + if (cpcap_regulator_to_name[id]) + if (!strcmp(dev->name, cpcap_regulator_to_name[id])) + break; + + switch (id) { + case CPCAP_SW1 ... CPCAP_SW6: + uc_pdata->type = REGULATOR_TYPE_BUCK; + break; + + case CPCAP_VCAM ... CPCAP_VAUDIO: + uc_pdata->type = REGULATOR_TYPE_LDO; + break; + + default: + log_err("CPCAP: Invalid regulator ID\n"); + return -ENODEV; + } + + dev->driver_data = id; + return 0; +} + +static const struct dm_regulator_ops cpcap_regulator_ops = { + .get_value = cpcap_regulator_get_value, + .set_value = cpcap_regulator_set_value, + .get_enable = cpcap_regulator_get_enable, + .set_enable = cpcap_regulator_set_enable, +}; + +U_BOOT_DRIVER(cpcap_sw) = { + .name = CPCAP_SW_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &cpcap_regulator_ops, + .probe = cpcap_regulator_probe, +}; + +U_BOOT_DRIVER(cpcap_ldo) = { + .name = CPCAP_LDO_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &cpcap_regulator_ops, + .probe = cpcap_regulator_probe, +}; diff --git a/include/power/cpcap.h b/include/power/cpcap.h index ecc0ece6518..bb0e28cec55 100644 --- a/include/power/cpcap.h +++ b/include/power/cpcap.h @@ -235,4 +235,139 @@ #define CPCAP_REG_ST_TEST2 0x7d18 /* ST Test2 */ +/* Drivers name */ +#define CPCAP_LDO_DRIVER "cpcap_ldo" +#define CPCAP_SW_DRIVER "cpcap_sw" + +enum cpcap_regulator_id { + CPCAP_SW1, + CPCAP_SW2, + CPCAP_SW3, + CPCAP_SW4, + CPCAP_SW5, + CPCAP_SW6, + CPCAP_VCAM, + CPCAP_VCSI, + CPCAP_VDAC, + CPCAP_VDIG, + CPCAP_VFUSE, + CPCAP_VHVIO, + CPCAP_VSDIO, + CPCAP_VPLL, + CPCAP_VRF1, + CPCAP_VRF2, + CPCAP_VRFREF, + CPCAP_VWLAN1, + CPCAP_VWLAN2, + CPCAP_VSIM, + CPCAP_VSIMCARD, + CPCAP_VVIB, + CPCAP_VUSB, + CPCAP_VAUDIO, + CPCAP_REGULATORS_COUNT, +}; + +static const char * const cpcap_regulator_to_name[] = { + /* BUCK */ + [CPCAP_SW1] = "sw1", + [CPCAP_SW2] = "sw2", + [CPCAP_SW3] = "sw3", + [CPCAP_SW4] = "sw4", + [CPCAP_SW5] = "sw5", + [CPCAP_SW6] = "sw6", + /* LDO */ + [CPCAP_VCAM] = "vcam", + [CPCAP_VCSI] = "vcsi", + [CPCAP_VDAC] = "vdac", + [CPCAP_VDIG] = "vdig", + [CPCAP_VFUSE] = "vfuse", + [CPCAP_VHVIO] = "vhvio", + [CPCAP_VSDIO] = "vsdio", + [CPCAP_VPLL] = "vpll", + [CPCAP_VRF1] = "vrf1", + [CPCAP_VRF2] = "vrf2", + [CPCAP_VRFREF] = "vrfref", + [CPCAP_VWLAN1] = "vwlan1", + [CPCAP_VWLAN2] = "vwlan2", + [CPCAP_VSIM] = "vsim", + [CPCAP_VSIMCARD] = "vsimcard", + [CPCAP_VVIB] = "vvib", + [CPCAP_VUSB] = "vusb", + [CPCAP_VAUDIO] = "vaudio", +}; + +static const u32 unknown_val_tbl[] = { 0, }; +static const u32 sw1_val_tbl[] = { 750000, 762500, 775000, 787500, 800000, + 812500, 825000, 837500, 850000, 862500, + 875000, 887500, 900000, 912500, 925000, + 937500, 950000, 962500, 975000, 987500, + 1000000, 1012500, 1025000, 1037500, + 1050000, 1062500, 1075000, 1087500, + 1100000, 1112500, 1125000, 1137500, + 1150000, 1162500, 1175000, 1187500, + 1200000, 1212500, 1225000, 1237500, + 1250000, 1262500, 1275000, 1287500, + 1300000, 1312500, 1325000, 1337500, + 1350000, 1362500, 1375000, 1387500, + 1400000, 1412500, 1425000, 1437500, + 1450000, 1462500, 1475000 }; +static const u32 sw2_sw4_val_tbl[] = { 900000, 912500, 925000, 937500, 950000, + 962500, 975000, 987500, 1000000, 1012500, + 1025000, 1037500, 1050000, 1062500, + 1075000, 1087500, 1100000, 1112500, + 1125000, 1137500, 1150000, 1162500, + 1175000, 1187500, 1200000, 1212500, + 1225000, 1237500, 1250000, 1262500, + 1275000, 1287500, 1300000, 1312500, + 1325000, 1337500, 1350000, 1362500, + 1375000, 1387500, 1400000, 1412500, + 1425000, 1437500, 1450000, 1462500, + 1475000 }; +static const u32 sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000 }; +static const u32 sw5_val_tbl[] = { 0, 5050000 }; +static const u32 vcam_val_tbl[] = { 2600000, 2700000, 2800000, 2900000 }; +static const u32 vcsi_val_tbl[] = { 1200000, 1800000 }; +static const u32 vdac_val_tbl[] = { 1200000, 1500000, 1800000, 2500000 }; +static const u32 vdig_val_tbl[] = { 1200000, 1350000, 1500000, 1875000 }; +static const u32 vfuse_val_tbl[] = { 1500000, 1600000, 1700000, 1800000, 1900000, + 2000000, 2100000, 2200000, 2300000, 2400000, + 2500000, 2600000, 2700000, 3150000 }; +static const u32 vhvio_val_tbl[] = { 2775000 }; +static const u32 vsdio_val_tbl[] = { 1500000, 1600000, 1800000, 2600000, + 2700000, 2800000, 2900000, 3000000 }; +static const u32 vpll_val_tbl[] = { 1200000, 1300000, 1400000, 1800000 }; +static const u32 vrf1_val_tbl[] = { 2775000, 2500000 }; /* Yes, this is correct */ +static const u32 vrf2_val_tbl[] = { 0, 2775000 }; +static const u32 vrfref_val_tbl[] = { 2500000, 2775000 }; +static const u32 vwlan1_val_tbl[] = { 1800000, 1900000 }; +static const u32 vwlan2_val_tbl[] = { 2775000, 3000000, 3300000, 3300000 }; +static const u32 vsim_val_tbl[] = { 1800000, 2900000 }; +static const u32 vsimcard_val_tbl[] = { 1800000, 2900000 }; +static const u32 vvib_val_tbl[] = { 1300000, 1800000, 2000000, 3000000 }; +static const u32 vusb_val_tbl[] = { 0, 3300000 }; +static const u32 vaudio_val_tbl[] = { 0, 2775000 }; + +struct cpcap_regulator_data { + u16 reg; + u16 assignment_reg; + u16 assignment_mask; + u16 mode_mask; + u16 volt_mask; + u8 volt_shft; + u16 mode_val; + u16 off_mode_val; + u32 val_tbl_sz; + const u32 *val_tbl; + u32 mode_cntr; + u32 volt_trans_time; /* in micro seconds */ + u32 turn_on_time; /* in micro seconds */ + + /* + * Bit difference between lowest value in val_tbl and start of voltage + * table setting in cpcap. Use this for switchers that have many too + * many voltages to list in val_tbl. + */ + u32 bit_offset_from_cpcap_lowest_voltage; +}; + #endif /* _CPCAP_H_ */ From a9bf7e70c587b67bdb27ffd739c3553d1e08d573 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 25 Mar 2025 20:23:07 +0200 Subject: [PATCH 12/24] input: add support for CPCAP power button CPCAP has a dedicated interrupt for power button. Implement this to have more input control over the devices. Signed-off-by: Svyatoslav Ryhel --- drivers/input/Kconfig | 6 ++ drivers/input/Makefile | 1 + drivers/input/cpcap_pwrbutton.c | 134 ++++++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 drivers/input/cpcap_pwrbutton.c diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index c2b365af11d..c09f0ae795e 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -55,6 +55,12 @@ config BUTTON_KEYBOARD dt node to define button-event mapping. For example, an arrows and enter may be implemented to navigate boot menu. +config CPCAP_POWER_BUTTON + bool "Enable power button of CPCAP PMIC support" + depends on DM_KEYBOARD && DM_PMIC_CPCAP + help + Enable support for a dedicated power button of the CPCAP PMIC. + config CROS_EC_KEYB bool "Enable Chrome OS EC keyboard support" depends on INPUT diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 8d4107b8848..1303fcdb0b7 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_$(PHASE_)CROS_EC_KEYB) += cros_ec_keyb.o obj-$(CONFIG_$(PHASE_)OF_CONTROL) += key_matrix.o obj-$(CONFIG_$(PHASE_)DM_KEYBOARD) += input.o keyboard-uclass.o obj-$(CONFIG_BUTTON_KEYBOARD) += button_kbd.o +obj-$(CONFIG_CPCAP_POWER_BUTTON) += cpcap_pwrbutton.o ifndef CONFIG_XPL_BUILD diff --git a/drivers/input/cpcap_pwrbutton.c b/drivers/input/cpcap_pwrbutton.c new file mode 100644 index 00000000000..c8ad39d33ca --- /dev/null +++ b/drivers/input/cpcap_pwrbutton.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright(C) 2025 Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const unsigned int cpcpap_to_reg[] = { + CPCAP_REG_INT1, + CPCAP_REG_INT2, + CPCAP_REG_INT3, + CPCAP_REG_INT4, +}; + +/** + * struct cpcap_pwrbutton_priv + * + * @bank: id of interrupt bank co-responding to an IRQ register + * @id: id of interrupt pin co-responding to the bit in IRQ register + * @keycode: linux key code + * @old_state: holder of last button state + * @skip: holder of keycode skip state. This is required since both pressing + * and releasing generate same event and cause key send duplication. + */ +struct cpcap_pwrbutton_priv { + u32 bank; + u32 id; + + u32 keycode; + + bool old_state; + bool skip; +}; + +static int cpcap_pwrbutton_read_keys(struct input_config *input) +{ + struct udevice *dev = input->dev; + struct cpcap_pwrbutton_priv *priv = dev_get_priv(dev); + u32 value, state_changed; + bool state; + + value = pmic_reg_read(dev->parent, cpcpap_to_reg[priv->bank]) & + BIT(priv->id); + + /* Interrupt bit is cleared by writing it to interrupt reg */ + pmic_reg_write(dev->parent, cpcpap_to_reg[priv->bank], BIT(priv->id)); + + state = value >> priv->id; + state_changed = state != priv->old_state; + + if (state_changed && !priv->skip) { + priv->old_state = state; + input_add_keycode(input, priv->keycode, state); + } + + if (state) + priv->skip = !priv->skip; + + return 0; +} + +static int cpcap_pwrbutton_of_to_plat(struct udevice *dev) +{ + struct cpcap_pwrbutton_priv *priv = dev_get_priv(dev); + ofnode irq_parent; + u32 irq_desc; + int ret; + + /* Check interrupt parent, driver supports only CPCAP as parent */ + irq_parent = ofnode_parse_phandle(dev_ofnode(dev), "interrupt-parent", 0); + if (!ofnode_device_is_compatible(irq_parent, "motorola,cpcap")) + return -EINVAL; + + ret = dev_read_u32(dev, "interrupts", &irq_desc); + if (ret) + return ret; + + /* IRQ registers are 16 bit wide */ + priv->bank = irq_desc / 16; + priv->id = irq_desc % 16; + + ret = dev_read_u32(dev, "linux,code", &priv->keycode); + if (ret) + return ret; + + priv->old_state = false; + priv->skip = false; + return 0; +} + +static int cpcap_pwrbutton_probe(struct udevice *dev) +{ + struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev); + struct stdio_dev *sdev = &uc_priv->sdev; + struct input_config *input = &uc_priv->input; + int ret; + + input_init(input, false); + input_add_tables(input, false); + + /* Register the device */ + input->dev = dev; + input->read_keys = cpcap_pwrbutton_read_keys; + strcpy(sdev->name, "cpcap-pwrbutton"); + ret = input_stdio_register(sdev); + if (ret) { + log_debug("%s: input_stdio_register() failed\n", __func__); + return ret; + } + + return 0; +} + +static const struct udevice_id cpcap_pwrbutton_ids[] = { + { .compatible = "motorola,cpcap-pwrbutton" }, + { } +}; + +U_BOOT_DRIVER(cpcap_pwrbutton) = { + .name = "cpcap_pwrbutton", + .id = UCLASS_KEYBOARD, + .of_match = cpcap_pwrbutton_ids, + .of_to_plat = cpcap_pwrbutton_of_to_plat, + .probe = cpcap_pwrbutton_probe, + .priv_auto = sizeof(struct cpcap_pwrbutton_priv), +}; From 01793b3ddba6ad31d24ecacb9ff00c807fd00acc Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 19 Mar 2025 10:15:29 +0200 Subject: [PATCH 13/24] video: panel: add Motorola Atrix 4G and Droid X2 panel Add support for the LCD panel module used in Motorola Atrix 4G or Droid X2. Exact panel vendor and model are unknown. The panel has a 540x960 (qHD) resolution and uses 24 bit RGB per pixel. Signed-off-by: Svyatoslav Ryhel --- drivers/video/Kconfig | 10 ++ drivers/video/Makefile | 1 + drivers/video/mot-panel.c | 308 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 319 insertions(+) create mode 100644 drivers/video/mot-panel.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index d343dfb061b..6c323be3e32 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -529,6 +529,16 @@ config VIDEO_LCD_HIMAX_HX8394 Say Y here if you want to enable support for Himax HX8394 dsi 4dl panel. +config VIDEO_LCD_MOT + tristate "Atrix 4G and Droid X2 540x960 DSI video mode panel" + depends on PANEL && BACKLIGHT + select VIDEO_MIPI_DSI + help + Say Y here if you want to enable support for the LCD panel module for + Motorola Atrix 4G or Droid X2. Exact panel vendor and model are + unknown. The panel has a 540x960 resolution and uses 24 bit RGB per + pixel. + config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" select VIDEO_MIPI_DSI diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 74df5711d18..2145afa2686 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -59,6 +59,7 @@ obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o +obj-$(CONFIG_VIDEO_LCD_MOT) += mot-panel.o obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o obj-$(CONFIG_VIDEO_LCD_RENESAS_R61307) += renesas-r61307.o diff --git a/drivers/video/mot-panel.c b/drivers/video/mot-panel.c new file mode 100644 index 00000000000..a9114957867 --- /dev/null +++ b/drivers/video/mot-panel.c @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Motorola ATRIX 4G and DROID X2 DSI panel driver + * Exact manufacturer and model unknown + * + * Copyright (c) 2025 Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mot_panel_priv { + struct udevice *vdd; + struct udevice *vddio; + + struct udevice *backlight; + + struct gpio_desc reset_gpio; +}; + +#define dsi_generic_write_seq(dsi, cmd, seq...) do { \ + static const u8 b[] = { cmd, seq }; \ + int ret; \ + ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b)); \ + if (ret < 0) \ + return ret; \ + } while (0) + +static struct display_timing default_timing = { + .pixelclock.typ = 38250000, + .hactive.typ = 540, + .hfront_porch.typ = 32, + .hback_porch.typ = 32, + .hsync_len.typ = 16, + .vactive.typ = 960, + .vfront_porch.typ = 12, + .vback_porch.typ = 12, + .vsync_len.typ = 8, +}; + +static int mot_es2(struct mipi_dsi_device *dsi) +{ + int ret; + + dsi_generic_write_seq(dsi, 0x55, 0x01); + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + log_debug("%s: failed to exit sleep mode: %d\n", __func__, ret); + return ret; + } + mdelay(120); + + dsi_generic_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49, + 0x74, 0x29, 0x12, 0x15, 0x2f, 0x2f, 0x04); + dsi_generic_write_seq(dsi, 0xf8, 0x4b, 0x04, 0x10, 0x1a, 0x2c, 0x2c, + 0x2c, 0x2c, 0x14, 0x12); + + dsi_generic_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x00, 0x80, 0xc7, 0x00); + dsi_generic_write_seq(dsi, 0xb7, 0x66, 0xf6, 0x46, 0x9f, 0x90, 0x99, + 0xff, 0x80, 0x6d, 0x01); + + /* Gamma R */ + dsi_generic_write_seq(dsi, 0xf9, 0x04); + dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c, + 0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f); + dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x30, 0x12, 0x0e, 0x0c, + 0x22, 0x27, 0x31, 0x2e, 0x07, 0x0f); + + /* Gamma G */ + dsi_generic_write_seq(dsi, 0xf9, 0x02); + dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11, + 0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f); + dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x37, 0x15, 0x15, 0x11, + 0x1f, 0x25, 0x2d, 0x2a, 0x05, 0x0f); + + /* Gamma B */ + dsi_generic_write_seq(dsi, 0xf9, 0x01); + dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15, + 0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b); + dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x3f, 0x16, 0x1f, 0x15, + 0x1f, 0x25, 0x2d, 0x2b, 0x06, 0x0b); + + /* Gamma W */ + dsi_generic_write_seq(dsi, 0xf9, 0x20); + dsi_generic_write_seq(dsi, 0xfa, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11, + 0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08); + dsi_generic_write_seq(dsi, 0xfb, 0x00, 0x2f, 0x34, 0x15, 0x1a, 0x11, + 0x1f, 0x23, 0x2d, 0x29, 0x02, 0x08); + + dsi_generic_write_seq(dsi, 0x53, 0x2c); + dsi_generic_write_seq(dsi, 0x35, 0x00); + + return 0; +} + +static int __maybe_unused mot_es4(struct mipi_dsi_device *dsi) +{ + int ret; + + dsi_generic_write_seq(dsi, 0xd2, 0x04, 0x53); + dsi_generic_write_seq(dsi, 0xd2, 0x05, 0x53); + dsi_generic_write_seq(dsi, 0x55, 0x01); + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + log_debug("%s: failed to exit sleep mode: %d\n", __func__, ret); + return ret; + } + mdelay(120); + + dsi_generic_write_seq(dsi, 0xb5, 0x03, 0x7f, 0x0a, 0x80, 0xff, 0x00); + dsi_generic_write_seq(dsi, 0xb7, 0x7a, 0xf7, 0x4d, 0x91, 0x90, 0xb3, + 0xff, 0x80, 0x6d, 0x01); + dsi_generic_write_seq(dsi, 0xf4, 0x00, 0xbb, 0x46, 0x53, 0x0c, 0x49, + 0x74, 0x29, 0x12, 0x15, 0x37, 0x37, 0x04); + dsi_generic_write_seq(dsi, 0xf8, 0x0a, 0x04, 0x10, 0x2a, 0x35, 0x35, + 0x35, 0x35, 0x21, 0x1a); + + /* Gamma R */ + dsi_generic_write_seq(dsi, 0xf9, 0x04); + dsi_generic_write_seq(dsi, 0xfa, 0x08, 0x1c, 0x1b, 0x0f, 0x0f, 0x0a, + 0x1e, 0x22, 0x27, 0x26, 0x07, 0x0d); + dsi_generic_write_seq(dsi, 0xfb, 0x08, 0x3c, 0x27, 0x0f, 0x0f, 0x0a, + 0x1e, 0x26, 0x31, 0x2f, 0x07, 0x0b); + + /* Gamma G */ + dsi_generic_write_seq(dsi, 0xf9, 0x02); + dsi_generic_write_seq(dsi, 0xfa, 0x30, 0x14, 0x0f, 0x00, 0x06, 0x02, + 0x1e, 0x22, 0x27, 0x27, 0x08, 0x10); + dsi_generic_write_seq(dsi, 0xfb, 0x30, 0x35, 0x0f, 0x00, 0x0a, 0x02, + 0x1c, 0x23, 0x31, 0x2f, 0x08, 0x0e); + + /* Gamma B */ + dsi_generic_write_seq(dsi, 0xf9, 0x01); + dsi_generic_write_seq(dsi, 0xfa, 0x12, 0x1b, 0x26, 0x0e, 0x12, 0x0b, + 0x1e, 0x22, 0x27, 0x27, 0x06, 0x0c); + dsi_generic_write_seq(dsi, 0xfb, 0x12, 0x3b, 0x2c, 0x12, 0x12, 0x0e, + 0x1e, 0x26, 0x31, 0x2f, 0x06, 0x0d); + + /* Gamma W */ + dsi_generic_write_seq(dsi, 0xf9, 0x20); + dsi_generic_write_seq(dsi, 0xfa, 0x37, 0x1b, 0x09, 0x01, 0x06, 0x04, + 0x19, 0x19, 0x22, 0x24, 0x04, 0x15); + dsi_generic_write_seq(dsi, 0xfb, 0x37, 0x3b, 0x17, 0x01, 0x0a, 0x04, + 0x19, 0x1d, 0x2c, 0x2c, 0x04, 0x13); + + dsi_generic_write_seq(dsi, 0x53, 0x2c); + dsi_generic_write_seq(dsi, 0x35, 0x00); + dsi_generic_write_seq(dsi, 0xc3, 0x01, 0x4e); + + return 0; +} + +static int mot_panel_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *dsi = plat->device; + int ret; + + dsi_generic_write_seq(dsi, 0xf0, 0x5a, 0x5a); + dsi_generic_write_seq(dsi, 0xf1, 0x5a, 0x5a); + dsi_generic_write_seq(dsi, 0xd0, 0x8e); + + ret = mot_es2(dsi); + if (ret) + return ret; + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + log_debug("%s: failed to set display on: %d\n", __func__, ret); + return ret; + } + mdelay(20); + + return 0; +} + +static int mot_panel_set_backlight(struct udevice *dev, int percent) +{ + struct mot_panel_priv *priv = dev_get_priv(dev); + int ret; + + ret = backlight_enable(priv->backlight); + if (ret) + return ret; + + mdelay(5); + + return backlight_set_brightness(priv->backlight, percent); +} + +static int mot_panel_timings(struct udevice *dev, struct display_timing *timing) +{ + memcpy(timing, &default_timing, sizeof(*timing)); + return 0; +} + +static int mot_panel_of_to_plat(struct udevice *dev) +{ + struct mot_panel_priv *priv = dev_get_priv(dev); + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + log_debug("%s: cannot get backlight: ret = %d\n", __func__, ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vdd-supply", &priv->vdd); + if (ret) { + log_debug("%s: cannot get vdd-supply: ret = %d\n", __func__, ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vddio-supply", &priv->vddio); + if (ret) { + log_debug("%s: cannot get vddio-supply: ret = %d\n", __func__, ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpios", 0, + &priv->reset_gpio, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: could not decode reser-gpios (%d)\n", __func__, ret); + return ret; + } + + return 0; +} + +static int mot_panel_hw_init(struct udevice *dev) +{ + struct mot_panel_priv *priv = dev_get_priv(dev); + int ret; + + ret = regulator_set_enable_if_allowed(priv->vddio, 1); + if (ret) { + log_debug("%s: enabling vddio-supply failed (%d)\n", __func__, ret); + return ret; + } + + ret = regulator_set_enable_if_allowed(priv->vdd, 1); + if (ret) { + log_debug("%s: enabling vdd-supply failed (%d)\n", __func__, ret); + return ret; + } + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) { + log_debug("%s: error entering reset (%d)\n", __func__, ret); + return ret; + } + mdelay(50); + + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) { + log_debug("%s: error exiting reset (%d)\n", __func__, ret); + return ret; + } + mdelay(10); + + return 0; +} + +static int mot_panel_probe(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + + /* fill characteristics of DSI data link */ + plat->lanes = 2; + plat->format = MIPI_DSI_FMT_RGB888; + plat->mode_flags = MIPI_DSI_MODE_LPM; + + return mot_panel_hw_init(dev); +} + +static const struct panel_ops mot_panel_ops = { + .enable_backlight = mot_panel_enable_backlight, + .set_backlight = mot_panel_set_backlight, + .get_display_timing = mot_panel_timings, +}; + +static const struct udevice_id mot_panel_ids[] = { + { .compatible = "motorola,mot-panel" }, + { } +}; + +U_BOOT_DRIVER(mot_panel) = { + .name = "mot_panel", + .id = UCLASS_PANEL, + .of_match = mot_panel_ids, + .ops = &mot_panel_ops, + .of_to_plat = mot_panel_of_to_plat, + .probe = mot_panel_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct mot_panel_priv), +}; From 041cb0b23acfaff8978ee6e4204147e9ae9b7dd9 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Wed, 19 Mar 2025 13:51:58 +0200 Subject: [PATCH 14/24] video: backlight: add TI LM3532 led controller The LM3532 is a 500-kHz fixed frequency asynchronous boost converter which provides the power for 3 high-voltage, low-side current sinks. The device is programmable over an I2C-compatible interface and has independent current control for all three channels. Signed-off-by: Svyatoslav Ryhel --- drivers/video/Kconfig | 9 + drivers/video/Makefile | 1 + drivers/video/lm3532_backlight.c | 380 +++++++++++++++++++++++++++++++ 3 files changed, 390 insertions(+) create mode 100644 drivers/video/lm3532_backlight.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 6c323be3e32..73353944971 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -738,6 +738,15 @@ config ATMEL_HLCD help HLCDC supports video output to an attached LCD panel. +config BACKLIGHT_LM3532 + bool "Backlight Driver for LM3532" + depends on BACKLIGHT + select DM_I2C + help + Say Y to enable the backlight driver for National Semiconductor / TI + LM3532 Lighting Power chip. Only backlight functions is supported as + for now. Supported backlight level range is from 1 to 255. + config BACKLIGHT_LM3533 bool "Backlight Driver for LM3533" depends on BACKLIGHT diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 2145afa2686..fbdb058647a 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_$(PHASE_)BMP) += bmp.o endif +obj-$(CONFIG_BACKLIGHT_LM3532) += lm3532_backlight.o obj-$(CONFIG_BACKLIGHT_LM3533) += lm3533_backlight.o obj-$(CONFIG_BACKLIGHT_LP855x) += lp855x_backlight.o obj-${CONFIG_EXYNOS_FB} += exynos/ diff --git a/drivers/video/lm3532_backlight.c b/drivers/video/lm3532_backlight.c new file mode 100644 index 00000000000..81b3b910196 --- /dev/null +++ b/drivers/video/lm3532_backlight.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TI LM3532 LED driver + * + * Copyright (c) 2019 Texas Instruments Incorporated + * Copyright (c) 2025 Svyatoslav Ryhel + */ + +#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LM3532_BL_MODE_MANUAL 0x00 +#define LM3532_BL_MODE_ALS 0x01 + +#define LM3532_REG_OUTPUT_CFG 0x10 +#define LM3532_REG_STARTSHUT_RAMP 0x11 +#define LM3532_REG_RT_RAMP 0x12 +#define LM3532_REG_PWM_A_CFG 0x13 +#define LM3532_REG_PWM_B_CFG 0x14 +#define LM3532_REG_PWM_C_CFG 0x15 +#define LM3532_REG_ZONE_CFG_A 0x16 +#define LM3532_REG_CTRL_A_FS_CURR 0x17 +#define LM3532_REG_ZONE_CFG_B 0x18 +#define LM3532_REG_CTRL_B_FS_CURR 0x19 +#define LM3532_REG_ZONE_CFG_C 0x1a +#define LM3532_REG_CTRL_C_FS_CURR 0x1b +#define LM3532_REG_ENABLE 0x1d +#define LM3532_ALS_CONFIG 0x23 +#define LM3532_REG_ZN_0_HI 0x60 +#define LM3532_REG_ZN_0_LO 0x61 +#define LM3532_REG_ZN_1_HI 0x62 +#define LM3532_REG_ZN_1_LO 0x63 +#define LM3532_REG_ZN_2_HI 0x64 +#define LM3532_REG_ZN_2_LO 0x65 +#define LM3532_REG_ZN_3_HI 0x66 +#define LM3532_REG_ZN_3_LO 0x67 +#define LM3532_REG_ZONE_TRGT_A 0x70 +#define LM3532_REG_ZONE_TRGT_B 0x75 +#define LM3532_REG_ZONE_TRGT_C 0x7a +#define LM3532_REG_MAX 0x7e + +/* Control Enable */ +#define LM3532_CTRL_A_ENABLE BIT(0) +#define LM3532_CTRL_B_ENABLE BIT(1) +#define LM3532_CTRL_C_ENABLE BIT(2) + +/* PWM Zone Control */ +#define LM3532_PWM_ZONE_MASK 0x7c +#define LM3532_PWM_ZONE_0_EN BIT(2) +#define LM3532_PWM_ZONE_1_EN BIT(3) +#define LM3532_PWM_ZONE_2_EN BIT(4) +#define LM3532_PWM_ZONE_3_EN BIT(5) +#define LM3532_PWM_ZONE_4_EN BIT(6) + +/* Brightness Configuration */ +#define LM3532_I2C_CTRL BIT(0) +#define LM3532_ALS_CTRL 0 +#define LM3532_LINEAR_MAP BIT(1) +#define LM3532_ZONE_MASK (BIT(2) | BIT(3) | BIT(4)) +#define LM3532_ZONE_0 0 +#define LM3532_ZONE_1 BIT(2) +#define LM3532_ZONE_2 BIT(3) +#define LM3532_ZONE_3 (BIT(2) | BIT(3)) +#define LM3532_ZONE_4 BIT(4) + +#define LM3532_ENABLE_ALS BIT(3) +#define LM3532_ALS_SEL_SHIFT 6 + +/* Zone Boundary Register */ +#define LM3532_ALS_WINDOW_mV 2000 +#define LM3532_ALS_ZB_MAX 4 +#define LM3532_ALS_OFFSET_mV 2 + +#define LM3532_CONTROL_A 0 +#define LM3532_CONTROL_B 1 +#define LM3532_CONTROL_C 2 +#define LM3532_MAX_CONTROL_BANKS 3 +#define LM3532_MAX_LED_STRINGS 3 + +#define LM3532_OUTPUT_CFG_MASK 0x3 +#define LM3532_BRT_VAL_ADJUST 8 +#define LM3532_RAMP_DOWN_SHIFT 3 + +#define LM3532_NUM_RAMP_VALS 8 +#define LM3532_NUM_AVG_VALS 8 +#define LM3532_NUM_IMP_VALS 32 + +#define LM3532_FS_CURR_MIN 5000 +#define LM3532_FS_CURR_MAX 29800 +#define LM3532_FS_CURR_STEP 800 + +struct lm3532_bank_data { + int control_bank; + int mode; + int ctrl_brt_pointer; + int num_leds; + int full_scale_current; + u32 present:1; + u32 led_strings[LM3532_MAX_CONTROL_BANKS]; +}; + +struct lm3532_backlight_priv { + struct gpio_desc enable_gpio; + struct udevice *regulator; + + u32 runtime_ramp_up; + u32 runtime_ramp_down; + + struct lm3532_bank_data bank[LM3532_MAX_CONTROL_BANKS]; +}; + +/* This device does not like i2c md so use this instead */ +static void __maybe_unused dump_i2c(struct udevice *dev) +{ + int i, c; + + for (i = 0; i < 0x10; i++) { + printf("00%02x: %02x", i * 0x10, dm_i2c_reg_read(dev, i * 0x10)); + for (c = 1; c < 0xf; c++) + printf(" %02x", dm_i2c_reg_read(dev, i * 0x10 + c)); + printf(" %02x\n", dm_i2c_reg_read(dev, i * 0x10 + 0xf)); + } +} + +static int lm3532_backlight_enable(struct udevice *dev) +{ + struct lm3532_backlight_priv *priv = dev_get_priv(dev); + int ret, i; + + for (i = 0; i < LM3532_MAX_CONTROL_BANKS; i++) { + if (priv->bank[i].present) { + u32 ctrl_en_val = BIT(priv->bank[i].control_bank); + + ret = dm_i2c_reg_clrset(dev, LM3532_REG_ENABLE, + ctrl_en_val, ctrl_en_val); + if (ret) { + log_debug("%s: failed to set ctrl: %d\n", + __func__, ret); + return ret; + } + } + } + + regulator_set_enable_if_allowed(priv->regulator, 1); + + return 0; +} + +static int lm3532_backlight_set_brightness(struct udevice *dev, int percent) +{ + struct lm3532_backlight_priv *priv = dev_get_priv(dev); + struct lm3532_bank_data *bank; + int ret, i; + + for (i = 0; i < LM3532_MAX_CONTROL_BANKS; i++) { + if (priv->bank[i].present) { + bank = &priv->bank[i]; + u32 brightness_reg = LM3532_REG_ZONE_TRGT_A + + bank->control_bank * 5 + + (bank->ctrl_brt_pointer >> 2); + + ret = dm_i2c_reg_write(dev, brightness_reg, percent); + if (ret) { + log_debug("%s: failed to set brightness: %d\n", + __func__, ret); + return ret; + } + } + } + + return 0; +} + +static const int ramp_table[LM3532_NUM_RAMP_VALS] = { 8, 1024, 2048, 4096, 8192, + 16384, 32768, 65536 }; +static int lm3532_get_ramp_index(int ramp_time) +{ + int i; + + if (ramp_time <= ramp_table[0]) + return 0; + + if (ramp_time > ramp_table[LM3532_NUM_RAMP_VALS - 1]) + return LM3532_NUM_RAMP_VALS - 1; + + for (i = 1; i < LM3532_NUM_RAMP_VALS; i++) { + if (ramp_time == ramp_table[i]) + return i; + + /* Find an approximate index by looking up the table */ + if (ramp_time > ramp_table[i - 1] && + ramp_time < ramp_table[i]) { + if (ramp_time - ramp_table[i - 1] < ramp_table[i] - ramp_time) + return i - 1; + else + return i; + } + } + + return 0; +} + +static int lm3532_backlight_of_to_plat(struct udevice *dev) +{ + struct lm3532_backlight_priv *priv = dev_get_priv(dev); + u32 ramp_time, reg; + ofnode child; + int ret; + + ret = gpio_request_by_name(dev, "enable-gpios", 0, + &priv->enable_gpio, GPIOD_IS_OUT); + if (ret) { + log_debug("%s: could not decode enable-gpios (%d)\n", __func__, ret); + return ret; + } + + ret = device_get_supply_regulator(dev, "vin-supply", &priv->regulator); + if (ret) { + log_debug("%s: vin regulator not defined: %d\n", __func__, ret); + if (ret != -ENOENT) + return log_ret(ret); + } + + ramp_time = dev_read_u32_default(dev, "ramp-up-us", 0); + priv->runtime_ramp_up = lm3532_get_ramp_index(ramp_time); + + ramp_time = dev_read_u32_default(dev, "ramp-down-us", 0); + priv->runtime_ramp_down = lm3532_get_ramp_index(ramp_time); + + /* Backlight is one of children but has no dedicated driver */ + ofnode_for_each_subnode(child, dev_ofnode(dev)) { + ret = ofnode_read_u32(child, "reg", ®); + if (ret || reg > LM3532_CONTROL_C) { + log_debug("%s: control bank invalid %d\n", __func__, reg); + continue; + } + + struct lm3532_bank_data *bank = &priv->bank[reg]; + + bank->control_bank = reg; + bank->present = 1; + bank->mode = ofnode_read_u32_default(child, "ti,led-mode", + LM3532_BL_MODE_MANUAL); + bank->mode = LM3532_BL_MODE_ALS ? LM3532_ALS_CTRL : LM3532_I2C_CTRL; + + if (ofnode_read_bool(child, "ti,linear-mapping-mode")) + bank->mode |= LM3532_LINEAR_MAP; + + bank->num_leds = ofnode_read_size(child, "led-sources"); + bank->num_leds /= sizeof(u32); + if (bank->num_leds > LM3532_MAX_LED_STRINGS) { + log_debug("%s: too many LED string defined %d\n", + __func__, bank->num_leds); + continue; + } + + ret = ofnode_read_u32_array(child, "led-sources", + bank->led_strings, + bank->num_leds); + if (ret) { + log_debug("%s: led-sources property missing %d\n", + __func__, ret); + continue; + } + + ret = ofnode_read_u32(child, "led-max-microamp", + &bank->full_scale_current); + if (ret) + log_debug("%s: failed getting led-max-microamp %d\n", + __func__, ret); + else + bank->full_scale_current = min(bank->full_scale_current, + LM3532_FS_CURR_MAX); + } + + return 0; +} + +static int lm3532_backlight_init_registers(struct udevice *dev, + struct lm3532_bank_data *bank) +{ + struct lm3532_backlight_priv *priv = dev_get_priv(dev); + u32 brightness_config_val, runtime_ramp_val; + u32 output_cfg_val = 0, output_cfg_shift = 0, output_cfg_mask = 0; + int fs_current_reg, fs_current_val; + int ret, i; + + if (!bank->present) + return 0; + + u32 brightness_config_reg = LM3532_REG_ZONE_CFG_A + bank->control_bank * 2; + /* + * This could be hard coded to the default value but the control + * brightness register may have changed during boot. + */ + ret = dm_i2c_reg_read(dev, brightness_config_reg); + if (ret < 0) + return ret; + + bank->ctrl_brt_pointer = ret & ~LM3532_ZONE_MASK; + brightness_config_val = bank->ctrl_brt_pointer | bank->mode; + + ret = dm_i2c_reg_write(dev, brightness_config_reg, brightness_config_val); + if (ret) + return ret; + + if (bank->full_scale_current) { + fs_current_reg = LM3532_REG_CTRL_A_FS_CURR + bank->control_bank * 2; + fs_current_val = (bank->full_scale_current - LM3532_FS_CURR_MIN) / + LM3532_FS_CURR_STEP; + + ret = dm_i2c_reg_write(dev, fs_current_reg, fs_current_val); + if (ret) + return ret; + } + + for (i = 0; i < bank->num_leds; i++) { + output_cfg_shift = bank->led_strings[i] * 2; + output_cfg_val |= (bank->control_bank << output_cfg_shift); + output_cfg_mask |= LM3532_OUTPUT_CFG_MASK << output_cfg_shift; + } + + ret = dm_i2c_reg_clrset(dev, LM3532_REG_OUTPUT_CFG, output_cfg_mask, + output_cfg_val); + if (ret) + return ret; + + runtime_ramp_val = priv->runtime_ramp_up | + (priv->runtime_ramp_down << LM3532_RAMP_DOWN_SHIFT); + + return dm_i2c_reg_write(dev, LM3532_REG_RT_RAMP, runtime_ramp_val); +} + +static int lm3532_backlight_probe(struct udevice *dev) +{ + struct lm3532_backlight_priv *priv = dev_get_priv(dev); + int ret, i; + + if (device_get_uclass_id(dev->parent) != UCLASS_I2C) + return -EPROTONOSUPPORT; + + dm_gpio_set_value(&priv->enable_gpio, 1); + + for (i = 0; i < LM3532_MAX_CONTROL_BANKS; i++) { + ret = lm3532_backlight_init_registers(dev, &priv->bank[i]); + if (ret) + return ret; + } + + return 0; +} + +static const struct backlight_ops lm3532_backlight_ops = { + .enable = lm3532_backlight_enable, + .set_brightness = lm3532_backlight_set_brightness, +}; + +static const struct udevice_id lm3532_backlight_ids[] = { + { .compatible = "ti,lm3532" }, + { } +}; + +U_BOOT_DRIVER(lm3532_backlight) = { + .name = "lm3532_backlight", + .id = UCLASS_PANEL_BACKLIGHT, + .of_match = lm3532_backlight_ids, + .of_to_plat = lm3532_backlight_of_to_plat, + .probe = lm3532_backlight_probe, + .ops = &lm3532_backlight_ops, + .priv_auto = sizeof(struct lm3532_backlight_priv), +}; From 645350ed4b56f822b6da798c0cec101c3b1e4893 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Sun, 3 Dec 2023 19:34:49 +0200 Subject: [PATCH 15/24] board: motorola: add Atrix 4G MB860 and Droid X2 MB870 support The Motorola Atrix 4G (MB860) and Droid X2 (MB870) both featured a dual-core NVIDIA Tegra 2 AP20H processor clocked at 1GHz, coupled with 1GB of DDR2 RAM. Storage consisted of 16GB of internal flash memory, expandable via microSD. The display was a 4.0-inch TFT LCD with a resolution of 960x540 pixels (qHD). The devices originally ran on Android up to 2.3 (Gingerbread). Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/Makefile | 2 + arch/arm/dts/tegra20-motorola-daytona.dts | 9 + arch/arm/dts/tegra20-motorola-mot.dtsi | 490 ++++++++++++++++++++++ arch/arm/dts/tegra20-motorola-olympus.dts | 9 + arch/arm/mach-tegra/tegra20/Kconfig | 5 + board/motorola/mot/Kconfig | 12 + board/motorola/mot/MAINTAINERS | 7 + board/motorola/mot/Makefile | 9 + board/motorola/mot/configs/daytona.config | 2 + board/motorola/mot/configs/olympus.config | 2 + board/motorola/mot/mot-spl.c | 58 +++ board/motorola/mot/mot.env | 15 + configs/mot_defconfig | 93 ++++ doc/board/index.rst | 1 + doc/board/motorola/index.rst | 9 + doc/board/motorola/mot.rst | 104 +++++ include/configs/mot.h | 25 ++ 17 files changed, 852 insertions(+) create mode 100644 arch/arm/dts/tegra20-motorola-daytona.dts create mode 100644 arch/arm/dts/tegra20-motorola-mot.dtsi create mode 100644 arch/arm/dts/tegra20-motorola-olympus.dts create mode 100644 board/motorola/mot/Kconfig create mode 100644 board/motorola/mot/MAINTAINERS create mode 100644 board/motorola/mot/Makefile create mode 100644 board/motorola/mot/configs/daytona.config create mode 100644 board/motorola/mot/configs/olympus.config create mode 100644 board/motorola/mot/mot-spl.c create mode 100644 board/motorola/mot/mot.env create mode 100644 configs/mot_defconfig create mode 100644 doc/board/motorola/index.rst create mode 100644 doc/board/motorola/mot.rst create mode 100644 include/configs/mot.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 080ea522ed5..341bac1afc5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -87,6 +87,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra20-asus-tf101g.dtb \ tegra20-harmony.dtb \ tegra20-medcom-wide.dtb \ + tegra20-motorola-daytona.dtb \ + tegra20-motorola-olympus.dtb \ tegra20-paz00.dtb \ tegra20-plutux.dtb \ tegra20-seaboard.dtb \ diff --git a/arch/arm/dts/tegra20-motorola-daytona.dts b/arch/arm/dts/tegra20-motorola-daytona.dts new file mode 100644 index 00000000000..1be8887a332 --- /dev/null +++ b/arch/arm/dts/tegra20-motorola-daytona.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-motorola-mot.dtsi" + +/ { + model = "Motorola Droid X2 (MB870)"; + compatible = "motorola,daytona", "nvidia,tegra20"; +}; diff --git a/arch/arm/dts/tegra20-motorola-mot.dtsi b/arch/arm/dts/tegra20-motorola-mot.dtsi new file mode 100644 index 00000000000..f00707c2859 --- /dev/null +++ b/arch/arm/dts/tegra20-motorola-mot.dtsi @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include "tegra20.dtsi" + +/ { + chosen { + stdout-path = &uartb; + }; + + aliases { + i2c0 = &gen1_i2c; + + spi0 = &cpcap_spi; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + rtc1 = "/rtc@7000e000"; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + clocks = <&tegra_car TEGRA20_CLK_DSI>, + <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; + clock-names = "dsi", "parent"; + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel { + compatible = "motorola,mot-panel"; + + reset-gpios = <&gpio TEGRA_GPIO(E, 3) GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_5v0_panel>; + vddio-supply = <&vdd_1v8_vio>; + + backlight = <&backlight>; + }; + }; + }; + + gpio@6000d000 { + volume-buttons-hog { + gpio-hog; + gpios = ; + output-low; + }; + + usb-mux-hog { + gpio-hog; + gpios = ; + output-high; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + crt { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + displaya { + nvidia,pins = "lcsn", "ld0", "ld1", "ld3", + "ld5", "ld6", "ld7", "ld8", + "ld9", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", + "lhp0", "lhp1", "lhp2", "lhs", + "lpp", "lsc0", "lpw1", "lsda", + "lspi"; + nvidia,function = "displaya"; + }; + + gmi { + nvidia,pins = "ata", "atc", "atd", "ate", + "gmb", "gmd", "gpu"; + nvidia,function = "gmi"; + }; + + hdmi { + nvidia,pins = "hdint"; + nvidia,function = "hdmi"; + }; + + i2c1 { + nvidia,pins = "i2cp", "rm"; + nvidia,function = "i2c1"; + }; + + i2c2 { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + + i2c3 { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + kbc { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + osc { + nvidia,pins = "cdev1", "cdev2"; + nvidia,function = "osc"; + }; + + owr { + nvidia,pins = "owc", "uac"; + nvidia,function = "owr"; + }; + + pcie { + nvidia,pins = "gpv"; + nvidia,function = "pcie"; + }; + + pwr-on { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rsvd4 { + nvidia,pins = "lvp0", "lvp1", "lvs", "lsc0", + "ld10", "ld11", "lm1", "ld2", + "ld4", "ldc"; + nvidia,function = "rsvd4"; + }; + + rtck { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + sdio3 { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "sdio3"; + }; + + sdio4 { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + spdif { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + + spi1 { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + + spi2 { + nvidia,pins = "spia", "spib", "spic", "spig", + "spih"; + nvidia,function = "spi2"; + }; + + spi3 { + nvidia,pins = "lm0", "lpw0", "lpw2", "lsc1"; + nvidia,function = "spi3"; + }; + + uarta { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + + uartc { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + uartd { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + ulpi { + nvidia,pins = "uab"; + nvidia,function = "ulpi"; + }; + + vi { + nvidia,pins = "dta", "dtb", "dtc", "dtd", + "dte"; + nvidia,function = "vi"; + }; + + vi-sensor-clk { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + conf-lcsn { + nvidia,pins = "lcsn", "lpw1", "lsck", "lsda", + "lsdi", "ldc"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-ata { + nvidia,pins = "ata", "atb", "atc", "ddc", + "gmc", "gpu", "kbca", "kbcb", + "kbcc", "kbcd", "kbce", "kbcf", + "lm1", "lvp0", "owc", "sdb", + "sdc", "sdd", "sdio1", "uaa", + "uad", "uca", "ucb", "pmce", + "lvs"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-cdev1 { + nvidia,pins = "cdev1", "crtp", "csus", "pta"; + nvidia,pull = ; + }; + + conf-atd { + nvidia,pins = "atd", "ate", "cdev2", "dte", + "gma", "gmb", "gmd", "gme", + "gpu7", "gpv", "hdint", "i2cp", + "irrx", "irtx", "pmc", "rm", + "slxa", "slxc", "slxd", "slxk", + "spdi", "spdo", "spid", "spie", + "spif", "uda", "ck32", "ddrc", + "pmca", "pmcb", "pmcc", "pmcd", + "xm2c", "xm2d"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", + "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", + "ld12", "ld13", "ld14", "ld15", + "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", + "lpp", "lpw0", "lpw2", "lsc0", + "lsc1", "lspi", "lvp1"; + nvidia,tristate = ; + }; + + conf-dap1 { + nvidia,pins = "dap1", "dap2", "dap3", "dap4"; + nvidia,pull = ; + }; + + conf-dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", + "dtf"; + nvidia,pull = ; + nvidia,tristate = ; + }; + + conf-spi2 { + nvidia,pins = "spia", "spib", "spic", "spig", + "spih"; + nvidia,pull = ; + nvidia,tristate = ; + }; + }; + }; + + uartb: serial@70006040 { + clocks = <&tegra_car 7>; + status = "okay"; + }; + + gen1_i2c: i2c@7000c000 { + status = "okay"; + clock-frequency = <400000>; + + backlight: led-controller@38 { + compatible = "ti,lm3532"; + reg = <0x38>; + + enable-gpios = <&gpio TEGRA_GPIO(E, 0) GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight_led: led@0 { + reg = <0>; + + led-sources = <2>; + led-max-microamp = <26600>; + + ti,led-mode = <0>; + ti,linear-mapping-mode; + + label = ":backlight"; + }; + }; + }; + + cpcap_spi: spi@7000d600 { + status = "okay"; + spi-max-frequency = <25000000>; + + pmic: cpcap@0 { + compatible = "motorola,cpcap"; + reg = <0>; + + interrupt-controller; + #interrupt-cells = <2>; + + spi-cs-high; + spi-max-frequency = <8000000>; + + power_button: button { + compatible = "motorola,cpcap-pwrbutton"; + + interrupt-parent = <&pmic>; + interrupts = <23 IRQ_TYPE_NONE>; + + linux,code = ; + }; + + regulator { + compatible = "motorola,mot-cpcap-regulator"; + + regulators { + /* SW1 is vdd_cpu */ + /* SW2 is vdd_core */ + + vdd_1v8_vio: sw3 { + regulator-name = "vdd_1v8_vio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SW4 is vdd_aon (rtc) */ + + vcore_emmc: vsdio { + regulator-name = "vcore_emmc"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: vcsi { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: vsimcard { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + }; + + avdd_3v3_periph: vusb { + regulator-name = "avdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + micro_usb: usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&avdd_3v3_periph>; + }; + + sdmmc3: sdhci@c8000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio TEGRA_GPIO(V, 7) GPIO_ACTIVE_LOW>; + timeout-ms = <500>; + }; + + vdd_5v0_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_disp"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(F, 7) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_usd: regulator-usd { + compatible = "regulator-fixed"; + regulator-name = "vdd_usd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio TEGRA_GPIO(F, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra20-motorola-olympus.dts b/arch/arm/dts/tegra20-motorola-olympus.dts new file mode 100644 index 00000000000..bba5513d6bf --- /dev/null +++ b/arch/arm/dts/tegra20-motorola-olympus.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-motorola-mot.dtsi" + +/ { + model = "Motorola Atrix 4G (MB860)"; + compatible = "motorola,olympus", "nvidia,tegra20"; +}; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index e2735d93e28..63678376840 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -29,6 +29,10 @@ config TARGET_MEDCOM_WIDE bool "Avionic Design Medcom-Wide board" select BOARD_LATE_INIT +config TARGET_MOT + bool "Motorola Tegra20 board" + select BOARD_LATE_INIT + config TARGET_PAZ00 bool "Paz00 board" select BOARD_LATE_INIT @@ -76,6 +80,7 @@ config SYS_SOC source "board/nvidia/harmony/Kconfig" source "board/avionic-design/medcom-wide/Kconfig" +source "board/motorola/mot/Kconfig" source "board/compal/paz00/Kconfig" source "board/acer/picasso/Kconfig" source "board/avionic-design/plutux/Kconfig" diff --git a/board/motorola/mot/Kconfig b/board/motorola/mot/Kconfig new file mode 100644 index 00000000000..8b76165ade7 --- /dev/null +++ b/board/motorola/mot/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MOT + +config SYS_BOARD + default "mot" + +config SYS_VENDOR + default "motorola" + +config SYS_CONFIG_NAME + default "mot" + +endif diff --git a/board/motorola/mot/MAINTAINERS b/board/motorola/mot/MAINTAINERS new file mode 100644 index 00000000000..2aff81a8781 --- /dev/null +++ b/board/motorola/mot/MAINTAINERS @@ -0,0 +1,7 @@ +MOT BOARD +M: Svyatoslav Ryhel +S: Maintained +F: board/motorola/mot/ +F: configs/mot_defconfig +F: doc/board/motorola/mot.rst +F: include/configs/mot.h diff --git a/board/motorola/mot/Makefile b/board/motorola/mot/Makefile new file mode 100644 index 00000000000..f1073c2f287 --- /dev/null +++ b/board/motorola/mot/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2010-2012 +# NVIDIA Corporation +# +# (C) Copyright 2025 +# Svyatoslav Ryhel + +obj-$(CONFIG_XPL_BUILD) += mot-spl.o diff --git a/board/motorola/mot/configs/daytona.config b/board/motorola/mot/configs/daytona.config new file mode 100644 index 00000000000..0b6131b77c9 --- /dev/null +++ b/board/motorola/mot/configs/daytona.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-daytona" +CONFIG_SYS_PROMPT="Tegra20 (Daytona) # " diff --git a/board/motorola/mot/configs/olympus.config b/board/motorola/mot/configs/olympus.config new file mode 100644 index 00000000000..57aa60160dd --- /dev/null +++ b/board/motorola/mot/configs/olympus.config @@ -0,0 +1,2 @@ +CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus" +CONFIG_SYS_PROMPT="Tegra20 (Olympus) # " diff --git a/board/motorola/mot/mot-spl.c b/board/motorola/mot/mot-spl.c new file mode 100644 index 00000000000..a86e5233ac1 --- /dev/null +++ b/board/motorola/mot/mot-spl.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T20 Motorola Atrix 4G and Droid X2 SPL stage configuration + * + * (C) Copyright 2025 + * Svyatoslav Ryhel + */ + +#include +#include +#include +#include +#include +#include + +/* + * Unlike all other supported Tegra devices and most known Tegra devices, the + * both Atrix 4G and Droid X2 have no hardware way to enter APX/RCM mode, which + * may lead to a dangerous situation when, if BCT is set correctly and the + * bootloader is faulty, the device will hang in a permanent brick state. + * Exiting from this state can be done only by disassembling the device and + * shortening testpad to the ground. + * + * To prevent this or to minimize the probability of such an accident, it was + * proposed to add the RCM rebooting hook as early into SPL as possible since + * SPL is much more robust and has minimal changes that can break bootflow. + * + * gpio_early_init_uart() function was chosen as it is the earliest function + * exposed for setup by the device. Hook performs a check for volume up + * button state and triggers RCM if it is pressed. + */ +void gpio_early_init_uart(void) +{ + int value; + + /* Configure pinmux for PR0 */ + pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_KBC); + pinmux_set_pullupdown(PMUX_PINGRP_KBCA, PMUX_PULL_UP); + pinmux_tristate_disable(PMUX_PINGRP_KBCA); + + /* Configure pinmux for PQ0 */ + pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_KBC); + pinmux_set_pullupdown(PMUX_PINGRP_KBCC, PMUX_PULL_UP); + pinmux_tristate_disable(PMUX_PINGRP_KBCC); + + /* Hog column 0 (PQ0) low - active */ + spl_gpio_output(NULL, TEGRA_GPIO(Q, 0), 0); + udelay(500); + + spl_gpio_input(NULL, TEGRA_GPIO(R, 0)); + value = spl_gpio_get_value(NULL, TEGRA_GPIO(R, 0)); + + /* Enter RCM if button is pressed */ + if (!value) { + tegra_pmc_writel(2, PMC_SCRATCH0); + tegra_pmc_writel(PMC_CNTRL_MAIN_RST, PMC_CNTRL); + } +} diff --git a/board/motorola/mot/mot.env b/board/motorola/mot/mot.env new file mode 100644 index 00000000000..f2bf298a997 --- /dev/null +++ b/board/motorola/mot/mot.env @@ -0,0 +1,15 @@ +#include + +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +partitions=name=emmc,start=0,size=-,uuid=${uuid_gpt_rootfs} +boot_dev=1 + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=update bootloader=run flash_uboot +bootmenu_4=reboot RCM=enterrcm +bootmenu_5=reboot=reset +bootmenu_6=power off=poweroff +bootmenu_delay=-1 diff --git a/configs/mot_defconfig b/configs/mot_defconfig new file mode 100644 index 00000000000..40b4feeeb90 --- /dev/null +++ b/configs/mot_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x00110000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="mot" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus" +CONFIG_SPL_STACK=0xffffc +CONFIG_SPL_TEXT_BASE=0x00108000 +CONFIG_SYS_LOAD_ADDR=0x2000000 +CONFIG_TEGRA20=y +CONFIG_TARGET_MOT=y +CONFIG_TEGRA_ENABLE_UARTB=y +CONFIG_CMD_EBTUPDATE=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff" +CONFIG_SYS_PBSIZE=2085 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x90000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra20 (Mot) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x11000000 +CONFIG_FASTBOOT_BUF_SIZE=0x5000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_GPIO_HOG=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_CPCAP_POWER_BUTTON=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_CPCAP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_CPCAP=y +CONFIG_SYS_NS16550=y +CONFIG_TEGRA20_SLINK=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_POWEROFF_GPIO=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Motorola" +CONFIG_USB_GADGET_VENDOR_NUM=0x22b8 +CONFIG_USB_GADGET_PRODUCT_NUM=0x708c +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_LCD_MOT=y +CONFIG_BACKLIGHT_LM3532=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_DSI_TEGRA=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 7ad1137c94a..9ce436af5f9 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -41,6 +41,7 @@ Board-specific doc mediatek/index microchip/index microsoft/index + motorola/index nxp/index openpiton/index ouya/index diff --git a/doc/board/motorola/index.rst b/doc/board/motorola/index.rst new file mode 100644 index 00000000000..9666ff2f4ab --- /dev/null +++ b/doc/board/motorola/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Motorola +======== + +.. toctree:: + :maxdepth: 2 + + mot diff --git a/doc/board/motorola/mot.rst b/doc/board/motorola/mot.rst new file mode 100644 index 00000000000..d0f89bcd357 --- /dev/null +++ b/doc/board/motorola/mot.rst @@ -0,0 +1,104 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Motorola Atrix 4G (MB860) and Droid X2 (MB870) +============================================================= + +``DISCLAMER!`` Moving your device to use U-Boot assumes replacement of the +vendor bootloader. Vendor Android firmwares will no longer be able to run on +the device. This replacement IS reversible if you have backups. + +Quick Start +----------- + +- Prerequisites +- Build U-Boot +- Process U-Boot +- Flashing U-Boot into the eMMC +- Boot +- Self Upgrading + +Prerequisites +------------- + +In order to work with RCM/APX mode, both devices require a factory cable which +is made by routing 5V to the ID pin of a micro-USB cable (5v is applied to both +ID and dedicated 5v). This way, the host PC can detect the device in RCM mode, +and the device can operate without a battery. + +Build U-Boot +------------ + +Device support is implemented by applying config fragment to a generic +board defconfig. Valid fragments are ``daytona.config`` and ``olympus.config``. + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make mot_defconfig olympus.config # For Atrix 4G + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +image, ready for further processing. + +Process U-Boot +-------------- + +``DISCLAMER!`` All questions related to the re-crypt work should be asked +in re-crypt repo issues. NOT HERE! + +re-crypt is a tool that processes the ``u-boot-dtb-tegra.bin`` binary into form +usable by device. This process is required only on the first installation or to +recover the device in case of a failed update. You need to know your device +individual SBK to continue. + +.. code-block:: bash + + $ git clone https://gitlab.com/grate-driver/re-crypt.git + $ cd re-crypt # place your u-boot-dtb-tegra.bin here + $ ./re-crypt.py --dev olympus --sbk --split + +where SBK has next form ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` ``0xXXXXXXXX`` + +The script will produce ``bct.img`` and ``ebt.img`` ready to flash. + +Flashing U-Boot into the eMMC +----------------------------- + +``DISCLAMER!`` All questions related to fusee-tools should be asked in the proper +place. NOT HERE! Flashing U-Boot will erase all eMMC, so make a backup before! + +U-Boot pre-loaded into RAM acts the same as when it was booted "cold". Currently +U-Boot supports bootmenu entry fastboot, which allows to write a processed copy +of U-Boot permanently into eMMC. + +While pre-loading U-Boot, hold the ``volume down`` button which will trigger +the bootmenu. There, select ``fastboot`` using the volume and power buttons. +After, on host PC, do: + +.. code-block:: bash + + $ fastboot flash 0.1 bct.img + $ fastboot flash 0.2 ebt.img + $ fastboot reboot + +Device will reboot. + +Boot +---- + +To boot Linux, U-Boot will look for an ``extlinux.conf`` on MicroSD and then on +eMMC. Additionally, if the Volume Down button is pressed while booting, the +device will enter bootmenu. Bootmenu contains entries to mount MicroSD and eMMC +as mass storage, fastboot, reboot, reboot RCM, poweroff, enter U-Boot console +and update bootloader (check the next chapter). + +Flashing ``repart-block.bin`` eliminates vendor restrictions on eMMC and allows +the user to use/partition it in any way the user desires. + +Self Upgrading +-------------- + +Place your ``u-boot-dtb-tegra.bin`` on the first partition of the MicroSD card +and insert it into the device. Enter bootmenu, choose update the bootloader +option with the Power button and U-Boot should update itself. Once the process +is completed, U-Boot will ask to press any button to reboot. diff --git a/include/configs/mot.h b/include/configs/mot.h new file mode 100644 index 00000000000..63931e90dda --- /dev/null +++ b/include/configs/mot.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "tegra20-common.h" + +/* High-level configuration options */ +#define CFG_TEGRA_BOARD_STRING "Motorola Mot" + +/* Board-specific serial config */ +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTB_BASE + +/* Tegra common post configuration overwrites text env in the board */ +#define BOARD_EXTRA_ENV_SETTINGS \ + "stdin=serial,tegra-kbc,button-kbd,cpcap-pwrbutton\0" + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ From a35bf832d7047662761571b6f80861cb25477030 Mon Sep 17 00:00:00 2001 From: Artur Kowalski Date: Sun, 30 Mar 2025 21:11:54 +0200 Subject: [PATCH 16/24] pinctrl: tegra20: detect unknown/invalid pin/func configurations Tegra20 driver doesn't know about some pin configurations and even about some pins. In case when pin configuration is unknown the pin would be muxed to whatever is under function 0, in case when pin itself is unknown, it could cause out-of-bounds array access in pinmux_set_func and pinmux_set_pullupdown. Signed-off-by: Artur Kowalski Reviewed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel --- drivers/pinctrl/tegra/pinctrl-tegra20.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index d59b3ec7b5d..c32d590a7e0 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -37,6 +37,11 @@ static void tegra_pinctrl_set_pin(struct udevice *config) if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) break; + if (pin_id == PMUX_PINGRP_COUNT) { + log_debug("%s: %s(%d) is not valid\n", __func__, pins[i], pin_id); + continue; + } + if (pull >= 0) pinmux_set_pullupdown(pin_id, pull); @@ -58,13 +63,16 @@ static void tegra_pinctrl_set_func(struct udevice *config) const char **pins; function = dev_read_string(config, "nvidia,function"); - if (function) + if (function) { for (i = 0; i < PMUX_FUNC_COUNT; i++) if (tegra_pinctrl_to_func[i]) if (!strcmp(function, tegra_pinctrl_to_func[i])) break; - func_id = i; + func_id = i; + } else { + func_id = PMUX_FUNC_COUNT; + } count = dev_read_string_list(config, "nvidia,pins", &pins); if (count < 0) { @@ -78,6 +86,12 @@ static void tegra_pinctrl_set_func(struct udevice *config) if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) break; + if (func_id == PMUX_FUNC_COUNT || pin_id == PMUX_PINGRP_COUNT) { + log_debug("%s: pin %s(%d) or function %s(%d) is not valid\n", + __func__, pins[i], pin_id, function, func_id); + continue; + } + debug("%s(%d) muxed to %s(%d)\n", pins[i], pin_id, function, func_id); pinmux_set_func(pin_id, func_id); From e9245a360ac6eb12ee08138de13aeddc34a8d30a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 31 Mar 2025 11:28:53 +0300 Subject: [PATCH 17/24] pinctrl: tegra: detect unknown/invalid pin/func configurations Applies same logic to general Tegra pincontrol driver as is done to Tegra20 by commit: a35bf832d70 ("pinctrl: tegra20: detect unknown/invalid pin/func configurations") Suggested-by: Artur Kowalski Signed-off-by: Svyatoslav Ryhel --- drivers/pinctrl/tegra/pinctrl-tegra.c | 75 +++++++++++++++++++++------ 1 file changed, 59 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index b04be168bc8..bc02825ee1f 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -14,7 +14,7 @@ static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt) { struct pmux_drvgrp_config *drive_group; - int i, ret, pad_id; + int i, ret, pad_id, count = 0; const char **pads; drive_group = kmalloc_array(drvcnt, sizeof(*drive_group), GFP_KERNEL); @@ -46,21 +46,32 @@ static void tegra_pinctrl_set_drive(struct udevice *config, int drvcnt) goto exit; } + /* + * i goes through all drive instances defined, while + * count is increased only if a valid configuration is found + */ for (i = 0; i < drvcnt; i++) { for (pad_id = 0; pad_id < PMUX_DRVGRP_COUNT; pad_id++) if (tegra_pinctrl_to_drvgrp[pad_id]) if (!strcmp(pads[i], tegra_pinctrl_to_drvgrp[pad_id])) { - drive_group[i].drvgrp = pad_id; + drive_group[count].drvgrp = pad_id; break; } - debug("%s drvmap: %d, %d, %d, %d, %d\n", pads[i], - drive_group[i].drvgrp, drive_group[i].slwf, - drive_group[i].slwr, drive_group[i].drvup, - drive_group[i].drvdn); + if (pad_id == PMUX_DRVGRP_COUNT) { + log_debug("%s: drive %s is not valid\n", __func__, pads[i]); + continue; + } + + log_debug("%s(%d) drvmap: %d, %d, %d, %d, %d\n", pads[count], count, + drive_group[count].drvgrp, drive_group[count].slwf, + drive_group[count].slwr, drive_group[count].drvup, + drive_group[count].drvdn); + + count++; } - pinmux_config_drvgrp_table(drive_group, drvcnt); + pinmux_config_drvgrp_table(drive_group, count); free(pads); exit: @@ -71,7 +82,7 @@ exit: static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt) { struct pmux_mipipadctrlgrp_config *mipipad_group; - int i, ret, pad_id; + int i, ret, pad_id, count = 0; const char *function; const char **pads; @@ -89,6 +100,11 @@ static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt) if (!strcmp(function, tegra_pinctrl_to_func[i])) break; + if (!function || i == PMUX_FUNC_COUNT) { + log_debug("%s: pin function is not defined or is not valid\n", __func__); + goto exit; + } + mipipad_group[0].func = i; for (i = 1; i < padcnt; i++) @@ -100,16 +116,27 @@ static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt) goto exit; } + /* + * i goes through all pin instances defined, while + * count is increased only if a valid configuration is found + */ for (i = 0; i < padcnt; i++) { for (pad_id = 0; pad_id < PMUX_MIPIPADCTRLGRP_COUNT; pad_id++) if (tegra_pinctrl_to_mipipadgrp[pad_id]) if (!strcmp(pads[i], tegra_pinctrl_to_mipipadgrp[pad_id])) { - mipipad_group[i].grp = pad_id; + mipipad_group[count].grp = pad_id; break; } + + if (pad_id == PMUX_MIPIPADCTRLGRP_COUNT) { + log_debug("%s: drive %s is not valid\n", __func__, pads[i]); + continue; + } + + count++; } - pinmux_config_mipipadctrlgrp_table(mipipad_group, padcnt); + pinmux_config_mipipadctrlgrp_table(mipipad_group, count); free(pads); exit: @@ -122,7 +149,7 @@ static void tegra_pinctrl_set_mipipad(struct udevice *config, int padcnt) { } static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt) { struct pmux_pingrp_config *pinmux_group; - int i, ret, pin_id; + int i, ret, pin_id, count = 0; const char *function; const char **pins; @@ -140,6 +167,11 @@ static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt) if (!strcmp(function, tegra_pinctrl_to_func[i])) break; + if (!function || i == PMUX_FUNC_COUNT) { + log_debug("%s: pin function is not defined or is not valid\n", __func__); + goto exit; + } + pinmux_group[0].func = i; pinmux_group[0].pull = dev_read_u32_default(config, "nvidia,pull", PMUX_PULL_NORMAL); @@ -178,20 +210,31 @@ static void tegra_pinctrl_set_pin(struct udevice *config, int pincnt) goto exit; } + /* + * i goes through all pin instances defined, while + * count is increased only if a valid configuration is found + */ for (i = 0; i < pincnt; i++) { for (pin_id = 0; pin_id < PMUX_PINGRP_COUNT; pin_id++) if (tegra_pinctrl_to_pingrp[pin_id]) if (!strcmp(pins[i], tegra_pinctrl_to_pingrp[pin_id])) { - pinmux_group[i].pingrp = pin_id; + pinmux_group[count].pingrp = pin_id; break; } - debug("%s pinmap: %d, %d, %d, %d\n", pins[i], - pinmux_group[i].pingrp, pinmux_group[i].func, - pinmux_group[i].pull, pinmux_group[i].tristate); + if (pin_id == PMUX_PINGRP_COUNT) { + log_debug("%s: pin %s is not valid\n", __func__, pins[i]); + continue; + } + + log_debug("%s(%d) pinmap: %d, %d, %d, %d\n", pins[count], count, + pinmux_group[count].pingrp, pinmux_group[count].func, + pinmux_group[count].pull, pinmux_group[count].tristate); + + count++; } - pinmux_config_pingrp_table(pinmux_group, pincnt); + pinmux_config_pingrp_table(pinmux_group, count); free(pins); exit: From 11bf63c23028f54d299a24c494242a11dcb387c7 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 31 Mar 2025 09:33:17 +0300 Subject: [PATCH 18/24] ARM: tegra: board: set CFG_SYS_NS16550_COM1 according to TEGRA_ENABLE_UART Link CFG_SYS_NS16550_COM1 value to chosen CONFIG_TEGRA_ENABLE_UART Tegra wide. Remove all CFG_SYS_NS16550_COM1 from device headers. Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/board.c | 5 +++++ include/configs/apalis-tk1.h | 3 --- include/configs/apalis_t30.h | 1 - include/configs/beaver.h | 3 --- include/configs/cardhu.h | 3 --- include/configs/cei-tk1-som.h | 3 --- include/configs/colibri_t20.h | 4 ---- include/configs/colibri_t30.h | 1 - include/configs/dalmore.h | 3 --- include/configs/endeavoru.h | 3 --- include/configs/grouper.h | 3 --- include/configs/harmony.h | 9 --------- include/configs/ideapad-yoga-11.h | 3 --- include/configs/jetson-tk1.h | 3 --- include/configs/medcom-wide.h | 3 --- include/configs/mocha.h | 3 --- include/configs/mot.h | 3 --- include/configs/nyan-big.h | 3 --- include/configs/ouya.h | 3 --- include/configs/paz00.h | 3 --- include/configs/picasso.h | 3 --- include/configs/plutux.h | 3 --- include/configs/qc750.h | 3 --- include/configs/seaboard.h | 3 --- include/configs/surface-rt.h | 3 --- include/configs/tec-ng.h | 3 --- include/configs/tec.h | 3 --- include/configs/transformer-t20.h | 3 --- include/configs/transformer-t30.h | 3 --- include/configs/trimslice.h | 3 --- include/configs/venice2.h | 3 --- include/configs/ventana.h | 3 --- include/configs/x3-t30.h | 3 --- 33 files changed, 5 insertions(+), 99 deletions(-) diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 7ca56a3b081..8c946f0f117 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -236,18 +236,23 @@ void board_init_uart_f(void) int uart_ids = 0; /* bit mask of which UART ids to enable */ #ifdef CONFIG_TEGRA_ENABLE_UARTA +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE uart_ids |= UARTA; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTB +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTB_BASE uart_ids |= UARTB; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTC +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTC_BASE uart_ids |= UARTC; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTD +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE uart_ids |= UARTD; #endif #ifdef CONFIG_TEGRA_ENABLE_UARTE +#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTE_BASE uart_ids |= UARTE; #endif setup_uarts(uart_ids); diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 4c690a17856..dbb9881f6ab 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -12,9 +12,6 @@ #include "tegra124-common.h" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #define FDT_MODULE "apalis-v1.2" #define FDT_MODULE_V1_0 "apalis" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 87a679efde6..c806ad0d9da 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -20,7 +20,6 @@ * Apalis UART3: NVIDIA UARTB * Apalis UART4: NVIDIA UARTC */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/beaver.h b/include/configs/beaver.h index e622b7127e3..229b766eefa 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Beaver" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 3412b883cbb..c33c96a5eb4 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index fbd38b77fe5..7b09441258c 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -18,9 +18,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "CEI tk1-som" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index bc616d14368..d96a87c059e 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -9,10 +9,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index 1f474669a73..0c93f377361 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -21,7 +21,6 @@ * Colibri UART-B: NVIDIA UARTD * Colibri UART-C: NVIDIA UARTB */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE #include "tegra-common-post.h" diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 095554157fa..82911eb6165 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Dalmore" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h index 33d0021ec13..20ffda0d251 100644 --- a/include/configs/endeavoru.h +++ b/include/configs/endeavoru.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "HTC One X" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/grouper.h b/include/configs/grouper.h index b6ef6ff2ecb..834e249d148 100644 --- a/include/configs/grouper.h +++ b/include/configs/grouper.h @@ -11,9 +11,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index cae7acdb70b..793fdffb277 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -13,15 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Harmony" -/* Board-specific serial config */ - -/* UARTD: keyboard satellite board UART, default */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#ifdef CONFIG_TEGRA_ENABLE_UARTA -/* UARTA: debug board UART */ -#define CFG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE -#endif - /* NAND support */ /* Environment in NAND (which is 512M), aligned to start of last sector */ diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h index c4e6b2a647c..0f98f890ef7 100644 --- a/include/configs/ideapad-yoga-11.h +++ b/include/configs/ideapad-yoga-11.h @@ -11,9 +11,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Lenovo Ideapad Yoga 11" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 9858f8ff2b5..2fb1c353ff8 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index 8dbe741278a..7694a2fc84c 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* NAND support */ /* Environment in NAND, aligned to start of last sector */ diff --git a/include/configs/mocha.h b/include/configs/mocha.h index 1c2eb906085..a84d599ccc9 100644 --- a/include/configs/mocha.h +++ b/include/configs/mocha.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Xiaomi Mocha" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE #define CFG_PRAM 0x38400 /* 225 MB */ #endif diff --git a/include/configs/mot.h b/include/configs/mot.h index 63931e90dda..28b8d504769 100644 --- a/include/configs/mot.h +++ b/include/configs/mot.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Motorola Mot" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTB_BASE - /* Tegra common post configuration overwrites text env in the board */ #define BOARD_EXTRA_ENV_SETTINGS \ "stdin=serial,tegra-kbc,button-kbd,cpcap-pwrbutton\0" diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index c04d402deb0..84db4bc3bca 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ouya.h b/include/configs/ouya.h index cc86c1002e3..a9f05ae5d01 100644 --- a/include/configs/ouya.h +++ b/include/configs/ouya.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Ouya Game Console" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 950b3217642..2d8d1f652bb 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Compal Paz00" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/picasso.h b/include/configs/picasso.h index a58c7e5f353..0b08a562018 100644 --- a/include/configs/picasso.h +++ b/include/configs/picasso.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 30bfce9f503..5d7e85d9284 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Avionic Design Plutux" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* NAND support */ /* Environment in NAND, aligned to start of last sector */ diff --git a/include/configs/qc750.h b/include/configs/qc750.h index ad9f9146bb7..f226d5a4c08 100644 --- a/include/configs/qc750.h +++ b/include/configs/qc750.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Wexler QC750" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 8e98620422d..79de9f83876 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Seaboard" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ /* NAND support */ diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h index 1f0837e179b..58be786ca77 100644 --- a/include/configs/surface-rt.h +++ b/include/configs/surface-rt.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Microsoft Surface RT" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 5e49abb49fa..4e610164fa3 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -12,9 +12,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h index 05dd7c96f61..cb10c0397f9 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* NAND support */ /* Environment in NAND, aligned to start of last sector */ diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h index 6a3d9b24036..1876d2cdc69 100644 --- a/include/configs/transformer-t20.h +++ b/include/configs/transformer-t20.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "ASUS Transformer" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h index 792b958a302..37828d3a9d9 100644 --- a/include/configs/transformer-t30.h +++ b/include/configs/transformer-t30.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "ASUS Transformer" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 7d1ff2afd14..c4f6defddbc 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "Compulab Trimslice" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - /* SPI */ /* Environment in SPI */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index 353b5ea67c1..fa001afdc0f 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -14,9 +14,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Venice2" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 1d9c60ca7c6..7a6e0254545 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -13,9 +13,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "NVIDIA Ventana" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - /* Environment in eMMC, at the end of 2nd "boot sector" */ #include "tegra-common-post.h" diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index c152af9b7e2..286de6a3af4 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -15,9 +15,6 @@ /* High-level configuration options */ #define CFG_TEGRA_BOARD_STRING "LG X3 Board" -/* Board-specific serial config */ -#define CFG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - #include "tegra-common-post.h" #endif /* __CONFIG_H */ From ee3462160cf2fdf29b44ef83df0265a19c37bc0a Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 31 Mar 2025 16:44:24 +0300 Subject: [PATCH 19/24] ARM: tegra: convert CFG_TEGRA_BOARD_STRING into Kconfig option Convert CFG_TEGRA_BOARD_STRING into Kconfig option and move it into device board Kconfig. Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/board2.c | 2 +- board/acer/picasso/Kconfig | 4 ++++ board/asus/grouper/Kconfig | 4 ++++ board/asus/transformer-t20/Kconfig | 4 ++++ board/asus/transformer-t30/Kconfig | 4 ++++ board/avionic-design/medcom-wide/Kconfig | 4 ++++ board/avionic-design/plutux/Kconfig | 4 ++++ board/avionic-design/tec-ng/Kconfig | 4 ++++ board/avionic-design/tec/Kconfig | 4 ++++ board/cei/cei-tk1-som/Kconfig | 4 ++++ board/compal/paz00/Kconfig | 4 ++++ board/compulab/trimslice/Kconfig | 4 ++++ board/htc/endeavoru/Kconfig | 4 ++++ board/lenovo/ideapad-yoga-11/Kconfig | 4 ++++ board/lg/x3-t30/Kconfig | 4 ++++ board/microsoft/surface-rt/Kconfig | 4 ++++ board/motorola/mot/Kconfig | 4 ++++ board/nvidia/beaver/Kconfig | 4 ++++ board/nvidia/cardhu/Kconfig | 4 ++++ board/nvidia/dalmore/Kconfig | 4 ++++ board/nvidia/harmony/Kconfig | 4 ++++ board/nvidia/jetson-tk1/Kconfig | 4 ++++ board/nvidia/nyan-big/Kconfig | 4 ++++ board/nvidia/p2371-0000/Kconfig | 4 ++++ board/nvidia/p2371-2180/Kconfig | 4 ++++ board/nvidia/p2571/Kconfig | 4 ++++ board/nvidia/p2771-0000/Kconfig | 4 ++++ board/nvidia/p3450-0000/Kconfig | 4 ++++ board/nvidia/seaboard/Kconfig | 4 ++++ board/nvidia/venice2/Kconfig | 4 ++++ board/nvidia/ventana/Kconfig | 4 ++++ board/ouya/ouya/Kconfig | 4 ++++ board/wexler/qc750/Kconfig | 4 ++++ board/xiaomi/mocha/Kconfig | 4 ++++ include/configs/beaver.h | 4 ---- include/configs/cardhu.h | 4 ---- include/configs/cei-tk1-som.h | 4 ---- include/configs/dalmore.h | 6 ------ include/configs/endeavoru.h | 4 ---- include/configs/grouper.h | 4 ---- include/configs/harmony.h | 8 -------- include/configs/ideapad-yoga-11.h | 4 ---- include/configs/jetson-tk1.h | 4 ---- include/configs/medcom-wide.h | 8 -------- include/configs/mocha.h | 3 --- include/configs/mot.h | 3 --- include/configs/nyan-big.h | 4 ---- include/configs/ouya.h | 4 ---- include/configs/p2371-0000.h | 8 -------- include/configs/p2371-2180.h | 8 -------- include/configs/p2571.h | 8 -------- include/configs/p2771-0000.h | 6 ------ include/configs/p3450-0000.h | 7 ------- include/configs/paz00.h | 6 ------ include/configs/picasso.h | 4 ---- include/configs/plutux.h | 8 -------- include/configs/qc750.h | 4 ---- include/configs/seaboard.h | 10 ---------- include/configs/surface-rt.h | 4 ---- include/configs/tec-ng.h | 4 ---- include/configs/tec.h | 8 -------- include/configs/transformer-t20.h | 4 ---- include/configs/transformer-t30.h | 4 ---- include/configs/trimslice.h | 9 --------- include/configs/venice2.h | 6 ------ include/configs/ventana.h | 6 ------ include/configs/x3-t30.h | 4 ---- 67 files changed, 133 insertions(+), 183 deletions(-) diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 6e9ef68caf9..68534dcbb22 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -96,7 +96,7 @@ int checkboard(void) { int board_id = tegra_board_id(); - printf("Board: %s", CFG_TEGRA_BOARD_STRING); + printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); if (board_id != -1) printf(", ID: %d\n", board_id); printf("\n"); diff --git a/board/acer/picasso/Kconfig b/board/acer/picasso/Kconfig index 73c0aa08508..c801bd26c7c 100644 --- a/board/acer/picasso/Kconfig +++ b/board/acer/picasso/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "picasso" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Acer Iconia Tab A500" + endif diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig index f935cce4225..5f25680d916 100644 --- a/board/asus/grouper/Kconfig +++ b/board/asus/grouper/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "grouper" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "ASUS Google Nexus 7 (2012)" + endif diff --git a/board/asus/transformer-t20/Kconfig b/board/asus/transformer-t20/Kconfig index d5fe4128289..2bf42825270 100644 --- a/board/asus/transformer-t20/Kconfig +++ b/board/asus/transformer-t20/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "transformer-t20" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "ASUS Transformer T20" + endif diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig index 915436ba6c5..04278f139dc 100644 --- a/board/asus/transformer-t30/Kconfig +++ b/board/asus/transformer-t30/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "transformer-t30" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "ASUS Transformer T30" + endif diff --git a/board/avionic-design/medcom-wide/Kconfig b/board/avionic-design/medcom-wide/Kconfig index 267647cb41f..741fc258b3a 100644 --- a/board/avionic-design/medcom-wide/Kconfig +++ b/board/avionic-design/medcom-wide/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "medcom-wide" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Avionic Design Medcom-Wide" + endif diff --git a/board/avionic-design/plutux/Kconfig b/board/avionic-design/plutux/Kconfig index 09a3ac940da..57324dc19e7 100644 --- a/board/avionic-design/plutux/Kconfig +++ b/board/avionic-design/plutux/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "plutux" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Avionic Design Plutux" + endif diff --git a/board/avionic-design/tec-ng/Kconfig b/board/avionic-design/tec-ng/Kconfig index 36a0cec1be1..34e2729fd60 100644 --- a/board/avionic-design/tec-ng/Kconfig +++ b/board/avionic-design/tec-ng/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "tec-ng" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Avionic Design Tamonten™ NG Evaluation Carrier" + endif diff --git a/board/avionic-design/tec/Kconfig b/board/avionic-design/tec/Kconfig index bc9751b1086..56b417950eb 100644 --- a/board/avionic-design/tec/Kconfig +++ b/board/avionic-design/tec/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "tec" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Avionic Design Tamonten Evaluation Carrier" + endif diff --git a/board/cei/cei-tk1-som/Kconfig b/board/cei/cei-tk1-som/Kconfig index 5fcb51f2f26..32ff61ac44d 100644 --- a/board/cei/cei-tk1-som/Kconfig +++ b/board/cei/cei-tk1-som/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "cei-tk1-som" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "CEI tk1-som" + endif diff --git a/board/compal/paz00/Kconfig b/board/compal/paz00/Kconfig index 30ba11d360a..0ddac85be12 100644 --- a/board/compal/paz00/Kconfig +++ b/board/compal/paz00/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "paz00" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Compal Paz00" + endif diff --git a/board/compulab/trimslice/Kconfig b/board/compulab/trimslice/Kconfig index 35769140347..b26c2970fe4 100644 --- a/board/compulab/trimslice/Kconfig +++ b/board/compulab/trimslice/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "trimslice" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Compulab Trimslice" + endif diff --git a/board/htc/endeavoru/Kconfig b/board/htc/endeavoru/Kconfig index 0b72c4a687d..f0967376647 100644 --- a/board/htc/endeavoru/Kconfig +++ b/board/htc/endeavoru/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "endeavoru" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "HTC One X" + endif diff --git a/board/lenovo/ideapad-yoga-11/Kconfig b/board/lenovo/ideapad-yoga-11/Kconfig index 67644409fc1..670a5bb700c 100644 --- a/board/lenovo/ideapad-yoga-11/Kconfig +++ b/board/lenovo/ideapad-yoga-11/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "ideapad-yoga-11" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Lenovo Ideapad Yoga 11" + endif diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig index 53b6ab3e93c..5a3a67d9f3b 100644 --- a/board/lg/x3-t30/Kconfig +++ b/board/lg/x3-t30/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "x3-t30" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "LG X3 Board" + endif diff --git a/board/microsoft/surface-rt/Kconfig b/board/microsoft/surface-rt/Kconfig index 9e66897f6b1..7c8f67f21cb 100644 --- a/board/microsoft/surface-rt/Kconfig +++ b/board/microsoft/surface-rt/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "surface-rt" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Microsoft Surface RT" + endif diff --git a/board/motorola/mot/Kconfig b/board/motorola/mot/Kconfig index 8b76165ade7..3f6f03e95b5 100644 --- a/board/motorola/mot/Kconfig +++ b/board/motorola/mot/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mot" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Motorola Mot" + endif diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/beaver/Kconfig index 23f7c945f57..be461214223 100644 --- a/board/nvidia/beaver/Kconfig +++ b/board/nvidia/beaver/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "beaver" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Beaver" + endif diff --git a/board/nvidia/cardhu/Kconfig b/board/nvidia/cardhu/Kconfig index 63ace66aa78..8a98ace70b5 100644 --- a/board/nvidia/cardhu/Kconfig +++ b/board/nvidia/cardhu/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "cardhu" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Cardhu" + endif diff --git a/board/nvidia/dalmore/Kconfig b/board/nvidia/dalmore/Kconfig index 96eaa01cf87..643e082ec06 100644 --- a/board/nvidia/dalmore/Kconfig +++ b/board/nvidia/dalmore/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "dalmore" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Dalmore" + endif diff --git a/board/nvidia/harmony/Kconfig b/board/nvidia/harmony/Kconfig index 328c94677da..1f2bfdfe5d8 100644 --- a/board/nvidia/harmony/Kconfig +++ b/board/nvidia/harmony/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "harmony" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Harmony" + endif diff --git a/board/nvidia/jetson-tk1/Kconfig b/board/nvidia/jetson-tk1/Kconfig index d90a74ea382..7a2ffd83c84 100644 --- a/board/nvidia/jetson-tk1/Kconfig +++ b/board/nvidia/jetson-tk1/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "jetson-tk1" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Jetson TK1" + endif diff --git a/board/nvidia/nyan-big/Kconfig b/board/nvidia/nyan-big/Kconfig index 341c8d75c21..b239d69f5e5 100644 --- a/board/nvidia/nyan-big/Kconfig +++ b/board/nvidia/nyan-big/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "nyan-big" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Google/NVIDIA Nyan-big" + endif diff --git a/board/nvidia/p2371-0000/Kconfig b/board/nvidia/p2371-0000/Kconfig index f94be12be1a..28e9f39045c 100644 --- a/board/nvidia/p2371-0000/Kconfig +++ b/board/nvidia/p2371-0000/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p2371-0000" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P2371-0000" + endif diff --git a/board/nvidia/p2371-2180/Kconfig b/board/nvidia/p2371-2180/Kconfig index 8622bdaa16b..ffb412229c1 100644 --- a/board/nvidia/p2371-2180/Kconfig +++ b/board/nvidia/p2371-2180/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p2371-2180" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P2371-2180" + endif diff --git a/board/nvidia/p2571/Kconfig b/board/nvidia/p2571/Kconfig index 7bc48748408..1fc1978c639 100644 --- a/board/nvidia/p2571/Kconfig +++ b/board/nvidia/p2571/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p2571" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P2571" + endif diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig index 1b1116f0209..52a22b79734 100644 --- a/board/nvidia/p2771-0000/Kconfig +++ b/board/nvidia/p2771-0000/Kconfig @@ -13,4 +13,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p2771-0000" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P2771-0000" + endif diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig index 7a08cd88675..48a94e24d54 100644 --- a/board/nvidia/p3450-0000/Kconfig +++ b/board/nvidia/p3450-0000/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "p3450-0000" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA P3450-0000" + endif diff --git a/board/nvidia/seaboard/Kconfig b/board/nvidia/seaboard/Kconfig index 0924bde480f..df62519c652 100644 --- a/board/nvidia/seaboard/Kconfig +++ b/board/nvidia/seaboard/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "seaboard" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Seaboard" + endif diff --git a/board/nvidia/venice2/Kconfig b/board/nvidia/venice2/Kconfig index 6905f0014ea..7bd51c7a278 100644 --- a/board/nvidia/venice2/Kconfig +++ b/board/nvidia/venice2/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "venice2" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Venice2" + endif diff --git a/board/nvidia/ventana/Kconfig b/board/nvidia/ventana/Kconfig index c1ad7b76712..ea1146f75b7 100644 --- a/board/nvidia/ventana/Kconfig +++ b/board/nvidia/ventana/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "ventana" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA Ventana" + endif diff --git a/board/ouya/ouya/Kconfig b/board/ouya/ouya/Kconfig index 6bab40ce933..2db127f3e14 100644 --- a/board/ouya/ouya/Kconfig +++ b/board/ouya/ouya/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "ouya" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Ouya Game Console" + endif diff --git a/board/wexler/qc750/Kconfig b/board/wexler/qc750/Kconfig index 45a1e5e057b..29943358b84 100644 --- a/board/wexler/qc750/Kconfig +++ b/board/wexler/qc750/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "qc750" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Wexler QC750" + endif diff --git a/board/xiaomi/mocha/Kconfig b/board/xiaomi/mocha/Kconfig index 25c61d4169e..bb53cc56161 100644 --- a/board/xiaomi/mocha/Kconfig +++ b/board/xiaomi/mocha/Kconfig @@ -9,4 +9,8 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mocha" +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "Xiaomi Mocha" + endif diff --git a/include/configs/beaver.h b/include/configs/beaver.h index 229b766eefa..21b37b78a30 100644 --- a/include/configs/beaver.h +++ b/include/configs/beaver.h @@ -9,10 +9,6 @@ #include #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Beaver" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index c33c96a5eb4..7fc2d85f7bd 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -9,10 +9,6 @@ #include #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Cardhu" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index 7b09441258c..aa4057d6da0 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -14,10 +14,6 @@ #include #include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "CEI tk1-som" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 82911eb6165..0946588230d 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -9,12 +9,6 @@ #include #include "tegra114-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Dalmore" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h index 20ffda0d251..8cb3e414af2 100644 --- a/include/configs/endeavoru.h +++ b/include/configs/endeavoru.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "HTC One X" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/grouper.h b/include/configs/grouper.h index 834e249d148..aacbcf12658 100644 --- a/include/configs/grouper.h +++ b/include/configs/grouper.h @@ -7,10 +7,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Google Nexus 7 (2012)" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 793fdffb277..beecb70cd0c 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -9,14 +9,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Harmony" - -/* NAND support */ - -/* Environment in NAND (which is 512M), aligned to start of last sector */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h index 0f98f890ef7..aacbcf12658 100644 --- a/include/configs/ideapad-yoga-11.h +++ b/include/configs/ideapad-yoga-11.h @@ -7,10 +7,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Lenovo Ideapad Yoga 11" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 2fb1c353ff8..e4ee5ce6be8 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -10,10 +10,6 @@ #include #include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index 7694a2fc84c..becff398a56 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -10,14 +10,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" - -/* NAND support */ - -/* Environment in NAND, aligned to start of last sector */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/mocha.h b/include/configs/mocha.h index a84d599ccc9..7255f31baec 100644 --- a/include/configs/mocha.h +++ b/include/configs/mocha.h @@ -10,9 +10,6 @@ #include "tegra124-common.h" -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Xiaomi Mocha" - #ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE #define CFG_PRAM 0x38400 /* 225 MB */ #endif diff --git a/include/configs/mot.h b/include/configs/mot.h index 28b8d504769..018672cb28f 100644 --- a/include/configs/mot.h +++ b/include/configs/mot.h @@ -10,9 +10,6 @@ #include #include "tegra20-common.h" -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Motorola Mot" - /* Tegra common post configuration overwrites text env in the board */ #define BOARD_EXTRA_ENV_SETTINGS \ "stdin=serial,tegra-kbc,button-kbd,cpcap-pwrbutton\0" diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 84db4bc3bca..808cd908972 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -10,10 +10,6 @@ #include #include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ouya.h b/include/configs/ouya.h index a9f05ae5d01..381941760e3 100644 --- a/include/configs/ouya.h +++ b/include/configs/ouya.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Ouya Game Console" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h index a29d7135d0b..79240bd8ed0 100644 --- a/include/configs/p2371-0000.h +++ b/include/configs/p2371-0000.h @@ -10,14 +10,6 @@ #include #include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" - -/* Board-specific serial config */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h index 0b077aba659..24f3a7030e8 100644 --- a/include/configs/p2371-2180.h +++ b/include/configs/p2371-2180.h @@ -10,14 +10,6 @@ #include #include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" - -/* Board-specific serial config */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h index 5155aa7b1dd..0dbb45e7c2a 100644 --- a/include/configs/p2571.h +++ b/include/configs/p2571.h @@ -10,14 +10,6 @@ #include #include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2571" - -/* Board-specific serial config */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* _P2571_H */ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h index fc1b7c0302d..914c68ffdf9 100644 --- a/include/configs/p2771-0000.h +++ b/include/configs/p2771-0000.h @@ -9,12 +9,6 @@ #include #include "tegra186-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h index 1138c1d306f..c5a74e8f8fe 100644 --- a/include/configs/p3450-0000.h +++ b/include/configs/p3450-0000.h @@ -9,13 +9,6 @@ #include #include "tegra210-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA P3450-0000" - -/* Board-specific serial config */ - -/* General networking support */ #include "tegra-common-post.h" #endif /* _P3450_0000_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h index 2d8d1f652bb..ec123804545 100644 --- a/include/configs/paz00.h +++ b/include/configs/paz00.h @@ -11,12 +11,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Compal Paz00" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/picasso.h b/include/configs/picasso.h index 0b08a562018..4b6837dc000 100644 --- a/include/configs/picasso.h +++ b/include/configs/picasso.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Acer Iconia Tab A500" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 5d7e85d9284..becff398a56 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -10,14 +10,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Plutux" - -/* NAND support */ - -/* Environment in NAND, aligned to start of last sector */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/qc750.h b/include/configs/qc750.h index f226d5a4c08..2acafb488b1 100644 --- a/include/configs/qc750.h +++ b/include/configs/qc750.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Wexler QC750" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 79de9f83876..4a2c6623ac1 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -10,16 +10,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Seaboard" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - -/* NAND support */ - -/* Max number of NAND devices */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h index 58be786ca77..39f7dddf3d4 100644 --- a/include/configs/surface-rt.h +++ b/include/configs/surface-rt.h @@ -9,10 +9,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Microsoft Surface RT" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h index 4e610164fa3..3d6cb0b5257 100644 --- a/include/configs/tec-ng.h +++ b/include/configs/tec-ng.h @@ -8,10 +8,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h index cb10c0397f9..becff398a56 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -10,14 +10,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" - -/* NAND support */ - -/* Environment in NAND, aligned to start of last sector */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h index 1876d2cdc69..b82c6e34c8f 100644 --- a/include/configs/transformer-t20.h +++ b/include/configs/transformer-t20.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h index 37828d3a9d9..8cb3e414af2 100644 --- a/include/configs/transformer-t30.h +++ b/include/configs/transformer-t30.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "ASUS Transformer" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index c4f6defddbc..beecb70cd0c 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -9,15 +9,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "Compulab Trimslice" - -/* SPI */ - -/* Environment in SPI */ -/* 1MiB flash, environment located as high as possible */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h index fa001afdc0f..bbebe53d17e 100644 --- a/include/configs/venice2.h +++ b/include/configs/venice2.h @@ -10,12 +10,6 @@ #include #include "tegra124-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Venice2" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h index 7a6e0254545..00f9909b122 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -9,12 +9,6 @@ #include #include "tegra20-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "NVIDIA Ventana" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ - #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h index 286de6a3af4..8cb3e414af2 100644 --- a/include/configs/x3-t30.h +++ b/include/configs/x3-t30.h @@ -11,10 +11,6 @@ #define __CONFIG_H #include "tegra30-common.h" - -/* High-level configuration options */ -#define CFG_TEGRA_BOARD_STRING "LG X3 Board" - #include "tegra-common-post.h" #endif /* __CONFIG_H */ From 9ee12daa591b8adefa8ae221295a85e2ee467742 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Mon, 31 Mar 2025 17:18:18 +0300 Subject: [PATCH 20/24] ARM: tegra: replace per-device config headers with generic Tegra Most device headers contain SoC specific part and common Tegra post part. Add a generic header which can be used by any Tegra device of one of the supported SoC generations (T20, T30, T114, T124 or T210) without need in device specific configuration. Signed-off-by: Svyatoslav Ryhel --- board/acer/picasso/Kconfig | 2 +- board/asus/grouper/Kconfig | 2 +- board/asus/transformer-t20/Kconfig | 2 +- board/asus/transformer-t30/Kconfig | 2 +- board/avionic-design/medcom-wide/Kconfig | 2 +- board/avionic-design/plutux/Kconfig | 2 +- board/avionic-design/tec-ng/Kconfig | 2 +- board/avionic-design/tec/Kconfig | 2 +- board/cei/cei-tk1-som/Kconfig | 2 +- board/compal/paz00/Kconfig | 2 +- board/compulab/trimslice/Kconfig | 2 +- board/htc/endeavoru/Kconfig | 2 +- board/lenovo/ideapad-yoga-11/Kconfig | 2 +- board/lg/x3-t30/Kconfig | 2 +- board/microsoft/surface-rt/Kconfig | 2 +- board/nvidia/beaver/Kconfig | 2 +- board/nvidia/cardhu/Kconfig | 2 +- board/nvidia/dalmore/Kconfig | 2 +- board/nvidia/harmony/Kconfig | 2 +- board/nvidia/jetson-tk1/Kconfig | 2 +- board/nvidia/nyan-big/Kconfig | 2 +- board/nvidia/p2371-0000/Kconfig | 2 +- board/nvidia/p2371-2180/Kconfig | 2 +- board/nvidia/p2571/Kconfig | 2 +- board/nvidia/p2771-0000/Kconfig | 2 +- board/nvidia/p3450-0000/Kconfig | 2 +- board/nvidia/seaboard/Kconfig | 2 +- board/nvidia/venice2/Kconfig | 2 +- board/nvidia/ventana/Kconfig | 2 +- board/ouya/ouya/Kconfig | 2 +- board/toradex/apalis_t30/Kconfig | 2 +- board/toradex/apalis_t30/apalis_t30.env | 9 ++++++ board/toradex/colibri_t20/Kconfig | 2 +- board/toradex/colibri_t30/Kconfig | 2 +- board/toradex/colibri_t30/colibri_t30.env | 8 ++++++ board/wexler/qc750/Kconfig | 2 +- include/configs/apalis_t30.h | 26 ----------------- include/configs/beaver.h | 14 ---------- include/configs/cardhu.h | 14 ---------- include/configs/cei-tk1-som.h | 19 ------------- include/configs/colibri_t20.h | 14 ---------- include/configs/colibri_t30.h | 27 ------------------ include/configs/dalmore.h | 14 ---------- include/configs/endeavoru.h | 16 ----------- include/configs/grouper.h | 12 -------- include/configs/harmony.h | 14 ---------- include/configs/ideapad-yoga-11.h | 12 -------- include/configs/jetson-tk1.h | 15 ---------- include/configs/medcom-wide.h | 15 ---------- include/configs/nyan-big.h | 15 ---------- include/configs/ouya.h | 16 ----------- include/configs/p2371-0000.h | 15 ---------- include/configs/p2371-2180.h | 15 ---------- include/configs/p2571.h | 15 ---------- include/configs/p2771-0000.h | 14 ---------- include/configs/p3450-0000.h | 14 ---------- include/configs/paz00.h | 16 ----------- include/configs/picasso.h | 16 ----------- include/configs/plutux.h | 15 ---------- include/configs/qc750.h | 16 ----------- include/configs/seaboard.h | 15 ---------- include/configs/surface-rt.h | 14 ---------- include/configs/tec-ng.h | 13 --------- include/configs/tec.h | 15 ---------- include/configs/tegra.h | 34 +++++++++++++++++++++++ include/configs/transformer-t20.h | 16 ----------- include/configs/transformer-t30.h | 16 ----------- include/configs/trimslice.h | 14 ---------- include/configs/venice2.h | 15 ---------- include/configs/ventana.h | 14 ---------- include/configs/x3-t30.h | 16 ----------- 71 files changed, 85 insertions(+), 561 deletions(-) delete mode 100644 include/configs/apalis_t30.h delete mode 100644 include/configs/beaver.h delete mode 100644 include/configs/cardhu.h delete mode 100644 include/configs/cei-tk1-som.h delete mode 100644 include/configs/colibri_t20.h delete mode 100644 include/configs/colibri_t30.h delete mode 100644 include/configs/dalmore.h delete mode 100644 include/configs/endeavoru.h delete mode 100644 include/configs/grouper.h delete mode 100644 include/configs/harmony.h delete mode 100644 include/configs/ideapad-yoga-11.h delete mode 100644 include/configs/jetson-tk1.h delete mode 100644 include/configs/medcom-wide.h delete mode 100644 include/configs/nyan-big.h delete mode 100644 include/configs/ouya.h delete mode 100644 include/configs/p2371-0000.h delete mode 100644 include/configs/p2371-2180.h delete mode 100644 include/configs/p2571.h delete mode 100644 include/configs/p2771-0000.h delete mode 100644 include/configs/p3450-0000.h delete mode 100644 include/configs/paz00.h delete mode 100644 include/configs/picasso.h delete mode 100644 include/configs/plutux.h delete mode 100644 include/configs/qc750.h delete mode 100644 include/configs/seaboard.h delete mode 100644 include/configs/surface-rt.h delete mode 100644 include/configs/tec-ng.h delete mode 100644 include/configs/tec.h create mode 100644 include/configs/tegra.h delete mode 100644 include/configs/transformer-t20.h delete mode 100644 include/configs/transformer-t30.h delete mode 100644 include/configs/trimslice.h delete mode 100644 include/configs/venice2.h delete mode 100644 include/configs/ventana.h delete mode 100644 include/configs/x3-t30.h diff --git a/board/acer/picasso/Kconfig b/board/acer/picasso/Kconfig index c801bd26c7c..879b778aa53 100644 --- a/board/acer/picasso/Kconfig +++ b/board/acer/picasso/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "acer" config SYS_CONFIG_NAME - default "picasso" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/asus/grouper/Kconfig b/board/asus/grouper/Kconfig index 5f25680d916..3bd712b274c 100644 --- a/board/asus/grouper/Kconfig +++ b/board/asus/grouper/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "asus" config SYS_CONFIG_NAME - default "grouper" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/asus/transformer-t20/Kconfig b/board/asus/transformer-t20/Kconfig index 2bf42825270..3e80d38d590 100644 --- a/board/asus/transformer-t20/Kconfig +++ b/board/asus/transformer-t20/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "asus" config SYS_CONFIG_NAME - default "transformer-t20" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/asus/transformer-t30/Kconfig b/board/asus/transformer-t30/Kconfig index 04278f139dc..34fd6f200f8 100644 --- a/board/asus/transformer-t30/Kconfig +++ b/board/asus/transformer-t30/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "asus" config SYS_CONFIG_NAME - default "transformer-t30" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/avionic-design/medcom-wide/Kconfig b/board/avionic-design/medcom-wide/Kconfig index 741fc258b3a..54474b5061a 100644 --- a/board/avionic-design/medcom-wide/Kconfig +++ b/board/avionic-design/medcom-wide/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "avionic-design" config SYS_CONFIG_NAME - default "medcom-wide" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/avionic-design/plutux/Kconfig b/board/avionic-design/plutux/Kconfig index 57324dc19e7..35b19dd2ea0 100644 --- a/board/avionic-design/plutux/Kconfig +++ b/board/avionic-design/plutux/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "avionic-design" config SYS_CONFIG_NAME - default "plutux" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/avionic-design/tec-ng/Kconfig b/board/avionic-design/tec-ng/Kconfig index 34e2729fd60..8782e7a2a67 100644 --- a/board/avionic-design/tec-ng/Kconfig +++ b/board/avionic-design/tec-ng/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "avionic-design" config SYS_CONFIG_NAME - default "tec-ng" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/avionic-design/tec/Kconfig b/board/avionic-design/tec/Kconfig index 56b417950eb..12cc4e1f4d0 100644 --- a/board/avionic-design/tec/Kconfig +++ b/board/avionic-design/tec/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "avionic-design" config SYS_CONFIG_NAME - default "tec" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/cei/cei-tk1-som/Kconfig b/board/cei/cei-tk1-som/Kconfig index 32ff61ac44d..9b944730e63 100644 --- a/board/cei/cei-tk1-som/Kconfig +++ b/board/cei/cei-tk1-som/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "cei" config SYS_CONFIG_NAME - default "cei-tk1-som" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/compal/paz00/Kconfig b/board/compal/paz00/Kconfig index 0ddac85be12..7fa47fc8c77 100644 --- a/board/compal/paz00/Kconfig +++ b/board/compal/paz00/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "compal" config SYS_CONFIG_NAME - default "paz00" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/compulab/trimslice/Kconfig b/board/compulab/trimslice/Kconfig index b26c2970fe4..226ebc228a8 100644 --- a/board/compulab/trimslice/Kconfig +++ b/board/compulab/trimslice/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "compulab" config SYS_CONFIG_NAME - default "trimslice" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/htc/endeavoru/Kconfig b/board/htc/endeavoru/Kconfig index f0967376647..ef50da9be45 100644 --- a/board/htc/endeavoru/Kconfig +++ b/board/htc/endeavoru/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "htc" config SYS_CONFIG_NAME - default "endeavoru" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/lenovo/ideapad-yoga-11/Kconfig b/board/lenovo/ideapad-yoga-11/Kconfig index 670a5bb700c..cd4aa32d86d 100644 --- a/board/lenovo/ideapad-yoga-11/Kconfig +++ b/board/lenovo/ideapad-yoga-11/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "lenovo" config SYS_CONFIG_NAME - default "ideapad-yoga-11" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/lg/x3-t30/Kconfig b/board/lg/x3-t30/Kconfig index 5a3a67d9f3b..d2cdf860db4 100644 --- a/board/lg/x3-t30/Kconfig +++ b/board/lg/x3-t30/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "lg" config SYS_CONFIG_NAME - default "x3-t30" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/microsoft/surface-rt/Kconfig b/board/microsoft/surface-rt/Kconfig index 7c8f67f21cb..6afddb9b363 100644 --- a/board/microsoft/surface-rt/Kconfig +++ b/board/microsoft/surface-rt/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "microsoft" config SYS_CONFIG_NAME - default "surface-rt" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/beaver/Kconfig index be461214223..fe36d475b30 100644 --- a/board/nvidia/beaver/Kconfig +++ b/board/nvidia/beaver/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "beaver" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/cardhu/Kconfig b/board/nvidia/cardhu/Kconfig index 8a98ace70b5..92de3f2e669 100644 --- a/board/nvidia/cardhu/Kconfig +++ b/board/nvidia/cardhu/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "cardhu" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/dalmore/Kconfig b/board/nvidia/dalmore/Kconfig index 643e082ec06..8da3499b9f5 100644 --- a/board/nvidia/dalmore/Kconfig +++ b/board/nvidia/dalmore/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "dalmore" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/harmony/Kconfig b/board/nvidia/harmony/Kconfig index 1f2bfdfe5d8..eedee71cac9 100644 --- a/board/nvidia/harmony/Kconfig +++ b/board/nvidia/harmony/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "harmony" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/jetson-tk1/Kconfig b/board/nvidia/jetson-tk1/Kconfig index 7a2ffd83c84..9eeb55f639d 100644 --- a/board/nvidia/jetson-tk1/Kconfig +++ b/board/nvidia/jetson-tk1/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "jetson-tk1" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/nyan-big/Kconfig b/board/nvidia/nyan-big/Kconfig index b239d69f5e5..65fef3c063f 100644 --- a/board/nvidia/nyan-big/Kconfig +++ b/board/nvidia/nyan-big/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "nyan-big" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p2371-0000/Kconfig b/board/nvidia/p2371-0000/Kconfig index 28e9f39045c..e2770781a25 100644 --- a/board/nvidia/p2371-0000/Kconfig +++ b/board/nvidia/p2371-0000/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p2371-0000" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p2371-2180/Kconfig b/board/nvidia/p2371-2180/Kconfig index ffb412229c1..8d97dc354b6 100644 --- a/board/nvidia/p2371-2180/Kconfig +++ b/board/nvidia/p2371-2180/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p2371-2180" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p2571/Kconfig b/board/nvidia/p2571/Kconfig index 1fc1978c639..1d41e9d68f4 100644 --- a/board/nvidia/p2571/Kconfig +++ b/board/nvidia/p2571/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p2571" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig index 52a22b79734..199e04da07e 100644 --- a/board/nvidia/p2771-0000/Kconfig +++ b/board/nvidia/p2771-0000/Kconfig @@ -11,7 +11,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p2771-0000" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/p3450-0000/Kconfig b/board/nvidia/p3450-0000/Kconfig index 48a94e24d54..9235c2a0c35 100644 --- a/board/nvidia/p3450-0000/Kconfig +++ b/board/nvidia/p3450-0000/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "p3450-0000" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/seaboard/Kconfig b/board/nvidia/seaboard/Kconfig index df62519c652..a6baeeb7f87 100644 --- a/board/nvidia/seaboard/Kconfig +++ b/board/nvidia/seaboard/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "seaboard" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/venice2/Kconfig b/board/nvidia/venice2/Kconfig index 7bd51c7a278..9ebaa2fa413 100644 --- a/board/nvidia/venice2/Kconfig +++ b/board/nvidia/venice2/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "venice2" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/nvidia/ventana/Kconfig b/board/nvidia/ventana/Kconfig index ea1146f75b7..b8654c24e0b 100644 --- a/board/nvidia/ventana/Kconfig +++ b/board/nvidia/ventana/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "nvidia" config SYS_CONFIG_NAME - default "ventana" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/ouya/ouya/Kconfig b/board/ouya/ouya/Kconfig index 2db127f3e14..c698f730412 100644 --- a/board/ouya/ouya/Kconfig +++ b/board/ouya/ouya/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "ouya" config SYS_CONFIG_NAME - default "ouya" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig index 9cd497091d6..6260f8eb7f4 100644 --- a/board/toradex/apalis_t30/Kconfig +++ b/board/toradex/apalis_t30/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "toradex" config SYS_CONFIG_NAME - default "apalis_t30" + default "tegra" config TDX_CFG_BLOCK default y diff --git a/board/toradex/apalis_t30/apalis_t30.env b/board/toradex/apalis_t30/apalis_t30.env index a8f2904bcd7..85d0a05d0e1 100644 --- a/board/toradex/apalis_t30/apalis_t30.env +++ b/board/toradex/apalis_t30/apalis_t30.env @@ -1,6 +1,15 @@ uboot_hwpart=1 uboot_blk=0 +/* + * Board-specific serial config + * + * Apalis UART1: NVIDIA UARTA + * Apalis UART2: NVIDIA UARTD + * Apalis UART3: NVIDIA UARTB + * Apalis UART4: NVIDIA UARTC + */ + set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig index a43acddb801..8a7295a41e2 100644 --- a/board/toradex/colibri_t20/Kconfig +++ b/board/toradex/colibri_t20/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "toradex" config SYS_CONFIG_NAME - default "colibri_t20" + default "tegra" config TDX_CFG_BLOCK default y diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig index 68ef82b099d..643309fe856 100644 --- a/board/toradex/colibri_t30/Kconfig +++ b/board/toradex/colibri_t30/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "toradex" config SYS_CONFIG_NAME - default "colibri_t30" + default "tegra" config TDX_CFG_BLOCK default y diff --git a/board/toradex/colibri_t30/colibri_t30.env b/board/toradex/colibri_t30/colibri_t30.env index a8f2904bcd7..87919fbf155 100644 --- a/board/toradex/colibri_t30/colibri_t30.env +++ b/board/toradex/colibri_t30/colibri_t30.env @@ -1,6 +1,14 @@ uboot_hwpart=1 uboot_blk=0 +/* + * Board-specific serial config + * + * Colibri UART-A: NVIDIA UARTA + * Colibri UART-B: NVIDIA UARTD + * Colibri UART-C: NVIDIA UARTB + */ + set_blkcnt=setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 update_uboot=run set_blkcnt && mmc dev 0 ${uboot_hwpart} && diff --git a/board/wexler/qc750/Kconfig b/board/wexler/qc750/Kconfig index 29943358b84..b449720a8b3 100644 --- a/board/wexler/qc750/Kconfig +++ b/board/wexler/qc750/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "wexler" config SYS_CONFIG_NAME - default "qc750" + default "tegra" config TEGRA_BOARD_STRING string "Default Tegra board name" diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h deleted file mode 100644 index c806ad0d9da..00000000000 --- a/include/configs/apalis_t30.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014-2016 Marcel Ziswiler - * - * Configuration settings for the Toradex Apalis T30 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" - -/* - * Board-specific serial config - * - * Apalis UART1: NVIDIA UARTA - * Apalis UART2: NVIDIA UARTD - * Apalis UART3: NVIDIA UARTB - * Apalis UART4: NVIDIA UARTC - */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/beaver.h b/include/configs/beaver.h deleted file mode 100644 index 21b37b78a30..00000000000 --- a/include/configs/beaver.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h deleted file mode 100644 index 7fc2d85f7bd..00000000000 --- a/include/configs/cardhu.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h deleted file mode 100644 index aa4057d6da0..00000000000 --- a/include/configs/cei-tk1-som.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (c) Copyright 2016, Data61 - * Commonwealth Scientific and Industrial Research Organisation (CSIRO) - * - * Based on jetson-tk1.h which is: - * (C) Copyright 2013-2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h deleted file mode 100644 index d96a87c059e..00000000000 --- a/include/configs/colibri_t20.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Lucas Stach - * - * Configuration settings for the Toradex Colibri T20 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h deleted file mode 100644 index 0c93f377361..00000000000 --- a/include/configs/colibri_t30.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013-2016 Stefan Agner - * - * Configuration settings for the Toradex Colibri T30 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" - -/* High-level configuration options */ - -/* - * Board-specific serial config - * - * Colibri UART-A: NVIDIA UARTA - * Colibri UART-B: NVIDIA UARTD - * Colibri UART-C: NVIDIA UARTB - */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h deleted file mode 100644 index 0946588230d..00000000000 --- a/include/configs/dalmore.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra114-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/endeavoru.h b/include/configs/endeavoru.h deleted file mode 100644 index 8cb3e414af2..00000000000 --- a/include/configs/endeavoru.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2022 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/grouper.h b/include/configs/grouper.h deleted file mode 100644 index aacbcf12658..00000000000 --- a/include/configs/grouper.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h deleted file mode 100644 index beecb70cd0c..00000000000 --- a/include/configs/harmony.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ideapad-yoga-11.h b/include/configs/ideapad-yoga-11.h deleted file mode 100644 index aacbcf12658..00000000000 --- a/include/configs/ideapad-yoga-11.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h deleted file mode 100644 index e4ee5ce6be8..00000000000 --- a/include/configs/jetson-tk1.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2013-2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h deleted file mode 100644 index becff398a56..00000000000 --- a/include/configs/medcom-wide.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * (C) Copyright 2011-2012 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h deleted file mode 100644 index 808cd908972..00000000000 --- a/include/configs/nyan-big.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ouya.h b/include/configs/ouya.h deleted file mode 100644 index 381941760e3..00000000000 --- a/include/configs/ouya.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2025 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/p2371-0000.h b/include/configs/p2371-0000.h deleted file mode 100644 index 79240bd8ed0..00000000000 --- a/include/configs/p2371-0000.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _P2371_0000_H -#define _P2371_0000_H - -#include - -#include "tegra210-common.h" -#include "tegra-common-post.h" - -#endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h deleted file mode 100644 index 24f3a7030e8..00000000000 --- a/include/configs/p2371-2180.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _P2371_2180_H -#define _P2371_2180_H - -#include - -#include "tegra210-common.h" -#include "tegra-common-post.h" - -#endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h deleted file mode 100644 index 0dbb45e7c2a..00000000000 --- a/include/configs/p2571.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _P2571_H -#define _P2571_H - -#include - -#include "tegra210-common.h" -#include "tegra-common-post.h" - -#endif /* _P2571_H */ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h deleted file mode 100644 index 914c68ffdf9..00000000000 --- a/include/configs/p2771-0000.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013-2016, NVIDIA CORPORATION. - */ - -#ifndef _P2771_0000_H -#define _P2771_0000_H - -#include - -#include "tegra186-common.h" -#include "tegra-common-post.h" - -#endif diff --git a/include/configs/p3450-0000.h b/include/configs/p3450-0000.h deleted file mode 100644 index c5a74e8f8fe..00000000000 --- a/include/configs/p3450-0000.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2018-2019 NVIDIA Corporation. - */ - -#ifndef _P3450_0000_H -#define _P3450_0000_H - -#include - -#include "tegra210-common.h" -#include "tegra-common-post.h" - -#endif /* _P3450_0000_H */ diff --git a/include/configs/paz00.h b/include/configs/paz00.h deleted file mode 100644 index ec123804545..00000000000 --- a/include/configs/paz00.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/picasso.h b/include/configs/picasso.h deleted file mode 100644 index 4b6837dc000..00000000000 --- a/include/configs/picasso.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * - * (C) Copyright 2024 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h deleted file mode 100644 index becff398a56..00000000000 --- a/include/configs/plutux.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * (C) Copyright 2011-2012 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/qc750.h b/include/configs/qc750.h deleted file mode 100644 index 2acafb488b1..00000000000 --- a/include/configs/qc750.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2023 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h deleted file mode 100644 index 4a2c6623ac1..00000000000 --- a/include/configs/seaboard.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/surface-rt.h b/include/configs/surface-rt.h deleted file mode 100644 index 39f7dddf3d4..00000000000 --- a/include/configs/surface-rt.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - * - * Copyright (c) 2021, Open Surface RT - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h deleted file mode 100644 index 3d6cb0b5257..00000000000 --- a/include/configs/tec-ng.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h deleted file mode 100644 index becff398a56..00000000000 --- a/include/configs/tec.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * (C) Copyright 2011-2012 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tegra.h b/include/configs/tegra.h new file mode 100644 index 00000000000..77bc38930d2 --- /dev/null +++ b/include/configs/tegra.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation + * + * (C) Copyright 2025 + * Svyatoslav Ryhel + * + * Generic device header which can be used with SYS_CONFIG_NAME + * for any Tegra device (T20, T30, T114, T124, T186 or T210). + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#ifdef CONFIG_TEGRA20 +#include "tegra20-common.h" +#elif CONFIG_TEGRA30 +#include "tegra30-common.h" +#elif CONFIG_TEGRA114 +#include "tegra114-common.h" +#elif CONFIG_TEGRA124 +#include "tegra124-common.h" +#elif CONFIG_TEGRA186 +#include "tegra186-common.h" +#elif CONFIG_TEGRA210 +#include "tegra210-common.h" +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t20.h b/include/configs/transformer-t20.h deleted file mode 100644 index b82c6e34c8f..00000000000 --- a/include/configs/transformer-t20.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * - * (C) Copyright 2022 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/transformer-t30.h b/include/configs/transformer-t30.h deleted file mode 100644 index 8cb3e414af2..00000000000 --- a/include/configs/transformer-t30.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2022 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h deleted file mode 100644 index beecb70cd0c..00000000000 --- a/include/configs/trimslice.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h deleted file mode 100644 index bbebe53d17e..00000000000 --- a/include/configs/venice2.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h deleted file mode 100644 index 00f9909b122..00000000000 --- a/include/configs/ventana.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/x3-t30.h b/include/configs/x3-t30.h deleted file mode 100644 index 8cb3e414af2..00000000000 --- a/include/configs/x3-t30.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2010,2012 - * NVIDIA Corporation - * - * (C) Copyright 2022 - * Svyatoslav Ryhel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ From 69dffab9416c45f0341675aafd2c84e11df2d749 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 3 Apr 2025 10:52:51 +0300 Subject: [PATCH 21/24] ARM: tegra114: clock: avoid touching DISP clocks on init The clock initialization routine sets the DISP* clock parent to PLLC, resulting in DC failure in the case when PLLD was previously configured. This issue disrupts chainloading and to prevent failures caused by DISP* clock parent conflicts, clock initialization should not modify DISP*. The DC driver handles DISP* configuration. Signed-off-by: Svyatoslav Ryhel --- arch/arm/mach-tegra/tegra114/clock.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c index d5cc8ac44dd..d67d808b724 100644 --- a/arch/arm/mach-tegra/tegra114/clock.c +++ b/arch/arm/mach-tegra/tegra114/clock.c @@ -796,7 +796,6 @@ struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC5, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC6, CLOCK_ID_PERIPH }, { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH }, - { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL }, { PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH }, From 00d4996a82a459706109f4146cf6ac12e1477c7e Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Tue, 14 Mar 2023 18:24:51 +0200 Subject: [PATCH 22/24] board: asus: transformer: add ASUS Transformer Pad TF701T support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ASUS Transformer Pad TF701T is an Android tablet computer made by ASUS, successor to the ASUS Transformer Pad Infinity. The tablet includes a Tegra 4 T114 processor clocked at 1.9 GHz, and an upgraded 2560×1600 pixel resolution screen, increasing the pixel density to 300 PPI and a mobile dock. Transformers (t114) board derives from Nvidia Macallan development board. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra114-asus-tf701t.dts | 1245 +++++++++++++++++ arch/arm/mach-tegra/tegra114/Kconfig | 5 + board/asus/transformer-t114/Kconfig | 16 + board/asus/transformer-t114/MAINTAINERS | 8 + board/asus/transformer-t114/Makefile | 10 + .../transformer-t114/transformer-t114-spl.c | 42 + .../asus/transformer-t114/transformer-t114.c | 57 + .../transformer-t114/transformer-t114.env | 15 + configs/tf701t_defconfig | 89 ++ doc/board/asus/index.rst | 1 + doc/board/asus/transformer_t114.rst | 74 + include/configs/transformer-t114.h | 19 + 13 files changed, 1582 insertions(+) create mode 100644 arch/arm/dts/tegra114-asus-tf701t.dts create mode 100644 board/asus/transformer-t114/Kconfig create mode 100644 board/asus/transformer-t114/MAINTAINERS create mode 100644 board/asus/transformer-t114/Makefile create mode 100644 board/asus/transformer-t114/transformer-t114-spl.c create mode 100644 board/asus/transformer-t114/transformer-t114.c create mode 100644 board/asus/transformer-t114/transformer-t114.env create mode 100644 configs/tf701t_defconfig create mode 100644 doc/board/asus/transformer_t114.rst create mode 100644 include/configs/transformer-t114.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 341bac1afc5..c0bae4dd9e2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -118,6 +118,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-ouya.dtb \ tegra30-tec-ng.dtb \ tegra30-wexler-qc750.dtb \ + tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ tegra124-apalis.dtb \ tegra124-jetson-tk1.dtb \ diff --git a/arch/arm/dts/tegra114-asus-tf701t.dts b/arch/arm/dts/tegra114-asus-tf701t.dts new file mode 100644 index 00000000000..2505b9bb726 --- /dev/null +++ b/arch/arm/dts/tegra114-asus-tf701t.dts @@ -0,0 +1,1245 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra114.dtsi" + +/ { + model = "ASUS Transformer Pad TF701T"; + compatible = "asus,tf701t", "nvidia,tegra114"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + usb1 = &usb3; /* Dock USB */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + nvidia,ganged-mode = <&dsib>; + + panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + + link2 = <&panel_secondary>; + + power-supply = <&dvdd_1v8_lcd>; + backlight = <&backlight>; + }; + }; + + dsib: dsi@54400000 { + clocks = <&tegra_car TEGRA114_CLK_DSIB>, + <&tegra_car TEGRA114_CLK_DSIBLP>, + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel_secondary: panel@0 { + compatible = "sharp,lq101r1sx01"; + reg = <0>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* WLAN SDIO pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-power { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-reset { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-host-wake { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + wlan-3v3-com { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-A pinmux */ + uarta-cts { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uarta-rts { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GNSS UART-B pinmux */ + uartb-cts { + nvidia,pins = "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartb-rts { + nvidia,pins = "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartb-rxd { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartb-txd { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Bluetooth UART-C pinmux */ + uartc-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartc-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-shutdown { + nvidia,pins = "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-dev-wake { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-host-wake { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-pcm-dap4-out { + nvidia,pins = "dap4_fs_pp4", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + bt-pcm-dap4-in { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UART-D pinmux */ + uartd-cts { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartd-rts { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* MicroSD pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-data { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_cd_n_pv2", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + microsd-pwr { + nvidia,pins = "gmi_clk_pk1"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* EMMC pinmux */ + sdmmc4-clk-cmd { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-data { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + ddc-i2c { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,lock = ; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + nvidia,lock = ; + }; + + /* SPI pinmux */ + spi1-out { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi1-in { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi2 { + nvidia,pins = "ulpi_data4_po5", + "ulpi_data7_po0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi4-out { + nvidia,pins = "gmi_ad6_pg6", + "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spi4-in { + nvidia,pins = "gmi_ad5_pg5", + "gmi_ad7_pg7"; + nvidia,function = "spi4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO keys pinmux */ + hall-switch { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + lineout-switch { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + power-key { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + volume-keys { + nvidia,pins = "kb_row1_pr1", + "kb_row2_pr2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Sensors pinmux */ + nct-irq { + nvidia,pins = "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + mpu-irq { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI pinmux */ + hdmi-hpd { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi-en { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hdmi-cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* LED pinmux */ + backlight-pwm { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + backlight-en { + nvidia,pins = "gmi_ad10_ph2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Touchscreen pinmux */ + touch-irq { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-rst { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-pwr { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + touch-vio { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUDIO pinmux */ + audio-ldo1 { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hp-detect { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s0-in { + nvidia,pins = "dap1_din_pn1"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s0-out { + nvidia,pins = "dap1_dout_pn2", + "dap1_fs_pn0", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s1-in { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s1-out { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s2-in { + nvidia,pins = "dap3_fs_pp0", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap-i2s2-out { + nvidia,pins = "dap3_din_pp1"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif-in { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + spdif-out { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AsusEC pinmux */ + ec-irq { + nvidia,pins = "kb_col5_pq5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ec-req { + nvidia,pins = "kb_col2_pq2"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + hotplug-i2c { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "spi2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ps2-irq { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kbd-irq { + nvidia,pins = "gmi_cs0_n_pj0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dvfs-pin { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* Core pinmux */ + clk-32k-out { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sys-clk-req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* ULPI pinmux */ + ulpi-data0-6 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data1-5 { + nvidia,pins = "ulpi_data1_po2", + "ulpi_data5_po6"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data2-3 { + nvidia,pins = "ulpi_data2_po3", + "ulpi_data3_po4"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT V */ + pv0-gpio { + nvidia,pins = "pv0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1-gpio { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT U */ + pu0-gpio { + nvidia,pins = "pu0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu2-gpio { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PWM pinmux */ + pwm0 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwm1 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* EXTPERIPH pinmux */ + clk1-out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1-req { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GMI pinmux */ + gmi-wp-n { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-adv { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad0-ad1 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad2-ad3 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-iordy { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-a18 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-wait { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs6-n { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs7-n { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-dqs-p { + nvidia,pins = "gmi_dqs_p_pj3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs2-ad { + nvidia,pins = "gmi_cs2_n_pk3", + "gmi_ad14_ph6", + "gmi_ad15_ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs4-clk { + nvidia,pins = "gmi_cs4_n_pk2", + "gmi_clk_lb"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad11 { + nvidia,pins = "gmi_ad11_ph3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs1-oe { + nvidia,pins = "gmi_cs1_n_pj2", + "gmi_oe_n_pi1"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad4 { + nvidia,pins = "gmi_ad4_pg4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad13 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-rst-n { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT CC */ + pcc-gpio { + nvidia,pins = "pcc1", "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT BB */ + pbb3-gpio { + nvidia,pins = "pbb3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb4-5-6-gpio { + nvidia,pins = "pbb4", "pbb5", "pbb6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pbb7-gpio { + nvidia,pins = "pbb7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC pinmux */ + kb-r0-c1 { + nvidia,pins = "kb_row0_pr0", + "kb_col1_pq1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row4 { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row5 { + nvidia,pins = "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-r8-c3 { + nvidia,pins = "kb_row8_ps0", + "kb_col3_pq3"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* VI pinmux */ + cam-mclk { + nvidia,pins = "cam_mclk_pcc0", + "pbb0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUD pinmux */ + gpio-x4-aud { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x1-aud { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x3-aud { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x6-aud { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + usb-vbus { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GPIO power/drive control */ + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive-sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive-gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: smps9 { + regulator-name = "vdd_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: ldo2 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_usb: ldousb { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + /* USB via ASUS connector */ + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* Dock's USB port */ + usb3: usb@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-hall-sensor { + label = "Hall Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + dvdd_1v8_lcd: regulator-lcdvio { + compatible = "regulator-fixed"; + regulator-name = "dvdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index 5f0f909dd3b..fb88696ae41 100644 --- a/arch/arm/mach-tegra/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig @@ -8,11 +8,16 @@ config TARGET_DALMORE bool "NVIDIA Tegra114 Dalmore evaluation board" select BOARD_LATE_INIT +config TARGET_TRANSFORMER_T114 + bool "ASUS Tegra114 Transformer board" + select BOARD_LATE_INIT + endchoice config SYS_SOC default "tegra114" source "board/nvidia/dalmore/Kconfig" +source "board/asus/transformer-t114/Kconfig" endif diff --git a/board/asus/transformer-t114/Kconfig b/board/asus/transformer-t114/Kconfig new file mode 100644 index 00000000000..2560c35846e --- /dev/null +++ b/board/asus/transformer-t114/Kconfig @@ -0,0 +1,16 @@ +if TARGET_TRANSFORMER_T114 + +config SYS_BOARD + default "transformer-t114" + +config SYS_VENDOR + default "asus" + +config SYS_CONFIG_NAME + default "transformer-t114" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "ASUS Transformer T114" + +endif diff --git a/board/asus/transformer-t114/MAINTAINERS b/board/asus/transformer-t114/MAINTAINERS new file mode 100644 index 00000000000..2e8f01b98df --- /dev/null +++ b/board/asus/transformer-t114/MAINTAINERS @@ -0,0 +1,8 @@ +TRANSFORMER T114 BOARD +M: Svyatoslav Ryhel +S: Maintained +F: arch/arm/dts/tegra114-asus-tf701t.dts +F: board/asus/transformer-t114/ +F: configs/tf701t_defconfig +F: doc/board/asus/transformer_t114.rst +F: include/configs/transformer-t114.h diff --git a/board/asus/transformer-t114/Makefile b/board/asus/transformer-t114/Makefile new file mode 100644 index 00000000000..37dda5fea92 --- /dev/null +++ b/board/asus/transformer-t114/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +# +# Copyright (c) 2023, Svyatoslav Ryhel +# + +obj-$(CONFIG_XPL_BUILD) += transformer-t114-spl.o + +obj-y += transformer-t114.o diff --git a/board/asus/transformer-t114/transformer-t114-spl.c b/board/asus/transformer-t114/transformer-t114-spl.c new file mode 100644 index 00000000000..ceddff36dfc --- /dev/null +++ b/board/asus/transformer-t114/transformer-t114-spl.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * T114 Transformers SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +#define TPS65913_I2C_ADDR (0x58 << 1) + +#define TPS65913_SMPS12_CTRL 0x20 +#define TPS65913_SMPS12_VOLTAGE 0x23 +#define TPS65913_SMPS45_CTRL 0x28 +#define TPS65913_SMPS45_VOLTAGE 0x2B + +#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL) +#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE) +#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL) +#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE) + +void pmic_enable_cpu_vdd(void) +{ + /* Set CORE VDD to 1.200V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA); + + udelay(1000); + + /* Set CPU VDD to 1.0125V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA); + udelay(10 * 1000); +} diff --git a/board/asus/transformer-t114/transformer-t114.c b/board/asus/transformer-t114/transformer-t114.c new file mode 100644 index 00000000000..cca64b51e75 --- /dev/null +++ b/board/asus/transformer-t114/transformer-t114.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +/* T114 Transformers derive from Macallan board */ + +#include +#include +#include +#include + +#ifdef CONFIG_MMC_SDHCI_TEGRA + +#define TPS65913_I2C_ADDRESS 0x58 +#define TPS65913_PRIMARY_SECONDARY_PAD2 0xfb +#define GPIO_4 BIT(0) +#define TPS65913_PRIMARY_SECONDARY_PAD3 0xfe +#define DVFS2 BIT(1) +#define DVFS1 BIT(0) + +/* We are using this function only till palmas pinctrl driver is available */ +void pin_mux_mmc(void) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("%s: cannot find PMIC I2C chip\n", __func__); + return; + } + + /* GPIO4 function has to be GPIO */ + dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2, + GPIO_4, 0); + + /* DVFS1 is enabled, DVFS2 is disabled */ + dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3, + DVFS2 | DVFS1, DVFS1); +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + + return 0; +} +#endif diff --git a/board/asus/transformer-t114/transformer-t114.env b/board/asus/transformer-t114/transformer-t114.env new file mode 100644 index 00000000000..f7278b8661e --- /dev/null +++ b/board/asus/transformer-t114/transformer-t114.env @@ -0,0 +1,15 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +button_cmd_1_name=Hall Sensor +button_cmd_1=poweroff + +fastboot_partition_alias_boot=CAC +fastboot_partition_alias_root=UDA + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0:e; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/configs/tf701t_defconfig b/configs/tf701t_defconfig new file mode 100644 index 00000000000..69bc945568d --- /dev/null +++ b/configs/tf701t_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_SYS_MALLOC_LEN=0x2500000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="transformer-t114" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra114-asus-tf701t" +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TEGRA114=y +CONFIG_TARGET_TRANSFORMER_T114=y +CONFIG_TEGRA_ENABLE_UARTD=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff" +CONFIG_SYS_PBSIZE=2086 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra114 (Transformer) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_TEGRA_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_PALMAS_GPIO=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_PALMAS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_PALMAS=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="ASUS" +CONFIG_USB_GADGET_VENDOR_NUM=0x0b05 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4daf +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_FONT_8X16 is not set +CONFIG_VIDEO_FONT_16X32=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_LCD_SHARP_LQ101R1SX01=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_DSI_TEGRA=y diff --git a/doc/board/asus/index.rst b/doc/board/asus/index.rst index 2cac04ce04a..a9ba7a5ac53 100644 --- a/doc/board/asus/index.rst +++ b/doc/board/asus/index.rst @@ -9,3 +9,4 @@ ASUS grouper transformer_t20 transformer_t30 + transformer_t114 diff --git a/doc/board/asus/transformer_t114.rst b/doc/board/asus/transformer_t114.rst new file mode 100644 index 00000000000..3e42b5dd9a3 --- /dev/null +++ b/doc/board/asus/transformer_t114.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the ASUS Transformer device family +============================================= + +Quick Start +----------- + +- Build U-Boot +- Boot U-Boot by loading it into RAM (coldboot) +- Chainloading U-Boot from the vendor bootloader +- Boot + +Build U-Boot +------------ + +U-Boot can be built in two forms: U-Boot with SPL, which is used for booting +by loading directly into RAM and U-Boot without SPL, which can be flashed +and chainloaded from the vendor bootloader. + +To build U-Boot with SPL proseed: + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make tf701t_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +file, ready for cold booting by loading into RAM. + +To build U-Boot without SPL adjust tf701t_defconfig: + +.. code-block:: + + CONFIG_TEXT_BASE=0x80A00000 + CONFIG_SKIP_LOWLEVEL_INIT=y + # CONFIG_OF_BOARD_SETUP is not set + CONFIG_TEGRA_SUPPORT_NON_SECURE=y + +After the build succeeds, you will obtain the final ``u-boot-dtb.bin`` file, +ready for booting with fastboot boot or which can be further processed into +a flashable boot.img. + +Boot U-Boot by loading it into RAM (coldboot) +--------------------------------------------- + +Done fairly simply by using fusee-tools (using run_bootloader.sh) and placing +``u-boot-dtb-tegra.bin`` generated on the previous step into fusee-tools dir. +This method requires constant access to the host PC or payloader and can fully +eliminate influence of the vendor bootloader onto the boot process. + +.. code-block:: bash + + $ ./run_bootloader.sh -s T114 -t ./bct/tf701t.bct + +Chainloading U-Boot from the vendor bootloader +---------------------------------------------- + +``u-boot-dtb.bin`` has to be further packed into Android boot image form, +where ``u-boot-dtb.bin`` acts as kernel, while dtb and ramdisk parts should +not be included. Then the generated boot image can be flashed into the /boot +partition of the tablet using vendor bootloader's fastboot and will act as +the bootloader of the last stage. + +Boot +---- +In both cases after U-Boot obtains control it performs search of extlinux.conf +first on the dock USB device is available, then on MicroSD card if available +and lastly on eMMC. If none of the devices above are present, then the device +is turned off. + +If during boot of U-Boot Volume Down button is pressed, the device will enter +U-Boot bootmenu. diff --git a/include/configs/transformer-t114.h b/include/configs/transformer-t114.h new file mode 100644 index 00000000000..2fbf3417691 --- /dev/null +++ b/include/configs/transformer-t114.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2023, Svyatoslav Ryhel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra114-common.h" + +#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE + #define CFG_PRAM 0x20000 /* 128 MB */ +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ From b12931d7dedd4130b2e795525431b60ffac6541f Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Thu, 29 Jun 2023 10:10:26 +0300 Subject: [PATCH 23/24] board: nvidia: tegratab: add Nvidia Tegra Note 7 support The Tegra Note 7 is a mini tablet computer and the second Tegra 4 based mobile device designed by Nvidia that runs the Android operating system. The Tegra Note has a 7" IPS display with 1280 x 800 (217 ppi) resolution. The 1 GB of RAM and 16 GB of internal memory can be supplemented with a microSDXC card giving up to 64 GB of additional storage. Signed-off-by: Svyatoslav Ryhel --- arch/arm/dts/Makefile | 1 + arch/arm/dts/tegra114-nvidia-tegratab.dts | 1041 +++++++++++++++++++++ arch/arm/mach-tegra/tegra114/Kconfig | 5 + board/nvidia/tegratab/Kconfig | 16 + board/nvidia/tegratab/MAINTAINERS | 8 + board/nvidia/tegratab/Makefile | 10 + board/nvidia/tegratab/tegratab-spl.c | 42 + board/nvidia/tegratab/tegratab.c | 56 ++ board/nvidia/tegratab/tegratab.env | 15 + configs/tegratab_defconfig | 84 ++ doc/board/index.rst | 1 + doc/board/nvidia/index.rst | 9 + doc/board/nvidia/tegratab.rst | 74 ++ include/configs/tegratab.h | 19 + 14 files changed, 1381 insertions(+) create mode 100644 arch/arm/dts/tegra114-nvidia-tegratab.dts create mode 100644 board/nvidia/tegratab/Kconfig create mode 100644 board/nvidia/tegratab/MAINTAINERS create mode 100644 board/nvidia/tegratab/Makefile create mode 100644 board/nvidia/tegratab/tegratab-spl.c create mode 100644 board/nvidia/tegratab/tegratab.c create mode 100644 board/nvidia/tegratab/tegratab.env create mode 100644 configs/tegratab_defconfig create mode 100644 doc/board/nvidia/index.rst create mode 100644 doc/board/nvidia/tegratab.rst create mode 100644 include/configs/tegratab.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c0bae4dd9e2..57d3dd98ffb 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -120,6 +120,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-wexler-qc750.dtb \ tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ + tegra114-nvidia-tegratab.dtb \ tegra124-apalis.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ diff --git a/arch/arm/dts/tegra114-nvidia-tegratab.dts b/arch/arm/dts/tegra114-nvidia-tegratab.dts new file mode 100644 index 00000000000..f65772a8e01 --- /dev/null +++ b/arch/arm/dts/tegra114-nvidia-tegratab.dts @@ -0,0 +1,1041 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "tegra114.dtsi" + +/ { + model = "NVIDIA Tegra Note 7"; + compatible = "nvidia,tegratab", "nvidia,tegra114"; + + chosen { + stdout-path = &uartd; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + nvidia,180-rotation; + }; + + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel@0 { + compatible = "lg,ld070wx3-sl01"; + reg = <0>; + + vdd-supply = <&avdd_3v3_lcd>; + vcc-supply = <&dvdd_1v8_lcd>; + + backlight = <&backlight>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* ULPI pinmux */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data5_po6", + "ulpi_data6_po7", + "ulpi_data7_po0"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-data3 { + nvidia,pins = "ulpi_data3_po4", + "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SPI1 pinmux */ + ulpi-clk { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ulpi-dir { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* I2S pinmux */ + dap1-pins { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-dout { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap2-din { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap3-fs-pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-din { + nvidia,pins = "dap4_din_pp5"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + dap4-dout { + nvidia,pins = "dap4_fs_pp4", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC1 pinmux */ + sdmmc1-clk { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc1-wp-n { + nvidia,pins = "sdmmc1_wp_n_pv3"; + nvidia,function = "sdmmc1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc3-clk-lb { + nvidia,pins = "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + sdmmc4-cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* EXTPERIPH pinmux */ + clk1-req { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk1-out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-req { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk2-out { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-req-pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk3-out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + dvfs-pinmux { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* HDMI pinmux */ + hdmi-irq { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + hdmi-cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* UARTA pinmux */ + uarta-out { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uarta-in { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UARTB pinmux */ + uart2-cts-rts { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UARTC pinmux */ + uart3-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uart3-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* UARTD pinmux */ + gmi-a17 { + nvidia,pins = "gmi_a17_pb0"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-a18 { + nvidia,pins = "gmi_a18_pb1"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + uartd-out { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "uartd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* PORT U */ + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu1-2 { + nvidia,pins = "pu1", "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "pwm0"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* GMI section */ + gmi-wp-n-pc7 { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_adv_n_pk0", + "gmi_cs0_n_pj0", + "gmi_wr_n_pi0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-iordy-pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-wait-pi7 { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-clk-pk1 { + nvidia,pins = "gmi_clk_pk1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6", + "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs2-n-pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs4-n-pk2 { + nvidia,pins = "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs6-n-pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-cs7-n-pi6 { + nvidia,pins = "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad0-pg0 { + nvidia,pins = "gmi_ad0_pg0"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad1-pg1 { + nvidia,pins = "gmi_ad1_pg1", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad2-pg2 { + nvidia,pins = "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_oe_n_pi1"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad8-ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad9 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad12-ph4 { + nvidia,pins = "gmi_ad12_ph4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad13-ph5 { + nvidia,pins = "gmi_ad13_ph5"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-ad15-ph7 { + nvidia,pins = "gmi_ad15_ph7"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-dqs-p-pj3 { + nvidia,pins = "gmi_dqs_p_pj3"; + nvidia,function = "nand"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-rst-n-pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gmi-clk-lb { + nvidia,pins = "gmi_clk_lb"; + nvidia,function = "gmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* VI_ALT3 pinmux */ + cam-mclk { + nvidia,pins = "pbb0", "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + port-bb { + nvidia,pins = "pbb3", "pbb4", "pbb5", + "pbb6", "pbb7"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + port-cc { + nvidia,pins = "pcc1", "pcc2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + jtag-rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* KBC pinmux */ + kb-row0-pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row2-pr2 { + nvidia,pins = "kb_row2_pr2", + "kb_col0_pq0"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row3-pr3 { + nvidia,pins = "kb_row3_pr3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row4-pr4 { + nvidia,pins = "kb_row4_pr4", + "kb_row5_pr5", + "kb_row6_pr6", + "kb_col3_pq3", + "kb_col4_pq4"; + nvidia,function = "kbc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row7-pr7 { + nvidia,pins = "kb_row7_pr7", + "kb_col2_pq2", + "kb_col5_pq5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + kb-row8-ps0 { + nvidia,pins = "kb_row8_ps0", + "kb_col1_pq1", + "kb_col6_pq6", + "kb_col7_pq7"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* CORE pinmux */ + sys-clk-req { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk-32k-out { + nvidia,pins = "clk_32k_out_pa0", + "gmi_cs1_n_pj2"; + nvidia,function = "soc"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,rcv-sel = ; + }; + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + /* AUD pinmux */ + gpio-x1-aud-px1 { + nvidia,pins = "gpio_x1_aud_px1"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x3-aud-px3 { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x4-aud-px4 { + nvidia,pins = "gpio_x4_aud_px4", + "gpio_x5_aud_px5", + "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-x6-aud-px6 { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "rsvd4"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-w2-aud-pw2 { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + gpio-w3-aud-pw3 { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + + usb-vbus-en { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "rsvd2"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; + }; + + /* GPIO power/drive control */ + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive-sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + drive-gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <2>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + }; + }; + + uartd: serial@70006300 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + }; + }; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + avdd_3v3_lcd: smps6 { + regulator-name = "vdd_lcd_hv"; + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + regulator-boot-on; + }; + + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vcore_emmc: smps9 { + regulator-name = "vdd_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_dsi_csi: ldo2 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_sdmmc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + + avdd_usb: ldousb { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + pwms = <&pwm 1 1000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-hall-sensor { + label = "Hall Sensor"; + gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + dvdd_1v8_lcd: regulator-lcdvio { + compatible = "regulator-fixed"; + regulator-name = "dvdd_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index fb88696ae41..98f1d0e71c1 100644 --- a/arch/arm/mach-tegra/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig @@ -8,6 +8,10 @@ config TARGET_DALMORE bool "NVIDIA Tegra114 Dalmore evaluation board" select BOARD_LATE_INIT +config TARGET_TEGRATAB + bool "NVIDIA Tegra114 TegraTab evaluation board" + select BOARD_LATE_INIT + config TARGET_TRANSFORMER_T114 bool "ASUS Tegra114 Transformer board" select BOARD_LATE_INIT @@ -18,6 +22,7 @@ config SYS_SOC default "tegra114" source "board/nvidia/dalmore/Kconfig" +source "board/nvidia/tegratab/Kconfig" source "board/asus/transformer-t114/Kconfig" endif diff --git a/board/nvidia/tegratab/Kconfig b/board/nvidia/tegratab/Kconfig new file mode 100644 index 00000000000..8bd7cfd87b8 --- /dev/null +++ b/board/nvidia/tegratab/Kconfig @@ -0,0 +1,16 @@ +if TARGET_TEGRATAB + +config SYS_BOARD + default "tegratab" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "tegratab" + +config TEGRA_BOARD_STRING + string "Default Tegra board name" + default "NVIDIA TegraTab" + +endif diff --git a/board/nvidia/tegratab/MAINTAINERS b/board/nvidia/tegratab/MAINTAINERS new file mode 100644 index 00000000000..bfd9eae8658 --- /dev/null +++ b/board/nvidia/tegratab/MAINTAINERS @@ -0,0 +1,8 @@ +TEGRATAB BOARD +M: Svyatoslav Ryhel +S: Maintained +F: arch/arm/dts/tegra114-nvidia-tegratab.dts +F: board/nvidia/tegratab/ +F: configs/tegratab_defconfig +F: doc/board/nvidia/tegratab.rst +F: include/configs/tegratab.h diff --git a/board/nvidia/tegratab/Makefile b/board/nvidia/tegratab/Makefile new file mode 100644 index 00000000000..183a0ba0319 --- /dev/null +++ b/board/nvidia/tegratab/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. +# +# Copyright (c) 2023, Svyatoslav Ryhel +# + +obj-$(CONFIG_XPL_BUILD) += tegratab-spl.o + +obj-y += tegratab.o diff --git a/board/nvidia/tegratab/tegratab-spl.c b/board/nvidia/tegratab/tegratab-spl.c new file mode 100644 index 00000000000..423b3070910 --- /dev/null +++ b/board/nvidia/tegratab/tegratab-spl.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TegraTab SPL stage configuration + * + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +#include +#include +#include + +#define TPS65913_I2C_ADDR (0x58 << 1) + +#define TPS65913_SMPS12_CTRL 0x20 +#define TPS65913_SMPS12_VOLTAGE 0x23 +#define TPS65913_SMPS45_CTRL 0x28 +#define TPS65913_SMPS45_VOLTAGE 0x2B + +#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL) +#define TPS65913_SMPS12_VOLTAGE_DATA (0x3900 | TPS65913_SMPS12_VOLTAGE) +#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL) +#define TPS65913_SMPS45_VOLTAGE_DATA (0x4c00 | TPS65913_SMPS45_VOLTAGE) + +void pmic_enable_cpu_vdd(void) +{ + /* Set CORE VDD to 1.200V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA); + + udelay(1000); + + /* Set CPU VDD to 1.0125V. */ + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA); + udelay(1000); + tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA); + udelay(10 * 1000); +} diff --git a/board/nvidia/tegratab/tegratab.c b/board/nvidia/tegratab/tegratab.c new file mode 100644 index 00000000000..775e5be9cfa --- /dev/null +++ b/board/nvidia/tegratab/tegratab.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2010-2013 + * NVIDIA Corporation + * + * (C) Copyright 2023 + * Svyatoslav Ryhel + */ + +#include +#include +#include +#include + +#ifdef CONFIG_MMC_SDHCI_TEGRA + +#define TPS65913_I2C_ADDRESS 0x58 +#define TPS65913_PRIMARY_SECONDARY_PAD2 0xfb +#define GPIO_4 BIT(0) +#define TPS65913_PRIMARY_SECONDARY_PAD3 0xfe +#define DVFS2 BIT(1) +#define DVFS1 BIT(0) + +/* We are using this function only till palmas pinctrl driver is available */ +void pin_mux_mmc(void) +{ + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(0, TPS65913_I2C_ADDRESS, 1, &dev); + if (ret) { + log_debug("%s: cannot find PMIC I2C chip\n", __func__); + return; + } + + /* GPIO4 function has to be GPIO */ + dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD2, + GPIO_4, 0); + + /* DVFS1 is enabled, DVFS2 is disabled */ + dm_i2c_reg_clrset(dev, TPS65913_PRIMARY_SECONDARY_PAD3, + DVFS2 | DVFS1, DVFS1); +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* Remove TrustZone nodes and memory reserves */ + fdt_del_node_and_alias(blob, "/firmware"); + fdt_del_node_and_alias(blob, "/reserved-memory/trustzone@bfe00000"); + fdt_del_node_and_alias(blob, "/reserved-memory/bootloader-firmware@b7e00000"); + + return 0; +} +#endif diff --git a/board/nvidia/tegratab/tegratab.env b/board/nvidia/tegratab/tegratab.env new file mode 100644 index 00000000000..b2ba4f4354c --- /dev/null +++ b/board/nvidia/tegratab/tegratab.env @@ -0,0 +1,15 @@ +button_cmd_0_name=Volume Down +button_cmd_0=bootmenu +button_cmd_1_name=Hall Sensor +button_cmd_1=poweroff + +fastboot_partition_alias_boot=CAC +fastboot_partition_alias_root=UDA + +bootmenu_0=mount internal storage=usb start && ums 0 mmc 0:c; bootmenu +bootmenu_1=mount external storage=usb start && ums 0 mmc 1; bootmenu +bootmenu_2=fastboot=echo Starting Fastboot protocol ...; fastboot usb 0; bootmenu +bootmenu_3=reboot RCM=enterrcm +bootmenu_4=reboot=reset +bootmenu_5=power off=poweroff +bootmenu_delay=-1 diff --git a/configs/tegratab_defconfig b/configs/tegratab_defconfig new file mode 100644 index 00000000000..f0f83218ba5 --- /dev/null +++ b/configs/tegratab_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_ARCH_TEGRA=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_TEXT_BASE=0x80110000 +CONFIG_SYS_MALLOC_LEN=0x2500000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SOURCE_FILE="tegratab" +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xFFFFD000 +CONFIG_DEFAULT_DEVICE_TREE="tegra114-nvidia-tegratab" +CONFIG_SPL_STACK=0x800ffffc +CONFIG_SPL_TEXT_BASE=0x80108000 +CONFIG_SYS_LOAD_ADDR=0x82000000 +CONFIG_TEGRA114=y +CONFIG_TARGET_TEGRATAB=y +CONFIG_TEGRA_ENABLE_UARTD=y +CONFIG_BUTTON_CMD=y +CONFIG_BOOTDELAY=0 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan; echo 'Boot configuration not found... Power off in 3 sec'; sleep 3; poweroff" +CONFIG_SYS_PBSIZE=2086 +CONFIG_SPL_FOOTPRINT_LIMIT=y +CONFIG_SPL_MAX_FOOTPRINT=0x8000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80090000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x10000 +CONFIG_SYS_PROMPT="Tegra114 (TegraTab) # " +# CONFIG_CMD_BOOTEFI_BOOTMGR is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_UMS_ABORT_KEYED=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PAUSE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_TEGRA_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_PALMAS_GPIO=y +CONFIG_SYS_I2C_TEGRA=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_PALMAS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_PALMAS=y +CONFIG_PWM_TEGRA=y +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET_PALMAS=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_TEGRA=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_LOGO is not set +CONFIG_VIDEO_LCD_LG_LD070WX3=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_DSI_TEGRA=y diff --git a/doc/board/index.rst b/doc/board/index.rst index 9ce436af5f9..3c5a2c7d1cf 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc microchip/index microsoft/index motorola/index + nvidia/index nxp/index openpiton/index ouya/index diff --git a/doc/board/nvidia/index.rst b/doc/board/nvidia/index.rst new file mode 100644 index 00000000000..7c105445559 --- /dev/null +++ b/doc/board/nvidia/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +NVIDIA +====== + +.. toctree:: + :maxdepth: 2 + + tegratab diff --git a/doc/board/nvidia/tegratab.rst b/doc/board/nvidia/tegratab.rst new file mode 100644 index 00000000000..c6d97ce3828 --- /dev/null +++ b/doc/board/nvidia/tegratab.rst @@ -0,0 +1,74 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Nvidia Tegra Note 7 +================================== + +Quick Start +----------- + +- Build U-Boot +- Boot U-Boot by loading it into RAM (coldboot) +- Chainloading U-Boot from the vendor bootloader +- Boot + +Build U-Boot +------------ + +U-Boot can be built in two forms: U-Boot with SPL, which is used for booting +by loading directly into RAM and U-Boot without SPL, which can be flashed +and chainloaded from the vendor bootloader. + +To build U-Boot with SPL proseed: + +.. code-block:: bash + + $ export CROSS_COMPILE=arm-none-eabi- + $ make tegratab_defconfig + $ make + +After the build succeeds, you will obtain the final ``u-boot-dtb-tegra.bin`` +file, ready for cold booting by loading into RAM. + +To build U-Boot without SPL adjust tegratab_defconfig: + +.. code-block:: + + CONFIG_TEXT_BASE=0x80A00000 + CONFIG_SKIP_LOWLEVEL_INIT=y + # CONFIG_OF_BOARD_SETUP is not set + CONFIG_TEGRA_SUPPORT_NON_SECURE=y + +After the build succeeds, you will obtain the final ``u-boot-dtb.bin`` file, +ready for booting with fastboot boot or which can be further processed into +a flashable boot.img. + +Boot U-Boot by loading it into RAM (coldboot) +--------------------------------------------- + +Done fairly simply by using fusee-tools (using run_bootloader.sh) and placing +``u-boot-dtb-tegra.bin`` generated on the previous step into fusee-tools dir. +This method requires constant access to the host PC or payloader and can fully +eliminate influence of the vendor bootloader onto the boot process. + +.. code-block:: bash + + $ ./run_bootloader.sh -s T114 -t ./bct/tegratab.bct + +Chainloading U-Boot from the vendor bootloader +---------------------------------------------- + +``u-boot-dtb.bin`` has to be further packed into Android boot image form, +where ``u-boot-dtb.bin`` acts as kernel, while dtb and ramdisk parts should +not be included. Then the generated boot image can be flashed into the /boot +partition of the tablet using vendor bootloader's fastboot and will act as +the bootloader of the last stage. + +Boot +---- +In both cases after U-Boot obtains control it performs search of extlinux.conf +first on the dock USB device is available, then on MicroSD card if available +and lastly on eMMC. If none of the devices above are present, then the device +is turned off. + +If during boot of U-Boot Volume Down button is pressed, the device will enter +U-Boot bootmenu. diff --git a/include/configs/tegratab.h b/include/configs/tegratab.h new file mode 100644 index 00000000000..afab01ec09c --- /dev/null +++ b/include/configs/tegratab.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * Copyright (c) 2023, Svyatoslav Ryhel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "tegra114-common.h" + +#ifdef CONFIG_TEGRA_SUPPORT_NON_SECURE + #define CFG_PRAM 0x21c00 /* 135 MB */ +#endif + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ From 427dd4dd27eef00306a94800d66a6b82e2b11ad8 Mon Sep 17 00:00:00 2001 From: Artur Kowalski Date: Sun, 30 Mar 2025 21:26:39 +0200 Subject: [PATCH 24/24] ARM: tegra20: add funcmux for exposing UART over uSD slot on Tegra 20 UART-A can be exposed through uSD, this was tested on Transformer T20 but should work on all Ventana-based boards. TX is exported on SDD pingroup corresponding to uSD CLK pin RX is exported on SDB which is CMD pin in uSD slot Signed-off-by: Artur Kowalski Reviewed-by: Svyatoslav Ryhel Signed-off-by: Svyatoslav Ryhel --- arch/arm/include/asm/arch-tegra20/funcmux.h | 1 + arch/arm/mach-tegra/board.c | 2 ++ arch/arm/mach-tegra/tegra20/Kconfig | 3 +++ drivers/pinctrl/tegra/funcmux-tegra20.c | 9 ++++++++- 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-tegra20/funcmux.h b/arch/arm/include/asm/arch-tegra20/funcmux.h index e9e96c1f933..bafcf857620 100644 --- a/arch/arm/include/asm/arch-tegra20/funcmux.h +++ b/arch/arm/include/asm/arch-tegra20/funcmux.h @@ -19,6 +19,7 @@ enum { FUNCMUX_UART1_UAA_UAB, FUNCMUX_UART1_GPU, FUNCMUX_UART1_SDIO1, + FUNCMUX_UART1_SDB_SDD, FUNCMUX_UART2_UAD = 0, FUNCMUX_UART4_GMC = 0, diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c index 8c946f0f117..4835824f724 100644 --- a/arch/arm/mach-tegra/board.c +++ b/arch/arm/mach-tegra/board.c @@ -169,6 +169,8 @@ static int uart_configs[] = { FUNCMUX_UART1_GPU, #elif defined(CONFIG_TEGRA_UARTA_SDIO1) FUNCMUX_UART1_SDIO1, + #elif defined(CONFIG_TEGRA_UARTA_SDB_SDD) + FUNCMUX_UART1_SDB_SDD, #else FUNCMUX_UART1_IRRX_IRTX, #endif diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index 63678376840..a79fdc25650 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -17,6 +17,9 @@ config TEGRA_UARTA_GPU config TEGRA_UARTA_SDIO1 bool +config TEGRA_UARTA_SDB_SDD + bool + choice prompt "Tegra20 board select" optional diff --git a/drivers/pinctrl/tegra/funcmux-tegra20.c b/drivers/pinctrl/tegra/funcmux-tegra20.c index 951ae196161..f60d5aad3a4 100644 --- a/drivers/pinctrl/tegra/funcmux-tegra20.c +++ b/drivers/pinctrl/tegra/funcmux-tegra20.c @@ -62,8 +62,15 @@ int funcmux_select(enum periph_id id, int config) pinmux_tristate_disable(PMUX_PINGRP_SDIO1); bad_config = 0; break; + case FUNCMUX_UART1_SDB_SDD: + pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_UARTA); + pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_UARTA); + pinmux_tristate_disable(PMUX_PINGRP_SDB); + pinmux_tristate_disable(PMUX_PINGRP_SDD); + bad_config = 0; + break; } - if (!bad_config) { + if (!bad_config && config != FUNCMUX_UART1_SDB_SDD) { /* * Tegra appears to boot with function UARTA pre- * selected on mux group SDB. If two mux groups are