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sunxi: Remove non-DM GMAC pin setup

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This is now handled automatically by the pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Samuel Holland
2021-08-28 13:16:44 -05:00
committed by Andre Przywara
parent 7a93644c69
commit 3e42d919af
2 changed files with 0 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/include/asm/arch-sunxi/gpio.h
View File

@@ -135,8 +135,6 @@ enum sunxi_gpio_number {
#define SUNXI_GPIO_OUTPUT 1 #define SUNXI_GPIO_OUTPUT 1
#define SUNXI_GPIO_DISABLE 7 #define SUNXI_GPIO_DISABLE 7
#define SUN6I_GPA_GMAC 2
#define SUN7I_GPA_GMAC 5
#define SUN8I_H3_GPA_UART0 2 #define SUN8I_H3_GPA_UART0 2
#define SUN4I_GPB_PWM 2 #define SUN4I_GPB_PWM 2

55
board/sunxi/gmac.c
View File

@@ -1,13 +1,11 @@
#include <common.h> #include <common.h>
#include <netdev.h> #include <netdev.h>
#include <miiphy.h> #include <miiphy.h>
#include <asm/gpio.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
void eth_init_board(void) void eth_init_board(void)
{ {
int pin;
struct sunxi_ccm_reg *const ccm = struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
@@ -21,57 +19,4 @@ void eth_init_board(void)
setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
CCM_GMAC_CTRL_GPIT_MII); CCM_GMAC_CTRL_GPIT_MII);
#endif #endif
#ifndef CONFIG_MACH_SUN6I
/* Configure pin mux settings for GMAC */
#ifdef CONFIG_SUN7I_GMAC_FORCE_TXERR
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
#else
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
#endif
#ifdef CONFIG_RGMII
/* skip unused pins in RGMII mode */
if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
continue;
#endif
sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
#elif defined CONFIG_RGMII
/* Configure sun6i RGMII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 3);
}
#elif defined CONFIG_GMII
/* Configure sun6i GMII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
sunxi_gpio_set_drv(pin, 2);
}
#else
/* Configure sun6i MII mode pin mux settings */
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)
sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);
#endif
} }