From 0c3eec2aea8fba147c9eee48577f1dcab57c1174 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 23 Sep 2022 12:05:51 -0400 Subject: [PATCH 1/6] arm64: ls104x: Enable eDMA snooping This enables eDMA snooping on the LS1043A and LS1046A. This will allow marking the I2C, LPUART, and SPI devices on these SoCs as DMA coherent. Oddly, this bit is only documented for the LS1043A, and is marked as "reserved" in the LS1046ARM. I have tested this patch on the LS1046A and found that marking i2c0 as dma-coherent works without issue. Signed-off-by: Sean Anderson Acked-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 926f8f21b63..515dbe02fd7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -682,7 +682,7 @@ void fsl_lsch2_early_init_f(void) SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP | SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP | SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP | - SCFG_SNPCNFGCR_SATAWRSNP); + SCFG_SNPCNFGCR_SATAWRSNP | SCFG_SNPCNFGCR_EDMASNP); #elif defined(CONFIG_ARCH_LS1012A) setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP | diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 1fb1191a65e..2b73647ab4a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -383,6 +383,7 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 #define SCFG_SNPCNFGCR_USB1RDSNP 0x00200000 #define SCFG_SNPCNFGCR_USB1WRSNP 0x00100000 +#define SCFG_SNPCNFGCR_EDMASNP 0x00020000 #define SCFG_SNPCNFGCR_USB2RDSNP 0x00008000 #define SCFG_SNPCNFGCR_USB2WRSNP 0x00010000 #define SCFG_SNPCNFGCR_USB3RDSNP 0x00002000 From e6b719af9a1174038a60f5918624befe80eac847 Mon Sep 17 00:00:00 2001 From: Wei Lu Date: Mon, 26 Sep 2022 16:18:49 +0800 Subject: [PATCH 2/6] ls1043ardb: nand driver fixups for revision v7.0 boards The LS1043ARDB rev v7.0 board replace nand device MT29F4G08ABBDAH4-AITX:D with MT29F4G08ABBFAH4-AIT:F. Reflecting this change in board_fix_fdt(). CPLD V3.0 is needed for nandboot as the nand device changed. A new macro CPLD_CFG_RCW_SRC_NAND_4K(4Kpage) is added to distinguish from CPLD_CFG_RCW_SRC_NAND(2Kpage) to support nandboot on rev v7.0 board. Signed-off-by: Wei Lu Signed-off-by: Peng Fan --- board/freescale/ls1043ardb/cpld.c | 4 +++ board/freescale/ls1043ardb/cpld.h | 1 + board/freescale/ls1043ardb/ls1043ardb.c | 46 ++++++++++++++++++++++++- 3 files changed, 50 insertions(+), 1 deletion(-) diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 5d2e8015a05..232035638b3 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -69,6 +69,10 @@ void cpld_set_defbank(void) void cpld_set_nand(void) { u16 reg = CPLD_CFG_RCW_SRC_NAND; + + if (CPLD_READ(cpld_ver) > 0x2) + reg = CPLD_CFG_RCW_SRC_NAND_4K; + u8 reg5 = (u8)(reg >> 1); u8 reg6 = (u8)(reg & 1); diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index 2e757b557f4..eed34d63546 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -41,5 +41,6 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_BANK_SEL_ALTBANK 0x04 #define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 +#define CPLD_CFG_RCW_SRC_NAND_4K 0x118 #define CPLD_CFG_RCW_SRC_SD 0x040 #endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index f388eb496f4..8c91f0771fb 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -167,7 +167,7 @@ int checkboard(void) if (cfg_rcw_src == 0x25) printf("vBank %d\n", CPLD_READ(vbank)); - else if (cfg_rcw_src == 0x106) + else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118)) puts("NAND\n"); else printf("Invalid setting of SW4\n"); @@ -347,10 +347,54 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } +void nand_fixup(void) +{ + u32 csor = 0; + + if (CPLD_READ(pcba_ver) < 0x7) + return; + + /* Change NAND Flash PGS/SPRZ configuration */ + csor = CONFIG_SYS_NAND_CSOR; + if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) + csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K; + + if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64) + csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224; + + if (IS_ENABLED(CONFIG_TFABOOT)) { + u8 cfg_rcw_src1, cfg_rcw_src2; + u16 cfg_rcw_src; + + cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); + cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); + cpld_rev_bit(&cfg_rcw_src1); + cfg_rcw_src = cfg_rcw_src1; + cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; + + if (cfg_rcw_src == 0x25) + set_ifc_csor(IFC_CS1, csor); + else if (cfg_rcw_src == 0x118) + set_ifc_csor(IFC_CS0, csor); + else + printf("Invalid setting\n"); + } else { + if (IS_ENABLED(CONFIG_NAND_BOOT)) + set_ifc_csor(IFC_CS0, csor); + else + set_ifc_csor(IFC_CS1, csor); + } +} + #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) int board_fix_fdt(void *blob) { + /* nand driver fix up */ + nand_fixup(); + + /* fdt fix up */ fdt_fixup_phy_addr(blob); + return 0; } #endif From 8fd111351ce61106c14bcf7efa9af9724c9dd92f Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 26 Sep 2022 12:47:37 -0400 Subject: [PATCH 3/6] arm64: layerscape: Support SYSRESET CONFIG_SYSRESET provides its own implementation of reset_cpu. Disable our version when it is enabled. Signed-off-by: Sean Anderson Signed-off-by: Peng Fan --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c989a43cbeb..487c0ed5539 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1229,6 +1229,7 @@ int timer_init(void) return 0; } +#if !CONFIG_IS_ENABLED(SYSRESET) __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; void __efi_runtime reset_cpu(void) @@ -1248,6 +1249,7 @@ void __efi_runtime reset_cpu(void) scfg_out32(rstcr, val); #endif } +#endif #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET) From 3d970cb264ba2dd9b84fa689b397cd93ac939ac9 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 17 Oct 2022 11:45:10 -0400 Subject: [PATCH 4/6] arm: layerscape: Don't select FSL_IFC when booting from SD card FSL_IFC should only be selected when booting from NAND flash (or when NAND_FSL_IFC is enabled). The existing logic does this correctly when QSPI is also enabled, but not when just booting from SD. Signed-off-by: Sean Anderson Signed-off-by: Peng Fan --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 8a7bbb4a655..ebca11d1741 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -63,7 +63,7 @@ config ARCH_LS1043A bool select ARMV8_SET_SMPEN select ARM_ERRATA_855873 if !TFABOOT - select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI) + select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT) select FSL_LAYERSCAPE select FSL_LSCH2 select GICV2 @@ -100,7 +100,7 @@ config ARCH_LS1043A config ARCH_LS1046A bool select ARMV8_SET_SMPEN - select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI) + select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI && !SD_BOOT) select FSL_LAYERSCAPE select FSL_LSCH2 select GICV2 From 3ed84e73fb59c592c4cdfe3b56cce5cecf30a7da Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 17 Oct 2022 11:45:11 -0400 Subject: [PATCH 5/6] arm: layerscape: Disable unused parts of ICID tables Several parts of the ICID table are only necessary for U-Boot proper. Disable them in SPL. This saves around 500 bytes. Signed-off-by: Sean Anderson Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 2 ++ .../include/asm/arch-fsl-layerscape/fsl_icid.h | 16 ++++++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index 25cd82f16eb..2d87281ec21 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -46,6 +46,7 @@ void set_icids(void) #endif } +#ifndef CONFIG_SPL_BUILD int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids) { int i, ret; @@ -190,3 +191,4 @@ void fdt_fixup_icid(void *blob) fdt_fixup_fman_icids(blob, smmu_ph); #endif } +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 3c06a55cb85..8af0d35d27b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -12,11 +12,15 @@ #include struct icid_id_table { +#ifndef CONFIG_SPL_BUILD const char *compat; - u32 id; - u32 reg; phys_addr_t compat_addr; +#endif phys_addr_t reg_addr; + u32 reg; +#ifndef CONFIG_SPL_BUILD + u32 id; +#endif bool le; }; @@ -31,6 +35,13 @@ int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids); void set_icids(void); void fdt_fixup_icid(void *blob); +#ifdef CONFIG_SPL_BUILD +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \ + { .reg = regA, \ + .reg_addr = addr, \ + .le = _le \ + } +#else #define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \ { .compat = name, \ .id = idA, \ @@ -39,6 +50,7 @@ void fdt_fixup_icid(void *blob); .reg_addr = addr, \ .le = _le \ } +#endif #ifdef CONFIG_SYS_FSL_SEC_LE #define SEC_IS_LE true From c4f0de3eecd951cd5480cdbc9d96c63a4432a521 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 17 Oct 2022 11:45:12 -0400 Subject: [PATCH 6/6] arm: fsl: csu: Reduce size of ns_dev None of the values in this struct are larger than 256, so we can reduce the members to u8s. This saves around 1K. Signed-off-by: Sean Anderson Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- include/fsl_csu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/fsl_csu.h b/include/fsl_csu.h index 0e59ac3c324..40c29687979 100644 --- a/include/fsl_csu.h +++ b/include/fsl_csu.h @@ -24,8 +24,8 @@ enum csu_cslx_access { }; struct csu_ns_dev { - unsigned long ind; - uint32_t val; + u8 ind; + u8 val; }; void enable_layerscape_ns_access(void);