odroid-c2: enable I2C
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
This commit is contained in:

committed by
Heiko Schocher

parent
f8d9ca1833
commit
456efb5127
@@ -47,6 +47,7 @@
|
|||||||
#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53)
|
#define GXBB_GCLK_MPEG_OTHER GXBB_HIU_ADDR(0x53)
|
||||||
#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54)
|
#define GXBB_GCLK_MPEG_AO GXBB_HIU_ADDR(0x54)
|
||||||
|
|
||||||
|
#define GXBB_GCLK_MPEG_0_I2C BIT(9)
|
||||||
#define GXBB_GCLK_MPEG_1_ETH BIT(3)
|
#define GXBB_GCLK_MPEG_1_ETH BIT(3)
|
||||||
|
|
||||||
#endif /* __GXBB_H__ */
|
#endif /* __GXBB_H__ */
|
||||||
|
@@ -35,6 +35,7 @@ int misc_init_r(void)
|
|||||||
GXBB_ETH_REG_0_CLK_EN);
|
GXBB_ETH_REG_0_CLK_EN);
|
||||||
|
|
||||||
/* Enable power and clock gate */
|
/* Enable power and clock gate */
|
||||||
|
setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C);
|
||||||
setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
|
setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
|
||||||
clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
|
clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
|
||||||
|
|
||||||
|
@@ -11,12 +11,15 @@ CONFIG_DEBUG_UART=y
|
|||||||
# CONFIG_CMD_IMI is not set
|
# CONFIG_CMD_IMI is not set
|
||||||
# CONFIG_CMD_FPGA is not set
|
# CONFIG_CMD_FPGA is not set
|
||||||
CONFIG_CMD_GPIO=y
|
CONFIG_CMD_GPIO=y
|
||||||
|
CONFIG_CMD_I2C=y
|
||||||
# CONFIG_CMD_LOADS is not set
|
# CONFIG_CMD_LOADS is not set
|
||||||
CONFIG_CMD_MMC=y
|
CONFIG_CMD_MMC=y
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
CONFIG_OF_CONTROL=y
|
CONFIG_OF_CONTROL=y
|
||||||
CONFIG_NET_RANDOM_ETHADDR=y
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
CONFIG_DM_GPIO=y
|
CONFIG_DM_GPIO=y
|
||||||
|
CONFIG_DM_I2C=y
|
||||||
|
CONFIG_SYS_I2C_MESON=y
|
||||||
CONFIG_DM_MMC=y
|
CONFIG_DM_MMC=y
|
||||||
CONFIG_MMC_MESON_GX=y
|
CONFIG_MMC_MESON_GX=y
|
||||||
CONFIG_DM_ETH=y
|
CONFIG_DM_ETH=y
|
||||||
|
Reference in New Issue
Block a user