Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
17
arch/arm/include/asm/arch-exynos/board.h
Normal file
17
arch/arm/include/asm/arch-exynos/board.h
Normal file
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* (C) Copyright 2013 Samsung Electronics
|
||||
* Rajeshwari Shinde <rajeshwari.s@samsung.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _EXYNOS_BOARD_H
|
||||
#define _EXYNOS_BOARD_H
|
||||
|
||||
/*
|
||||
* Exynos baord specific changes for
|
||||
* board_init
|
||||
*/
|
||||
int exynos_init(void);
|
||||
|
||||
#endif /* EXYNOS_BOARD_H */
|
||||
@@ -14,6 +14,7 @@
|
||||
#define HPLL 3
|
||||
#define VPLL 4
|
||||
#define BPLL 5
|
||||
#define RPLL 6
|
||||
|
||||
enum pll_src_bit {
|
||||
EXYNOS_SRC_MPLL = 6,
|
||||
|
||||
@@ -858,6 +858,500 @@ struct exynos5_clock {
|
||||
unsigned char res123[0xf5d8];
|
||||
};
|
||||
|
||||
struct exynos5420_clock {
|
||||
unsigned int apll_lock; /* 0x10010000 */
|
||||
unsigned char res1[0xfc];
|
||||
unsigned int apll_con0;
|
||||
unsigned int apll_con1;
|
||||
unsigned char res2[0xf8];
|
||||
unsigned int src_cpu;
|
||||
unsigned char res3[0x1fc];
|
||||
unsigned int mux_stat_cpu;
|
||||
unsigned char res4[0xfc];
|
||||
unsigned int div_cpu0; /* 0x10010500 */
|
||||
unsigned int div_cpu1;
|
||||
unsigned char res5[0xf8];
|
||||
unsigned int div_stat_cpu0;
|
||||
unsigned int div_stat_cpu1;
|
||||
unsigned char res6[0xf8];
|
||||
unsigned int gate_bus_cpu;
|
||||
unsigned char res7[0xfc];
|
||||
unsigned int gate_sclk_cpu;
|
||||
unsigned char res8[0x1fc];
|
||||
unsigned int clkout_cmu_cpu; /* 0x10010a00 */
|
||||
unsigned int clkout_cmu_cpu_div_stat;
|
||||
unsigned char res9[0x5f8];
|
||||
unsigned int armclk_stopctrl;
|
||||
unsigned char res10[0x4];
|
||||
unsigned int arm_ema_ctrl;
|
||||
unsigned int arm_ema_status;
|
||||
unsigned char res11[0x10];
|
||||
unsigned int pwr_ctrl;
|
||||
unsigned int pwr_ctrl2;
|
||||
unsigned char res12[0xd8];
|
||||
unsigned int apll_con0_l8; /* 0x1001100 */
|
||||
unsigned int apll_con0_l7;
|
||||
unsigned int apll_con0_l6;
|
||||
unsigned int apll_con0_l5;
|
||||
unsigned int apll_con0_l4;
|
||||
unsigned int apll_con0_l3;
|
||||
unsigned int apll_con0_l2;
|
||||
unsigned int apll_con0_l1;
|
||||
unsigned int iem_control;
|
||||
unsigned char res13[0xdc];
|
||||
unsigned int apll_con1_l8; /* 0x10011200 */
|
||||
unsigned int apll_con1_l7;
|
||||
unsigned int apll_con1_l6;
|
||||
unsigned int apll_con1_l5;
|
||||
unsigned int apll_con1_l4;
|
||||
unsigned int apll_con1_l3;
|
||||
unsigned int apll_con1_l2;
|
||||
unsigned int apll_con1_l1;
|
||||
unsigned char res14[0xe0];
|
||||
unsigned int clkdiv_iem_l8;
|
||||
unsigned int clkdiv_iem_l7; /* 0x10011304 */
|
||||
unsigned int clkdiv_iem_l6;
|
||||
unsigned int clkdiv_iem_l5;
|
||||
unsigned int clkdiv_iem_l4;
|
||||
unsigned int clkdiv_iem_l3;
|
||||
unsigned int clkdiv_iem_l2;
|
||||
unsigned int clkdiv_iem_l1;
|
||||
unsigned char res15[0xe0];
|
||||
unsigned int l2_status;
|
||||
unsigned char res16[0x0c];
|
||||
unsigned int cpu_status; /* 0x10011410 */
|
||||
unsigned char res17[0x0c];
|
||||
unsigned int ptm_status;
|
||||
unsigned char res18[0xbdc];
|
||||
unsigned int cmu_cpu_spare0;
|
||||
unsigned int cmu_cpu_spare1;
|
||||
unsigned int cmu_cpu_spare2;
|
||||
unsigned int cmu_cpu_spare3;
|
||||
unsigned int cmu_cpu_spare4;
|
||||
unsigned char res19[0x1fdc];
|
||||
unsigned int cmu_cpu_version;
|
||||
unsigned char res20[0x20c];
|
||||
unsigned int src_cperi0; /* 0x10014200 */
|
||||
unsigned int src_cperi1;
|
||||
unsigned char res21[0xf8];
|
||||
unsigned int src_mask_cperi;
|
||||
unsigned char res22[0x100];
|
||||
unsigned int mux_stat_cperi1;
|
||||
unsigned char res23[0xfc];
|
||||
unsigned int div_cperi1;
|
||||
unsigned char res24[0xfc];
|
||||
unsigned int div_stat_cperi1;
|
||||
unsigned char res25[0xf8];
|
||||
unsigned int gate_bus_cperi0; /* 0x10014700 */
|
||||
unsigned int gate_bus_cperi1;
|
||||
unsigned char res26[0xf8];
|
||||
unsigned int gate_sclk_cperi;
|
||||
unsigned char res27[0xfc];
|
||||
unsigned int gate_ip_cperi;
|
||||
unsigned char res28[0xfc];
|
||||
unsigned int clkout_cmu_cperi;
|
||||
unsigned int clkout_cmu_cperi_div_stat;
|
||||
unsigned char res29[0x5f8];
|
||||
unsigned int dcgidx_map0; /* 0x10015000 */
|
||||
unsigned int dcgidx_map1;
|
||||
unsigned int dcgidx_map2;
|
||||
unsigned char res30[0x14];
|
||||
unsigned int dcgperf_map0;
|
||||
unsigned int dcgperf_map1;
|
||||
unsigned char res31[0x18];
|
||||
unsigned int dvcidx_map;
|
||||
unsigned char res32[0x1c];
|
||||
unsigned int freq_cpu;
|
||||
unsigned int freq_dpm;
|
||||
unsigned char res33[0x18];
|
||||
unsigned int dvsemclk_en; /* 0x10015080 */
|
||||
unsigned int maxperf;
|
||||
unsigned char res34[0x2e78];
|
||||
unsigned int cmu_cperi_spare0;
|
||||
unsigned int cmu_cperi_spare1;
|
||||
unsigned int cmu_cperi_spare2;
|
||||
unsigned int cmu_cperi_spare3;
|
||||
unsigned int cmu_cperi_spare4;
|
||||
unsigned int cmu_cperi_spare5;
|
||||
unsigned int cmu_cperi_spare6;
|
||||
unsigned int cmu_cperi_spare7;
|
||||
unsigned int cmu_cperi_spare8;
|
||||
unsigned char res35[0xcc];
|
||||
unsigned int cmu_cperi_version; /* 0x10017ff0 */
|
||||
unsigned char res36[0x50c];
|
||||
unsigned int div_g2d;
|
||||
unsigned char res37[0xfc];
|
||||
unsigned int div_stat_g2d;
|
||||
unsigned char res38[0xfc];
|
||||
unsigned int gate_bus_g2d;
|
||||
unsigned char res39[0xfc];
|
||||
unsigned int gate_ip_g2d;
|
||||
unsigned char res40[0x1fc];
|
||||
unsigned int clkout_cmu_g2d;
|
||||
unsigned int clkout_cmu_g2d_div_stat; /* 0x10018a04 */
|
||||
unsigned char res41[0xf8];
|
||||
unsigned int cmu_g2d_spare0;
|
||||
unsigned int cmu_g2d_spare1;
|
||||
unsigned int cmu_g2d_spare2;
|
||||
unsigned int cmu_g2d_spare3;
|
||||
unsigned int cmu_g2d_spare4;
|
||||
unsigned char res42[0x34dc];
|
||||
unsigned int cmu_g2d_version;
|
||||
unsigned char res43[0x30c];
|
||||
unsigned int div_cmu_isp0;
|
||||
unsigned int div_cmu_isp1;
|
||||
unsigned int div_isp2; /* 0x1001c308 */
|
||||
unsigned char res44[0xf4];
|
||||
unsigned int div_stat_cmu_isp0;
|
||||
unsigned int div_stat_cmu_isp1;
|
||||
unsigned int div_stat_isp2;
|
||||
unsigned char res45[0x2f4];
|
||||
unsigned int gate_bus_isp0;
|
||||
unsigned int gate_bus_isp1;
|
||||
unsigned int gate_bus_isp2;
|
||||
unsigned int gate_bus_isp3;
|
||||
unsigned char res46[0xf0];
|
||||
unsigned int gate_ip_isp0;
|
||||
unsigned int gate_ip_isp1;
|
||||
unsigned char res47[0xf8];
|
||||
unsigned int gate_sclk_isp;
|
||||
unsigned char res48[0x0c];
|
||||
unsigned int mcuisp_pwr_ctrl; /* 0x1001c910 */
|
||||
unsigned char res49[0x0ec];
|
||||
unsigned int clkout_cmu_isp;
|
||||
unsigned int clkout_cmu_isp_div_stat;
|
||||
unsigned char res50[0xf8];
|
||||
unsigned int cmu_isp_spare0;
|
||||
unsigned int cmu_isp_spare1;
|
||||
unsigned int cmu_isp_spare2;
|
||||
unsigned int cmu_isp_spare3;
|
||||
unsigned char res51[0x34e0];
|
||||
unsigned int cmu_isp_version;
|
||||
unsigned char res52[0x2c];
|
||||
unsigned int cpll_lock; /* 10020020 */
|
||||
unsigned char res53[0xc];
|
||||
unsigned int dpll_lock;
|
||||
unsigned char res54[0xc];
|
||||
unsigned int epll_lock;
|
||||
unsigned char res55[0xc];
|
||||
unsigned int rpll_lock;
|
||||
unsigned char res56[0xc];
|
||||
unsigned int ipll_lock;
|
||||
unsigned char res57[0xc];
|
||||
unsigned int spll_lock;
|
||||
unsigned char res58[0xc];
|
||||
unsigned int vpll_lock;
|
||||
unsigned char res59[0xc];
|
||||
unsigned int mpll_lock;
|
||||
unsigned char res60[0x8c];
|
||||
unsigned int cpll_con0; /* 10020120 */
|
||||
unsigned int cpll_con1;
|
||||
unsigned int dpll_con0;
|
||||
unsigned int dpll_con1;
|
||||
unsigned int epll_con0;
|
||||
unsigned int epll_con1;
|
||||
unsigned int epll_con2;
|
||||
unsigned char res601[0x4];
|
||||
unsigned int rpll_con0;
|
||||
unsigned int rpll_con1;
|
||||
unsigned int rpll_con2;
|
||||
unsigned char res602[0x4];
|
||||
unsigned int ipll_con0;
|
||||
unsigned int ipll_con1;
|
||||
unsigned char res61[0x8];
|
||||
unsigned int spll_con0;
|
||||
unsigned int spll_con1;
|
||||
unsigned char res62[0x8];
|
||||
unsigned int vpll_con0;
|
||||
unsigned int vpll_con1;
|
||||
unsigned char res63[0x8];
|
||||
unsigned int mpll_con0;
|
||||
unsigned int mpll_con1;
|
||||
unsigned char res64[0x78];
|
||||
unsigned int src_top0; /* 0x10020200 */
|
||||
unsigned int src_top1;
|
||||
unsigned int src_top2;
|
||||
unsigned int src_top3;
|
||||
unsigned int src_top4;
|
||||
unsigned int src_top5;
|
||||
unsigned int src_top6;
|
||||
unsigned int src_top7;
|
||||
unsigned char res65[0xc];
|
||||
unsigned int src_disp10; /* 0x1002022c */
|
||||
unsigned char res66[0x10];
|
||||
unsigned int src_mau;
|
||||
unsigned int src_fsys;
|
||||
unsigned char res67[0x8];
|
||||
unsigned int src_peric0;
|
||||
unsigned int src_peric1;
|
||||
unsigned char res68[0x18];
|
||||
unsigned int src_isp;
|
||||
unsigned char res69[0x0c];
|
||||
unsigned int src_top10;
|
||||
unsigned int src_top11;
|
||||
unsigned int src_top12;
|
||||
unsigned char res70[0x74];
|
||||
unsigned int src_mask_top0;
|
||||
unsigned int src_mask_top1;
|
||||
unsigned int src_mask_top2;
|
||||
unsigned char res71[0x10];
|
||||
unsigned int src_mask_top7;
|
||||
unsigned char res72[0xc];
|
||||
unsigned int src_mask_disp10; /* 0x1002032c */
|
||||
unsigned char res73[0x4];
|
||||
unsigned int src_mask_mau;
|
||||
unsigned char res74[0x8];
|
||||
unsigned int src_mask_fsys;
|
||||
unsigned char res75[0xc];
|
||||
unsigned int src_mask_peric0;
|
||||
unsigned int src_mask_peric1;
|
||||
unsigned char res76[0x18];
|
||||
unsigned int src_mask_isp;
|
||||
unsigned char res77[0x8c];
|
||||
unsigned int mux_stat_top0; /* 0x10020400 */
|
||||
unsigned int mux_stat_top1;
|
||||
unsigned int mux_stat_top2;
|
||||
unsigned int mux_stat_top3;
|
||||
unsigned int mux_stat_top4;
|
||||
unsigned int mux_stat_top5;
|
||||
unsigned int mux_stat_top6;
|
||||
unsigned int mux_stat_top7;
|
||||
unsigned char res78[0x60];
|
||||
unsigned int mux_stat_top10;
|
||||
unsigned int mux_stat_top11;
|
||||
unsigned int mux_stat_top12;
|
||||
unsigned char res79[0x74];
|
||||
unsigned int div_top0; /* 0x10020500 */
|
||||
unsigned int div_top1;
|
||||
unsigned int div_top2;
|
||||
unsigned char res80[0x20];
|
||||
unsigned int div_disp10;
|
||||
unsigned char res81[0x14];
|
||||
unsigned int div_mau;
|
||||
unsigned int div_fsys0;
|
||||
unsigned int div_fsys1;
|
||||
unsigned int div_fsys2;
|
||||
unsigned char res82[0x4];
|
||||
unsigned int div_peric0;
|
||||
unsigned int div_peric1;
|
||||
unsigned int div_peric2;
|
||||
unsigned int div_peric3;
|
||||
unsigned int div_peric4; /* 0x10020568 */
|
||||
unsigned char res83[0x14];
|
||||
unsigned int div_isp0;
|
||||
unsigned int div_isp1;
|
||||
unsigned char res84[0x8];
|
||||
unsigned int clkdiv2_ratio;
|
||||
unsigned char res850[0xc];
|
||||
unsigned int clkdiv4_ratio;
|
||||
unsigned char res85[0x5c];
|
||||
unsigned int div_stat_top0;
|
||||
unsigned int div_stat_top1;
|
||||
unsigned int div_stat_top2;
|
||||
unsigned char res86[0x20];
|
||||
unsigned int div_stat_disp10;
|
||||
unsigned char res87[0x14];
|
||||
unsigned int div_stat_mau; /* 0x10020644 */
|
||||
unsigned int div_stat_fsys0;
|
||||
unsigned int div_stat_fsys1;
|
||||
unsigned int div_stat_fsys2;
|
||||
unsigned char res88[0x4];
|
||||
unsigned int div_stat_peric0;
|
||||
unsigned int div_stat_peric1;
|
||||
unsigned int div_stat_peric2;
|
||||
unsigned int div_stat_peric3;
|
||||
unsigned int div_stat_peric4;
|
||||
unsigned char res89[0x14];
|
||||
unsigned int div_stat_isp0;
|
||||
unsigned int div_stat_isp1;
|
||||
unsigned char res90[0x8];
|
||||
unsigned int clkdiv2_stat0;
|
||||
unsigned char res91[0xc];
|
||||
unsigned int clkdiv4_stat;
|
||||
unsigned char res92[0x5c];
|
||||
unsigned int gate_bus_top; /* 0x10020700 */
|
||||
unsigned char res93[0xc];
|
||||
unsigned int gate_bus_gscl0;
|
||||
unsigned char res94[0xc];
|
||||
unsigned int gate_bus_gscl1;
|
||||
unsigned char res95[0x4];
|
||||
unsigned int gate_bus_disp1;
|
||||
unsigned char res96[0x4];
|
||||
unsigned int gate_bus_wcore;
|
||||
unsigned int gate_bus_mfc;
|
||||
unsigned int gate_bus_g3d;
|
||||
unsigned int gate_bus_gen;
|
||||
unsigned int gate_bus_fsys0;
|
||||
unsigned int gate_bus_fsys1;
|
||||
unsigned int gate_bus_fsys2;
|
||||
unsigned int gate_bus_mscl;
|
||||
unsigned int gate_bus_peric;
|
||||
unsigned int gate_bus_peric1;
|
||||
unsigned char res97[0x8];
|
||||
unsigned int gate_bus_peris0;
|
||||
unsigned int gate_bus_peris1; /* 0x10020764 */
|
||||
unsigned char res98[0x8];
|
||||
unsigned int gate_bus_noc;
|
||||
unsigned char res99[0xac];
|
||||
unsigned int gate_top_sclk_gscl;
|
||||
unsigned char res1000[0x4];
|
||||
unsigned int gate_top_sclk_disp1;
|
||||
unsigned char res100[0x10];
|
||||
unsigned int gate_top_sclk_mau;
|
||||
unsigned int gate_top_sclk_fsys;
|
||||
unsigned char res101[0xc];
|
||||
unsigned int gate_top_sclk_peric;
|
||||
unsigned char res102[0xc];
|
||||
unsigned int gate_top_sclk_cperi;
|
||||
unsigned char res103[0xc];
|
||||
unsigned int gate_top_sclk_isp;
|
||||
unsigned char res104[0x9c];
|
||||
unsigned int gate_ip_gscl0;
|
||||
unsigned char res105[0xc];
|
||||
unsigned int gate_ip_gscl1;
|
||||
unsigned char res106[0x4];
|
||||
unsigned int gate_ip_disp1;
|
||||
unsigned int gate_ip_mfc;
|
||||
unsigned int gate_ip_g3d;
|
||||
unsigned int gate_ip_gen; /* 0x10020934 */
|
||||
unsigned char res107[0xc];
|
||||
unsigned int gate_ip_fsys;
|
||||
unsigned char res108[0x8];
|
||||
unsigned int gate_ip_peric;
|
||||
unsigned char res109[0xc];
|
||||
unsigned int gate_ip_peris;
|
||||
unsigned char res110[0xc];
|
||||
unsigned int gate_ip_mscl;
|
||||
unsigned char res111[0xc];
|
||||
unsigned int gate_ip_block;
|
||||
unsigned char res112[0xc];
|
||||
unsigned int bypass;
|
||||
unsigned char res113[0x6c];
|
||||
unsigned int clkout_cmu_top;
|
||||
unsigned int clkout_cmu_top_div_stat;
|
||||
unsigned char res114[0xf8];
|
||||
unsigned int clkout_top_spare0;
|
||||
unsigned int clkout_top_spare1;
|
||||
unsigned int clkout_top_spare2;
|
||||
unsigned int clkout_top_spare3;
|
||||
unsigned char res115[0x34e0];
|
||||
unsigned int clkout_top_version;
|
||||
unsigned char res116[0xc01c];
|
||||
unsigned int bpll_lock; /* 0x10030010 */
|
||||
unsigned char res117[0xfc];
|
||||
unsigned int bpll_con0;
|
||||
unsigned int bpll_con1;
|
||||
unsigned char res118[0xe8];
|
||||
unsigned int src_cdrex;
|
||||
unsigned char res119[0x1fc];
|
||||
unsigned int mux_stat_cdrex;
|
||||
unsigned char res120[0xfc];
|
||||
unsigned int div_cdrex0;
|
||||
unsigned int div_cdrex1;
|
||||
unsigned char res121[0xf8];
|
||||
unsigned int div_stat_cdrex;
|
||||
unsigned char res1211[0xfc];
|
||||
unsigned int gate_bus_cdrex;
|
||||
unsigned int gate_bus_cdrex1;
|
||||
unsigned char res122[0x1f8];
|
||||
unsigned int gate_ip_cdrex;
|
||||
unsigned char res123[0x10];
|
||||
unsigned int dmc_freq_ctrl; /* 0x10030914 */
|
||||
unsigned char res124[0x4];
|
||||
unsigned int pause;
|
||||
unsigned int ddrphy_lock_ctrl;
|
||||
unsigned char res125[0xdc];
|
||||
unsigned int clkout_cmu_cdrex;
|
||||
unsigned int clkout_cmu_cdrex_div_stat;
|
||||
unsigned char res126[0x8];
|
||||
unsigned int lpddr3phy_ctrl;
|
||||
unsigned int lpddr3phy_con0;
|
||||
unsigned int lpddr3phy_con1;
|
||||
unsigned int lpddr3phy_con2;
|
||||
unsigned int lpddr3phy_con3;
|
||||
unsigned int lpddr3phy_con4;
|
||||
unsigned int lpddr3phy_con5; /* 0x10030a28 */
|
||||
unsigned int pll_div2_sel;
|
||||
unsigned char res127[0xd0];
|
||||
unsigned int cmu_cdrex_spare0;
|
||||
unsigned int cmu_cdrex_spare1;
|
||||
unsigned int cmu_cdrex_spare2;
|
||||
unsigned int cmu_cdrex_spare3;
|
||||
unsigned int cmu_cdrex_spare4;
|
||||
unsigned char res128[0x34dc];
|
||||
unsigned int cmu_cdrex_version; /* 0x10033ff0 */
|
||||
unsigned char res129[0x400c];
|
||||
unsigned int kpll_lock;
|
||||
unsigned char res130[0xfc];
|
||||
unsigned int kpll_con0;
|
||||
unsigned int kpll_con1;
|
||||
unsigned char res131[0xf8];
|
||||
unsigned int src_kfc;
|
||||
unsigned char res132[0x1fc];
|
||||
unsigned int mux_stat_kfc; /* 0x10038400 */
|
||||
unsigned char res133[0xfc];
|
||||
unsigned int div_kfc0;
|
||||
unsigned char res134[0xfc];
|
||||
unsigned int div_stat_kfc0;
|
||||
unsigned char res135[0xfc];
|
||||
unsigned int gate_bus_cpu_kfc;
|
||||
unsigned char res136[0xfc];
|
||||
unsigned int gate_sclk_cpu_kfc;
|
||||
unsigned char res137[0x1fc];
|
||||
unsigned int clkout_cmu_kfc;
|
||||
unsigned int clkout_cmu_kfc_div_stat; /* 0x10038a04 */
|
||||
unsigned char res138[0x5f8];
|
||||
unsigned int armclk_stopctrl_kfc;
|
||||
unsigned char res139[0x4];
|
||||
unsigned int armclk_ema_ctrl_kfc;
|
||||
unsigned int armclk_ema_status_kfc;
|
||||
unsigned char res140[0x10];
|
||||
unsigned int pwr_ctrl_kfc;
|
||||
unsigned int pwr_ctrl2_kfc;
|
||||
unsigned char res141[0xd8];
|
||||
unsigned int kpll_con0_l8;
|
||||
unsigned int kpll_con0_l7;
|
||||
unsigned int kpll_con0_l6;
|
||||
unsigned int kpll_con0_l5;
|
||||
unsigned int kpll_con0_l4;
|
||||
unsigned int kpll_con0_l3;
|
||||
unsigned int kpll_con0_l2;
|
||||
unsigned int kpll_con0_l1;
|
||||
unsigned int iem_control_kfc; /* 0x10039120 */
|
||||
unsigned char res142[0xdc];
|
||||
unsigned int kpll_con1_l8;
|
||||
unsigned int kpll_con1_l7;
|
||||
unsigned int kpll_con1_l6;
|
||||
unsigned int kpll_con1_l5;
|
||||
unsigned int kpll_con1_l4;
|
||||
unsigned int kpll_con1_l3;
|
||||
unsigned int kpll_con1_l2;
|
||||
unsigned int kpll_con1_l1;
|
||||
unsigned char res143[0xe0];
|
||||
unsigned int clkdiv_iem_l8_kfc; /* 0x10039300 */
|
||||
unsigned int clkdiv_iem_l7_kfc;
|
||||
unsigned int clkdiv_iem_l6_kfc;
|
||||
unsigned int clkdiv_iem_l5_kfc;
|
||||
unsigned int clkdiv_iem_l4_kfc;
|
||||
unsigned int clkdiv_iem_l3_kfc;
|
||||
unsigned int clkdiv_iem_l2_kfc;
|
||||
unsigned int clkdiv_iem_l1_kfc;
|
||||
unsigned char res144[0xe0];
|
||||
unsigned int l2_status_kfc;
|
||||
unsigned char res145[0xc];
|
||||
unsigned int cpu_status_kfc; /* 0x10039410 */
|
||||
unsigned char res146[0xc];
|
||||
unsigned int ptm_status_kfc;
|
||||
unsigned char res147[0xbdc];
|
||||
unsigned int cmu_kfc_spare0;
|
||||
unsigned int cmu_kfc_spare1;
|
||||
unsigned int cmu_kfc_spare2;
|
||||
unsigned int cmu_kfc_spare3;
|
||||
unsigned int cmu_kfc_spare4;
|
||||
unsigned char res148[0x1fdc];
|
||||
unsigned int cmu_kfc_version; /* 0x1003bff0 */
|
||||
};
|
||||
|
||||
/* structure for epll configuration used in audio clock configuration */
|
||||
struct set_epll_con_val {
|
||||
unsigned int freq_out; /* frequency out */
|
||||
|
||||
@@ -53,6 +53,7 @@
|
||||
#define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
|
||||
|
||||
/* EXYNOS4X12 */
|
||||
#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
|
||||
@@ -91,8 +92,9 @@
|
||||
#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
|
||||
|
||||
/* EXYNOS5 Common*/
|
||||
/* EXYNOS5 */
|
||||
#define EXYNOS5_I2C_SPACING 0x10000
|
||||
|
||||
#define EXYNOS5_AUDIOSS_BASE 0x03810000
|
||||
@@ -129,6 +131,46 @@
|
||||
|
||||
#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS5_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
|
||||
|
||||
/* EXYNOS5420 */
|
||||
#define EXYNOS5420_AUDIOSS_BASE 0x03810000
|
||||
#define EXYNOS5420_GPIO_PART5_BASE 0x03860000
|
||||
#define EXYNOS5420_PRO_ID 0x10000000
|
||||
#define EXYNOS5420_CLOCK_BASE 0x10010000
|
||||
#define EXYNOS5420_POWER_BASE 0x10040000
|
||||
#define EXYNOS5420_SWRESET 0x10040400
|
||||
#define EXYNOS5420_SYSREG_BASE 0x10050000
|
||||
#define EXYNOS5420_TZPC_BASE 0x100E0000
|
||||
#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
|
||||
#define EXYNOS5420_ACE_SFR_BASE 0x10830000
|
||||
#define EXYNOS5420_DMC_PHY_BASE 0x10C00000
|
||||
#define EXYNOS5420_DMC_CTRL_BASE 0x10C20000
|
||||
#define EXYNOS5420_DMC_TZASC_BASE 0x10D40000
|
||||
#define EXYNOS5420_USB_HOST_EHCI_BASE 0x12110000
|
||||
#define EXYNOS5420_MMC_BASE 0x12200000
|
||||
#define EXYNOS5420_SROMC_BASE 0x12250000
|
||||
#define EXYNOS5420_UART_BASE 0x12C00000
|
||||
#define EXYNOS5420_I2C_BASE 0x12C60000
|
||||
#define EXYNOS5420_I2C_8910_BASE 0x12E00000
|
||||
#define EXYNOS5420_SPI_BASE 0x12D20000
|
||||
#define EXYNOS5420_I2S_BASE 0x12D60000
|
||||
#define EXYNOS5420_PWMTIMER_BASE 0x12DD0000
|
||||
#define EXYNOS5420_SPI_ISP_BASE 0x131A0000
|
||||
#define EXYNOS5420_GPIO_PART2_BASE 0x13400000
|
||||
#define EXYNOS5420_GPIO_PART3_BASE 0x13410000
|
||||
#define EXYNOS5420_GPIO_PART4_BASE 0x14000000
|
||||
#define EXYNOS5420_GPIO_PART1_BASE 0x14010000
|
||||
#define EXYNOS5420_MIPI_DSIM_BASE 0x14500000
|
||||
#define EXYNOS5420_DP_BASE 0x145B0000
|
||||
|
||||
#define EXYNOS5420_USBPHY_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS5420_USBOTG_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS5420_FIMD_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS5420_ADC_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS5420_MODEM_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/io.h>
|
||||
@@ -163,6 +205,10 @@ static inline void s5p_set_cpu_id(void)
|
||||
/* Exynos5250 */
|
||||
s5p_cpu_id = 0x5250;
|
||||
break;
|
||||
case 0x420:
|
||||
/* Exynos5420 */
|
||||
s5p_cpu_id = 0x5420;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -190,6 +236,7 @@ static inline int __attribute__((no_instrument_function)) \
|
||||
IS_EXYNOS_TYPE(exynos4210, 0x4210)
|
||||
IS_EXYNOS_TYPE(exynos4412, 0x4412)
|
||||
IS_EXYNOS_TYPE(exynos5250, 0x5250)
|
||||
IS_EXYNOS_TYPE(exynos5420, 0x5420)
|
||||
|
||||
#define SAMSUNG_BASE(device, base) \
|
||||
static inline unsigned int __attribute__((no_instrument_function)) \
|
||||
@@ -200,6 +247,8 @@ static inline unsigned int __attribute__((no_instrument_function)) \
|
||||
return EXYNOS4X12_##base; \
|
||||
return EXYNOS4_##base; \
|
||||
} else if (cpu_is_exynos5()) { \
|
||||
if (proid_is_exynos5420()) \
|
||||
return EXYNOS5420_##base; \
|
||||
return EXYNOS5_##base; \
|
||||
} \
|
||||
return 0; \
|
||||
@@ -237,6 +286,7 @@ SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
|
||||
SAMSUNG_BASE(tzpc, TZPC_BASE)
|
||||
SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
|
||||
SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
|
||||
SAMSUNG_BASE(dmc_tzasc, DMC_TZASC_BASE)
|
||||
SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
|
||||
#endif
|
||||
|
||||
|
||||
@@ -205,6 +205,127 @@ struct exynos5_dmc {
|
||||
unsigned int pmcnt3_ppc_a;
|
||||
};
|
||||
|
||||
struct exynos5420_dmc {
|
||||
unsigned int concontrol;
|
||||
unsigned int memcontrol;
|
||||
unsigned int cgcontrol;
|
||||
unsigned char res500[0x4];
|
||||
unsigned int directcmd;
|
||||
unsigned int prechconfig0;
|
||||
unsigned int phycontrol0;
|
||||
unsigned int prechconfig1;
|
||||
unsigned char res1[0x8];
|
||||
unsigned int pwrdnconfig;
|
||||
unsigned int timingpzq;
|
||||
unsigned int timingref;
|
||||
unsigned int timingrow0;
|
||||
unsigned int timingdata0;
|
||||
unsigned int timingpower0;
|
||||
unsigned int phystatus;
|
||||
unsigned int etctiming;
|
||||
unsigned int chipstatus;
|
||||
unsigned char res3[0x8];
|
||||
unsigned int mrstatus;
|
||||
unsigned char res4[0x8];
|
||||
unsigned int qoscontrol0;
|
||||
unsigned char resr5[0x4];
|
||||
unsigned int qoscontrol1;
|
||||
unsigned char res6[0x4];
|
||||
unsigned int qoscontrol2;
|
||||
unsigned char res7[0x4];
|
||||
unsigned int qoscontrol3;
|
||||
unsigned char res8[0x4];
|
||||
unsigned int qoscontrol4;
|
||||
unsigned char res9[0x4];
|
||||
unsigned int qoscontrol5;
|
||||
unsigned char res10[0x4];
|
||||
unsigned int qoscontrol6;
|
||||
unsigned char res11[0x4];
|
||||
unsigned int qoscontrol7;
|
||||
unsigned char res12[0x4];
|
||||
unsigned int qoscontrol8;
|
||||
unsigned char res13[0x4];
|
||||
unsigned int qoscontrol9;
|
||||
unsigned char res14[0x4];
|
||||
unsigned int qoscontrol10;
|
||||
unsigned char res15[0x4];
|
||||
unsigned int qoscontrol11;
|
||||
unsigned char res16[0x4];
|
||||
unsigned int qoscontrol12;
|
||||
unsigned char res17[0x4];
|
||||
unsigned int qoscontrol13;
|
||||
unsigned char res18[0x4];
|
||||
unsigned int qoscontrol14;
|
||||
unsigned char res19[0x4];
|
||||
unsigned int qoscontrol15;
|
||||
unsigned char res20[0x4];
|
||||
unsigned int timing_set_sw;
|
||||
unsigned int timingrow1;
|
||||
unsigned int timingdata1;
|
||||
unsigned int timingpower1;
|
||||
unsigned char res300[0x4];
|
||||
unsigned int wrtra_config;
|
||||
unsigned int rdlvl_config;
|
||||
unsigned char res21[0x4];
|
||||
unsigned int brbrsvcontrol;
|
||||
unsigned int brbrsvconfig;
|
||||
unsigned int brbqosconfig;
|
||||
unsigned char res301[0x14];
|
||||
unsigned int wrlvl_config0;
|
||||
unsigned int wrlvl_config1;
|
||||
unsigned int wrlvl_status;
|
||||
unsigned char res23[0x4];
|
||||
unsigned int ppcclockon;
|
||||
unsigned int perevconfig0;
|
||||
unsigned int perevconfig1;
|
||||
unsigned int perevconfig2;
|
||||
unsigned int perevconfig3;
|
||||
unsigned char res24[0xc];
|
||||
unsigned int control_io_rdata;
|
||||
unsigned char res240[0xc];
|
||||
unsigned int cacal_config0;
|
||||
unsigned int cacal_config1;
|
||||
unsigned int cacal_status;
|
||||
unsigned char res302[0xa4];
|
||||
unsigned int bp_control0;
|
||||
unsigned int bp_config0_r;
|
||||
unsigned int bp_config0_w;
|
||||
unsigned char res303[0x4];
|
||||
unsigned int bp_control1;
|
||||
unsigned int bp_config1_r;
|
||||
unsigned int bp_config1_w;
|
||||
unsigned char res304[0x4];
|
||||
unsigned int bp_control2;
|
||||
unsigned int bp_config2_r;
|
||||
unsigned int bp_config2_w;
|
||||
unsigned char res305[0x4];
|
||||
unsigned int bp_control3;
|
||||
unsigned int bp_config3_r;
|
||||
unsigned int bp_config3_w;
|
||||
unsigned char res306[0xddb4];
|
||||
unsigned int pmnc_ppc;
|
||||
unsigned char res25[0xc];
|
||||
unsigned int cntens_ppc;
|
||||
unsigned char res26[0xc];
|
||||
unsigned int cntenc_ppc;
|
||||
unsigned char res27[0xc];
|
||||
unsigned int intens_ppc;
|
||||
unsigned char res28[0xc];
|
||||
unsigned int intenc_ppc;
|
||||
unsigned char res29[0xc];
|
||||
unsigned int flag_ppc;
|
||||
unsigned char res30[0xac];
|
||||
unsigned int ccnt_ppc;
|
||||
unsigned char res31[0xc];
|
||||
unsigned int pmcnt0_ppc;
|
||||
unsigned char res32[0xc];
|
||||
unsigned int pmcnt1_ppc;
|
||||
unsigned char res33[0xc];
|
||||
unsigned int pmcnt2_ppc;
|
||||
unsigned char res34[0xc];
|
||||
unsigned int pmcnt3_ppc;
|
||||
};
|
||||
|
||||
struct exynos5_phy_control {
|
||||
unsigned int phy_con0;
|
||||
unsigned int phy_con1;
|
||||
@@ -252,6 +373,61 @@ struct exynos5_phy_control {
|
||||
unsigned int phy_con42;
|
||||
};
|
||||
|
||||
struct exynos5420_phy_control {
|
||||
unsigned int phy_con0;
|
||||
unsigned int phy_con1;
|
||||
unsigned int phy_con2;
|
||||
unsigned int phy_con3;
|
||||
unsigned int phy_con4;
|
||||
unsigned int phy_con5;
|
||||
unsigned int phy_con6;
|
||||
unsigned char res2[0x4];
|
||||
unsigned int phy_con8;
|
||||
unsigned char res5[0x4];
|
||||
unsigned int phy_con10;
|
||||
unsigned int phy_con11;
|
||||
unsigned int phy_con12;
|
||||
unsigned int phy_con13;
|
||||
unsigned int phy_con14;
|
||||
unsigned int phy_con15;
|
||||
unsigned int phy_con16;
|
||||
unsigned char res4[0x4];
|
||||
unsigned int phy_con17;
|
||||
unsigned int phy_con18;
|
||||
unsigned int phy_con19;
|
||||
unsigned int phy_con20;
|
||||
unsigned int phy_con21;
|
||||
unsigned int phy_con22;
|
||||
unsigned int phy_con23;
|
||||
unsigned int phy_con24;
|
||||
unsigned int phy_con25;
|
||||
unsigned int phy_con26;
|
||||
unsigned int phy_con27;
|
||||
unsigned int phy_con28;
|
||||
unsigned int phy_con29;
|
||||
unsigned int phy_con30;
|
||||
unsigned int phy_con31;
|
||||
unsigned int phy_con32;
|
||||
unsigned int phy_con33;
|
||||
unsigned int phy_con34;
|
||||
unsigned char res6[0x8];
|
||||
unsigned int phy_con37;
|
||||
unsigned char res7[0x4];
|
||||
unsigned int phy_con39;
|
||||
unsigned int phy_con40;
|
||||
unsigned int phy_con41;
|
||||
unsigned int phy_con42;
|
||||
};
|
||||
|
||||
struct exynos5420_tzasc {
|
||||
unsigned char res1[0xf00];
|
||||
unsigned int membaseconfig0;
|
||||
unsigned int membaseconfig1;
|
||||
unsigned char res2[0x8];
|
||||
unsigned int memconfig0;
|
||||
unsigned int memconfig1;
|
||||
};
|
||||
|
||||
enum ddr_mode {
|
||||
DDR_MODE_DDR2,
|
||||
DDR_MODE_DDR3,
|
||||
@@ -286,6 +462,7 @@ enum mem_manuf {
|
||||
#define PHY_CON0_T_WRRDCMD_SHIFT 17
|
||||
#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
|
||||
#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
|
||||
#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
|
||||
|
||||
/* PHY_CON1 register fields */
|
||||
#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
|
||||
|
||||
@@ -127,6 +127,58 @@ struct exynos4x12_gpio_part4 {
|
||||
struct s5p_gpio_bank v4;
|
||||
};
|
||||
|
||||
struct exynos5420_gpio_part1 {
|
||||
struct s5p_gpio_bank a0;
|
||||
struct s5p_gpio_bank a1;
|
||||
struct s5p_gpio_bank a2;
|
||||
struct s5p_gpio_bank b0;
|
||||
struct s5p_gpio_bank b1;
|
||||
struct s5p_gpio_bank b2;
|
||||
struct s5p_gpio_bank b3;
|
||||
struct s5p_gpio_bank b4;
|
||||
struct s5p_gpio_bank h0;
|
||||
};
|
||||
|
||||
struct exynos5420_gpio_part2 {
|
||||
struct s5p_gpio_bank y7; /* 0x1340_0000 */
|
||||
struct s5p_gpio_bank res[0x5f]; /* */
|
||||
struct s5p_gpio_bank x0; /* 0x1340_0C00 */
|
||||
struct s5p_gpio_bank x1; /* 0x1340_0C20 */
|
||||
struct s5p_gpio_bank x2; /* 0x1340_0C40 */
|
||||
struct s5p_gpio_bank x3; /* 0x1340_0C60 */
|
||||
};
|
||||
|
||||
struct exynos5420_gpio_part3 {
|
||||
struct s5p_gpio_bank c0;
|
||||
struct s5p_gpio_bank c1;
|
||||
struct s5p_gpio_bank c2;
|
||||
struct s5p_gpio_bank c3;
|
||||
struct s5p_gpio_bank c4;
|
||||
struct s5p_gpio_bank d1;
|
||||
struct s5p_gpio_bank y0;
|
||||
struct s5p_gpio_bank y1;
|
||||
struct s5p_gpio_bank y2;
|
||||
struct s5p_gpio_bank y3;
|
||||
struct s5p_gpio_bank y4;
|
||||
struct s5p_gpio_bank y5;
|
||||
struct s5p_gpio_bank y6;
|
||||
};
|
||||
|
||||
struct exynos5420_gpio_part4 {
|
||||
struct s5p_gpio_bank e0; /* 0x1400_0000 */
|
||||
struct s5p_gpio_bank e1; /* 0x1400_0020 */
|
||||
struct s5p_gpio_bank f0; /* 0x1400_0040 */
|
||||
struct s5p_gpio_bank f1; /* 0x1400_0060 */
|
||||
struct s5p_gpio_bank g0; /* 0x1400_0080 */
|
||||
struct s5p_gpio_bank g1; /* 0x1400_00A0 */
|
||||
struct s5p_gpio_bank g2; /* 0x1400_00C0 */
|
||||
struct s5p_gpio_bank j4; /* 0x1400_00E0 */
|
||||
};
|
||||
|
||||
struct exynos5420_gpio_part5 {
|
||||
struct s5p_gpio_bank z0; /* 0x0386_0000 */
|
||||
};
|
||||
|
||||
struct exynos5_gpio_part1 {
|
||||
struct s5p_gpio_bank a0;
|
||||
struct s5p_gpio_bank a1;
|
||||
@@ -259,16 +311,67 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
|
||||
- EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
|
||||
|
||||
|
||||
/* EXYNOS5420 */
|
||||
#define exynos5420_gpio_part1_get_nr(bank, pin) \
|
||||
((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\
|
||||
EXYNOS5420_GPIO_PART1_BASE)->bank)) \
|
||||
- EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin)
|
||||
|
||||
#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define exynos5420_gpio_part2_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\
|
||||
EXYNOS5420_GPIO_PART2_BASE)->bank)) \
|
||||
- EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX)
|
||||
|
||||
#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define exynos5420_gpio_part3_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\
|
||||
EXYNOS5420_GPIO_PART3_BASE)->bank)) \
|
||||
- EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX)
|
||||
|
||||
#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define exynos5420_gpio_part4_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\
|
||||
EXYNOS5420_GPIO_PART4_BASE)->bank)) \
|
||||
- EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX)
|
||||
|
||||
#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
static inline unsigned int s5p_gpio_base(int nr)
|
||||
{
|
||||
if (cpu_is_exynos5()) {
|
||||
if (nr < EXYNOS5_GPIO_PART1_MAX)
|
||||
return EXYNOS5_GPIO_PART1_BASE;
|
||||
else if (nr < EXYNOS5_GPIO_PART2_MAX)
|
||||
return EXYNOS5_GPIO_PART2_BASE;
|
||||
else
|
||||
return EXYNOS5_GPIO_PART3_BASE;
|
||||
|
||||
if (proid_is_exynos5420()) {
|
||||
if (nr < EXYNOS5420_GPIO_PART1_MAX)
|
||||
return EXYNOS5420_GPIO_PART1_BASE;
|
||||
else if (nr < EXYNOS5420_GPIO_PART2_MAX)
|
||||
return EXYNOS5420_GPIO_PART2_BASE;
|
||||
else if (nr < EXYNOS5420_GPIO_PART3_MAX)
|
||||
return EXYNOS5420_GPIO_PART3_BASE;
|
||||
else
|
||||
return EXYNOS5420_GPIO_PART4_BASE;
|
||||
} else {
|
||||
if (nr < EXYNOS5_GPIO_PART1_MAX)
|
||||
return EXYNOS5_GPIO_PART1_BASE;
|
||||
else if (nr < EXYNOS5_GPIO_PART2_MAX)
|
||||
return EXYNOS5_GPIO_PART2_BASE;
|
||||
else
|
||||
return EXYNOS5_GPIO_PART3_BASE;
|
||||
}
|
||||
} else if (cpu_is_exynos4()) {
|
||||
if (nr < EXYNOS4_GPIO_PART1_MAX)
|
||||
return EXYNOS4_GPIO_PART1_BASE;
|
||||
@@ -282,13 +385,25 @@ static inline unsigned int s5p_gpio_base(int nr)
|
||||
static inline unsigned int s5p_gpio_part_max(int nr)
|
||||
{
|
||||
if (cpu_is_exynos5()) {
|
||||
if (nr < EXYNOS5_GPIO_PART1_MAX)
|
||||
return 0;
|
||||
else if (nr < EXYNOS5_GPIO_PART2_MAX)
|
||||
return EXYNOS5_GPIO_PART1_MAX;
|
||||
else
|
||||
return EXYNOS5_GPIO_PART2_MAX;
|
||||
|
||||
if (proid_is_exynos5420()) {
|
||||
if (nr < EXYNOS5420_GPIO_PART1_MAX)
|
||||
return 0;
|
||||
else if (nr < EXYNOS5420_GPIO_PART2_MAX)
|
||||
return EXYNOS5420_GPIO_PART1_MAX;
|
||||
else if (nr < EXYNOS5420_GPIO_PART3_MAX)
|
||||
return EXYNOS5420_GPIO_PART2_MAX;
|
||||
else if (nr < EXYNOS5420_GPIO_PART4_MAX)
|
||||
return EXYNOS5420_GPIO_PART3_MAX;
|
||||
else
|
||||
return EXYNOS5420_GPIO_PART4_MAX;
|
||||
} else {
|
||||
if (nr < EXYNOS5_GPIO_PART1_MAX)
|
||||
return 0;
|
||||
else if (nr < EXYNOS5_GPIO_PART2_MAX)
|
||||
return EXYNOS5_GPIO_PART1_MAX;
|
||||
else
|
||||
return EXYNOS5_GPIO_PART2_MAX;
|
||||
}
|
||||
} else if (cpu_is_exynos4()) {
|
||||
if (proid_is_exynos4412()) {
|
||||
if (nr < EXYNOS4X12_GPIO_PART1_MAX)
|
||||
|
||||
@@ -34,6 +34,9 @@ enum periph_id {
|
||||
PERIPH_ID_SDMMC1,
|
||||
PERIPH_ID_SDMMC2,
|
||||
PERIPH_ID_SDMMC3,
|
||||
PERIPH_ID_I2C8 = 87,
|
||||
PERIPH_ID_I2C9,
|
||||
PERIPH_ID_I2C10 = 203,
|
||||
PERIPH_ID_I2S0 = 98,
|
||||
PERIPH_ID_I2S1 = 99,
|
||||
|
||||
|
||||
@@ -831,6 +831,843 @@ struct exynos5_power {
|
||||
unsigned int cmu_reset_mau_option;
|
||||
unsigned char res163[0x24];
|
||||
};
|
||||
|
||||
struct exynos5420_power {
|
||||
unsigned int om_stat;
|
||||
unsigned int lpi_mask0;
|
||||
unsigned int lpi_mask1;
|
||||
unsigned char res1[0x10];
|
||||
unsigned int rtc_clko_sel;
|
||||
unsigned char res2[0x1e0];
|
||||
unsigned int central_seq_configuration;
|
||||
unsigned int central_seq_status;
|
||||
unsigned int central_seq_option;
|
||||
unsigned char res3[0x14];
|
||||
unsigned int seq_transition0;
|
||||
unsigned int seq_transition1;
|
||||
unsigned int seq_transition2;
|
||||
unsigned int seq_transition3;
|
||||
unsigned int seq_transition4;
|
||||
unsigned int seq_transition5;
|
||||
unsigned int seq_transition6;
|
||||
unsigned int seq_transition7;
|
||||
unsigned int central_seq_coreblk_configuration;
|
||||
unsigned int central_seq_coreblk_status;
|
||||
unsigned int central_seq_coreblk_option;
|
||||
unsigned char res4[0x14];
|
||||
unsigned int seq_coreblk_transition0;
|
||||
unsigned int seq_coreblk_transition1;
|
||||
unsigned int seq_coreblk_transition2;
|
||||
unsigned int seq_coreblk_transition3;
|
||||
unsigned int seq_coreblk_transition4;
|
||||
unsigned int seq_coreblk_transition5;
|
||||
unsigned int seq_coreblk_transition6;
|
||||
unsigned int seq_coreblk_transition7;
|
||||
unsigned char res5[0x180];
|
||||
unsigned int swreset;
|
||||
unsigned int rst_stat;
|
||||
unsigned int automatic_wdt_reset_disable;
|
||||
unsigned int mask_wdt_reset_request;
|
||||
unsigned int mask_wreset_request;
|
||||
unsigned char res6[0xec];
|
||||
unsigned int reset_sequencer_configuration;
|
||||
unsigned int reset_sequencer_status;
|
||||
unsigned int reset_sequencer_option;
|
||||
unsigned char res7[0xf4];
|
||||
unsigned int wakeup_stat;
|
||||
unsigned int eint_wakeup_mask;
|
||||
unsigned int wakeup_mask;
|
||||
unsigned int wakeup_interrupt;
|
||||
unsigned char res8[0x10];
|
||||
unsigned int wakeup_stat_coreblk;
|
||||
unsigned int eint_wakeup_mask_coreblk;
|
||||
unsigned int wakeup_mask_coreblk;
|
||||
unsigned int wakeup_interrupt_coreblk;
|
||||
unsigned char res9[0xd0];
|
||||
unsigned int hdmi_phy_control;
|
||||
unsigned int usbdev_phy_control;
|
||||
unsigned int usbdev1_phy_control;
|
||||
unsigned int usbhost_phy_control;
|
||||
unsigned char res104[0x4];
|
||||
unsigned int mipi_phy0_control;
|
||||
unsigned int mipi_phy1_control;
|
||||
unsigned int mipi_phy2_control;
|
||||
unsigned int adc_phy_control;
|
||||
unsigned int mtcadc_phy_control;
|
||||
unsigned int dptx_phy_control;
|
||||
unsigned char res10[0xd4];
|
||||
unsigned int inform0;
|
||||
unsigned int inform1;
|
||||
unsigned int inform2;
|
||||
unsigned int inform3;
|
||||
unsigned int sysip_dat0;
|
||||
unsigned int sysip_dat1;
|
||||
unsigned int sysip_dat2;
|
||||
unsigned int sysip_dat3;
|
||||
unsigned char res11[0xe0];
|
||||
unsigned int pmu_spare0;
|
||||
unsigned int pmu_spare1;
|
||||
unsigned int pmu_spare2;
|
||||
unsigned int pmu_spare3;
|
||||
unsigned char res12[0x4];
|
||||
unsigned int cg_status0;
|
||||
unsigned int cg_status1;
|
||||
unsigned int cg_status2;
|
||||
unsigned int cg_status3;
|
||||
unsigned int cg_status4;
|
||||
unsigned char res200[0x58];
|
||||
unsigned int irom_data_reg0;
|
||||
unsigned int irom_data_reg1;
|
||||
unsigned int irom_data_reg2;
|
||||
unsigned int irom_data_reg3;
|
||||
unsigned char res13[0x70];
|
||||
unsigned int pmu_debug;
|
||||
unsigned char res14[0x5fc];
|
||||
unsigned int arm_core0_sys_pwr_reg;
|
||||
unsigned char res500[0xc];
|
||||
unsigned int arm_core1_sys_pwr_reg;
|
||||
unsigned char res501[0xc];
|
||||
unsigned int arm_core2_sys_pwr_reg;
|
||||
unsigned char res502[0xc];
|
||||
unsigned int arm_core3_sys_pwr_reg;
|
||||
unsigned char res503[0xc];
|
||||
unsigned int kfc_core0_sys_pwr_reg;
|
||||
unsigned char res504[0xc];
|
||||
unsigned int kfc_core1_sys_pwr_reg;
|
||||
unsigned char res505[0xc];
|
||||
unsigned int kfc_core2_sys_pwr_reg;
|
||||
unsigned char res506[0xc];
|
||||
unsigned int kfc_core3_sys_pwr_reg;
|
||||
unsigned char res507[0x1c];
|
||||
unsigned int isp_arm_sys_pwr_reg;
|
||||
unsigned char res18[0xc];
|
||||
unsigned int arm_common_sys_pwr_reg;
|
||||
unsigned char res508[0xc];
|
||||
unsigned int kfc_common_sys_pwr_reg;
|
||||
unsigned char res19[0xc];
|
||||
unsigned int arm_l2_sys_pwr_reg;
|
||||
unsigned char res509[0xc];
|
||||
unsigned int kfc_l2_sys_pwr_reg;
|
||||
unsigned char res20[0xc];
|
||||
unsigned int cmu_cpu_aclkstop_sys_pwr_reg;
|
||||
unsigned int cmu_cpu_sclkstop_sys_pwr_reg;
|
||||
unsigned char res510[0x8];
|
||||
unsigned int cmu_kfc_aclkstop_sys_pwr_reg;
|
||||
unsigned char res511[0xc];
|
||||
unsigned int cmu_aclkstop_sys_pwr_reg;
|
||||
unsigned int cmu_sclkstop_sys_pwr_reg;
|
||||
unsigned char res21[0x4];
|
||||
unsigned int cmu_reset_sys_pwr_reg;
|
||||
unsigned char res22[0x10];
|
||||
unsigned int cmu_aclkstop_coreblk_sys_pwr_reg;
|
||||
unsigned int cmu_sclkstop_coreblk_sys_pwr_reg;
|
||||
unsigned char res23[0x4];
|
||||
unsigned int cmu_reset_coreblk_sys_pwr_reg;
|
||||
unsigned int dram_freq_down_sys_pwr_reg;
|
||||
unsigned int ddrphy_dlloff_sys_pwr_reg;
|
||||
unsigned int ddrphy_dlllock_sys_pwr_reg;
|
||||
unsigned char res25[0x4];
|
||||
unsigned int apll_sysclk_sys_pwr_reg;
|
||||
unsigned int mpll_sysclk_sys_pwr_reg;
|
||||
unsigned int vpll_sysclk_sys_pwr_reg;
|
||||
unsigned int epll_sysclk_sys_pwr_reg;
|
||||
unsigned int bpll_sysclk_sys_pwr_reg;
|
||||
unsigned int cpll_sysclk_sys_pwr_reg;
|
||||
unsigned int dpll_sysclk_sys_pwr_reg;
|
||||
unsigned int ipll_sysclk_sys_pwr_reg;
|
||||
unsigned int kpll_sysclk_sys_pwr_reg;
|
||||
unsigned int mplluser_sysclk_sys_pwr_reg;
|
||||
unsigned char res512[0x8];
|
||||
unsigned int bplluser_sysclk_sys_pwr_reg;
|
||||
unsigned int rpll_sysclk_sys_pwr_reg;
|
||||
unsigned int spll_sysclk_sys_pwr_reg;
|
||||
unsigned char res26[0x4];
|
||||
unsigned int top_bus_sys_pwr_reg;
|
||||
unsigned int top_retention_sys_pwr_reg;
|
||||
unsigned int top_pwr_sys_pwr_reg;
|
||||
unsigned char res29[0x4];
|
||||
unsigned int top_bus_coreblk_sys_pwr_reg;
|
||||
unsigned int top_retention_coreblk_sys_pwr_reg;
|
||||
unsigned int top_pwr_coreblk_sys_pwr_reg;
|
||||
unsigned char res30[0x4];
|
||||
unsigned int logic_reset_sys_pwr_reg;
|
||||
unsigned int oscclk_gate_sys_pwr_reg;
|
||||
unsigned char res31[0x8];
|
||||
unsigned int logic_reset_coreblk_sys_pwr_reg;
|
||||
unsigned int oscclk_gate_coreblk_sys_pwr_reg;
|
||||
unsigned int intram_mem_sys_pwr_reg;
|
||||
unsigned int introm_mem_sys_pwr_reg;
|
||||
unsigned char res32[0x44];
|
||||
unsigned int pad_retention_mau_sys_pwr_reg;
|
||||
unsigned int pad_retention_jtag_sys_pwr_reg;
|
||||
unsigned char res36[0x4];
|
||||
unsigned int pad_retention_dram_sys_pwr_reg;
|
||||
unsigned int pad_retention_uart_sys_pwr_reg;
|
||||
unsigned int pad_retention_mmca_sys_pwr_reg;
|
||||
unsigned int pad_retention_mmcb_sys_pwr_reg;
|
||||
unsigned int pad_retention_mmcc_sys_pwr_reg;
|
||||
unsigned int pad_retention_hsi_sys_pwr_reg;
|
||||
unsigned int pad_retention_ebia_sys_pwr_reg;
|
||||
unsigned int pad_retention_ebib_sys_pwr_reg;
|
||||
unsigned int pad_retention_spi_sys_pwr_reg;
|
||||
unsigned int pad_retention_dram_coreblk_sys_pwr_reg;
|
||||
unsigned char res28[0x8];
|
||||
unsigned int pad_isolation_sys_pwr_reg;
|
||||
unsigned char res37[0xc];
|
||||
unsigned int pad_isolation_coreblk_sys_pwr_reg;
|
||||
unsigned char res38[0xc];
|
||||
unsigned int pad_alv_sel_sys_pwr_reg;
|
||||
unsigned char res39[0x1c];
|
||||
unsigned int xusbxti_sys_pwr_reg;
|
||||
unsigned int xxti_sys_pwr_reg;
|
||||
unsigned char res40[0x38];
|
||||
unsigned int ext_regulator_sys_pwr_reg;
|
||||
unsigned char res41[0x3c];
|
||||
unsigned int gpio_mode_sys_pwr_reg;
|
||||
unsigned char res42[0x1c];
|
||||
unsigned int gpio_mode_coreblk_sys_pwr_reg;
|
||||
unsigned char res43[0x1c];
|
||||
unsigned int gpio_mode_mau_sys_pwr_reg;
|
||||
unsigned int top_asb_reset_sys_pwr_reg;
|
||||
unsigned int top_asb_isolation_sys_pwr_reg;
|
||||
unsigned char res44[0xb4];
|
||||
unsigned int gscl_sys_pwr_reg;
|
||||
unsigned int isp_sys_pwr_reg;
|
||||
unsigned int mfc_sys_pwr_reg;
|
||||
unsigned int g3d_sys_pwr_reg;
|
||||
unsigned int disp1_sys_pwr_reg;
|
||||
unsigned int mau_sys_pwr_reg;
|
||||
unsigned int g2d_sys_pwr_reg;
|
||||
unsigned int msc_sys_pwr_reg;
|
||||
unsigned int fsys_sys_pwr_reg;
|
||||
unsigned int fsys2_sys_pwr_reg;
|
||||
unsigned int psgen_sys_pwr_reg;
|
||||
unsigned int peric_sys_pwr_reg;
|
||||
unsigned int wcore_sys_pwr_reg;
|
||||
unsigned char res46[0x4c];
|
||||
unsigned int cmu_clkstop_gscl_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_isp_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_mfc_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_g3d_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_disp1_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_mau_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_g2d_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_msc_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_fsys_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_fsys2_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_psgen_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_peric_sys_pwr_reg;
|
||||
unsigned int cmu_clkstop_wcore_sys_pwr_reg;
|
||||
unsigned char res48[0x8];
|
||||
unsigned int cmu_sysclk_toppwr_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_gscl_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_isp_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_mfc_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_g3d_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_disp1_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_mau_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_g2d_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_msc_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_fsys_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_fsys2_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_psgen_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_peric_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_wcore_sys_pwr_reg;
|
||||
unsigned int cmu_sysclk_coreblk_toppwr_sys_pwr_reg;
|
||||
unsigned char res50[0x78];
|
||||
unsigned int cmu_reset_fsys2_sys_pwr_reg;
|
||||
unsigned int cmu_reset_psgen_sys_pwr_reg;
|
||||
unsigned int cmu_reset_peric_sys_pwr_reg;
|
||||
unsigned int cmu_reset_wcore_sys_pwr_reg;
|
||||
unsigned int cmu_reset_gscl_sys_pwr_reg;
|
||||
unsigned int cmu_reset_isp_sys_pwr_reg;
|
||||
unsigned int cmu_reset_mfc_sys_pwr_reg;
|
||||
unsigned int cmu_reset_g3d_sys_pwr_reg;
|
||||
unsigned int cmu_reset_disp1_sys_pwr_reg;
|
||||
unsigned int cmu_reset_mau_sys_pwr_reg;
|
||||
unsigned int cmu_reset_g2d_sys_pwr_reg;
|
||||
unsigned int cmu_reset_msc_sys_pwr_reg;
|
||||
unsigned int cmu_reset_fsys_sys_pwr_reg;
|
||||
unsigned char res52[0xa5c];
|
||||
unsigned int arm_core0_configuration;
|
||||
unsigned int arm_core0_status;
|
||||
unsigned int arm_core0_option;
|
||||
unsigned char res53[0x14];
|
||||
unsigned int dis_irq_arm_core0_local_configuration;
|
||||
unsigned int dis_irq_arm_core0_local_status;
|
||||
unsigned int dis_irq_arm_core0_local_option;
|
||||
unsigned char res54[0x14];
|
||||
unsigned int dis_irq_arm_core0_central_configuration;
|
||||
unsigned int dis_irq_arm_core0_central_status;
|
||||
unsigned int dis_irq_arm_core0_central_option;
|
||||
unsigned char res55[0x34];
|
||||
unsigned int arm_core1_configuration;
|
||||
unsigned int arm_core1_status;
|
||||
unsigned int arm_core1_option;
|
||||
unsigned char res56[0x14];
|
||||
unsigned int dis_irq_arm_core1_local_configuration;
|
||||
unsigned int dis_irq_arm_core1_local_status;
|
||||
unsigned int dis_irq_arm_core1_local_option;
|
||||
unsigned char res57[0x14];
|
||||
unsigned int dis_irq_arm_core1_central_configuration;
|
||||
unsigned int dis_irq_arm_core1_central_status;
|
||||
unsigned int dis_irq_arm_core1_central_option;
|
||||
unsigned char res600[0x34];
|
||||
unsigned int arm_core2_configuration;
|
||||
unsigned int arm_core2_status;
|
||||
unsigned int arm_core2_option;
|
||||
unsigned char res601[0x14];
|
||||
unsigned int dis_irq_arm_core2_local_configuration;
|
||||
unsigned int dis_irq_arm_core2_local_status;
|
||||
unsigned int dis_irq_arm_core2_local_option;
|
||||
unsigned char res602[0x14];
|
||||
unsigned int dis_irq_arm_core2_central_configuration;
|
||||
unsigned int dis_irq_arm_core2_central_status;
|
||||
unsigned int dis_irq_arm_core2_central_option;
|
||||
unsigned char res603[0x34];
|
||||
unsigned int arm_core3_configuration;
|
||||
unsigned int arm_core3_status;
|
||||
unsigned int arm_core3_option;
|
||||
unsigned char res900[0x14];
|
||||
unsigned int dis_irq_arm_core3_local_configuration;
|
||||
unsigned int dis_irq_arm_core3_local_status;
|
||||
unsigned int dis_irq_arm_core3_local_option;
|
||||
unsigned char res901[0x14];
|
||||
unsigned int dis_irq_arm_core3_central_configuration;
|
||||
unsigned int dis_irq_arm_core3_central_status;
|
||||
unsigned int dis_irq_arm_core3_central_option;
|
||||
unsigned char res604[0x34];
|
||||
unsigned int kfc_core0_configuration;
|
||||
unsigned int kfc_core0_status;
|
||||
unsigned int kfc_core0_option;
|
||||
unsigned char res605[0x14];
|
||||
unsigned int dis_irq_kfc_core0_local_configuration;
|
||||
unsigned int dis_irq_kfc_core0_local_status;
|
||||
unsigned int dis_irq_kfc_core0_local_option;
|
||||
unsigned char res606[0x14];
|
||||
unsigned int dis_irq_kfc_core0_central_configuration;
|
||||
unsigned int dis_irq_kfc_core0_central_status;
|
||||
unsigned int dis_irq_kfc_core0_central_option;
|
||||
unsigned char res607[0x34];
|
||||
unsigned int kfc_core1_configuration;
|
||||
unsigned int kfc_core1_status;
|
||||
unsigned int kfc_core1_option;
|
||||
unsigned char res608[0x14];
|
||||
unsigned int dis_irq_kfc_core1_local_configuration;
|
||||
unsigned int dis_irq_kfc_core1_local_status;
|
||||
unsigned int dis_irq_kfc_core1_local_option;
|
||||
unsigned char res609[0x14];
|
||||
unsigned int dis_irq_kfc_core1_central_configuration;
|
||||
unsigned int dis_irq_kfc_core1_central_status;
|
||||
unsigned int dis_irq_kfc_core1_central_option;
|
||||
unsigned char res610[0x34];
|
||||
unsigned int kfc_core2_configuration;
|
||||
unsigned int kfc_core2_status;
|
||||
unsigned int kfc_core2_option;
|
||||
unsigned char res611[0x14];
|
||||
unsigned int dis_irq_kfc_core2_local_configuration;
|
||||
unsigned int dis_irq_kfc_core2_local_status;
|
||||
unsigned int dis_irq_kfc_core2_local_option;
|
||||
unsigned char res612[0x14];
|
||||
unsigned int dis_irq_kfc_core2_central_configuration;
|
||||
unsigned int dis_irq_kfc_core2_central_status;
|
||||
unsigned int dis_irq_kfc_core2_central_option;
|
||||
unsigned char res613[0x34];
|
||||
unsigned int kfc_core3_configuration;
|
||||
unsigned int kfc_core3_status;
|
||||
unsigned int kfc_core3_option;
|
||||
unsigned char res614[0x14];
|
||||
unsigned int dis_irq_kfc_core3_local_configuration;
|
||||
unsigned int dis_irq_kfc_core3_local_status;
|
||||
unsigned int dis_irq_kfc_core3_local_option;
|
||||
unsigned char res615[0x14];
|
||||
unsigned int dis_irq_kfc_core3_central_configuration;
|
||||
unsigned int dis_irq_kfc_core3_central_status;
|
||||
unsigned int dis_irq_kfc_core3_central_option;
|
||||
unsigned char res61[0xb4];
|
||||
unsigned int isp_arm_configuration;
|
||||
unsigned int isp_arm_status;
|
||||
unsigned int isp_arm_option;
|
||||
unsigned char res62[0x14];
|
||||
unsigned int dis_irq_isp_arm_local_configuration;
|
||||
unsigned int dis_irq_isp_arm_local_status;
|
||||
unsigned int dis_irq_isp_arm_local_option;
|
||||
unsigned char res63[0x14];
|
||||
unsigned int dis_irq_isp_arm_central_configuration;
|
||||
unsigned int dis_irq_isp_arm_central_status;
|
||||
unsigned int dis_irq_isp_arm_central_option;
|
||||
unsigned char res64[0x34];
|
||||
unsigned int arm_common_configuration;
|
||||
unsigned int arm_common_status;
|
||||
unsigned int arm_common_option;
|
||||
unsigned char res616[0x74];
|
||||
unsigned int kfc_common_configuration;
|
||||
unsigned int kfc_common_status;
|
||||
unsigned int kfc_common_option;
|
||||
unsigned char res65[0x74];
|
||||
unsigned int arm_l2_configuration;
|
||||
unsigned int arm_l2_status;
|
||||
unsigned int arm_l2_option;
|
||||
unsigned char res617[0x74];
|
||||
unsigned int kfc_l2_configuration;
|
||||
unsigned int kfc_l2_status;
|
||||
unsigned int kfc_l2_option;
|
||||
unsigned char res66[0x74];
|
||||
unsigned int cmu_cpu_aclkstop_configuration;
|
||||
unsigned int cmu_cpu_aclkstop_status;
|
||||
unsigned int cmu_cpu_aclkstop_option;
|
||||
unsigned char res67[0x14];
|
||||
unsigned int cmu_cpu_sclkstop_configuration;
|
||||
unsigned int cmu_cpu_sclkstop_status;
|
||||
unsigned int cmu_cpu_sclkstop_option;
|
||||
unsigned char res618[0x4];
|
||||
unsigned int cmu_kfc_aclkstop_configuration;
|
||||
unsigned int cmu_kfc_aclkstop_status;
|
||||
unsigned int cmu_kfc_aclkstop_option;
|
||||
unsigned char res619[0xc4];
|
||||
unsigned int cmu_aclkstop_configuration;
|
||||
unsigned int cmu_aclkstop_status;
|
||||
unsigned int cmu_aclkstop_option;
|
||||
unsigned char res620[0x14];
|
||||
unsigned int cmu_sclkstop_configuration;
|
||||
unsigned int cmu_sclkstop_status;
|
||||
unsigned int cmu_sclkstop_option;
|
||||
unsigned char res68[0x34];
|
||||
unsigned int cmu_reset_configuration;
|
||||
unsigned int cmu_reset_status;
|
||||
unsigned int cmu_reset_option;
|
||||
unsigned char res69[0x94];
|
||||
unsigned int cmu_aclkstop_coreblk_configuration;
|
||||
unsigned int cmu_aclkstop_coreblk_status;
|
||||
unsigned int cmu_aclkstop_coreblk_option;
|
||||
unsigned char res70[0x14];
|
||||
unsigned int cmu_sclkstop_coreblk_configuration;
|
||||
unsigned int cmu_sclkstop_coreblk_status;
|
||||
unsigned int cmu_sclkstop_coreblk_option;
|
||||
unsigned char res71[0x34];
|
||||
unsigned int cmu_reset_coreblk_configuration;
|
||||
unsigned int cmu_reset_coreblk_status;
|
||||
unsigned int cmu_reset_coreblk_option;
|
||||
unsigned char res621[0x14];
|
||||
unsigned int dram_freq_down_configuration;
|
||||
unsigned int dram_freq_down_status;
|
||||
unsigned int dram_freq_down_option;
|
||||
unsigned char res622[0x14];
|
||||
unsigned int ddrphy_dlloff_configuration;
|
||||
unsigned int ddrphy_dlloff_status;
|
||||
unsigned int ddrphy_dlloff_option;
|
||||
unsigned char res72[0x14];
|
||||
unsigned int ddrphy_dlllock_configuration;
|
||||
unsigned int ddrphy_dlllock_status;
|
||||
unsigned int ddrphy_dlllock_option;
|
||||
unsigned char res73[0x34];
|
||||
unsigned int apll_sysclk_configuration;
|
||||
unsigned int apll_sysclk_status;
|
||||
unsigned int apll_sysclk_option;
|
||||
unsigned char res74[0x18];
|
||||
unsigned int mpll_sysclk_status;
|
||||
unsigned int mpll_sysclk_option;
|
||||
unsigned char res75[0x14];
|
||||
unsigned int vpll_sysclk_configuration;
|
||||
unsigned int vpll_sysclk_status;
|
||||
unsigned int vpll_sysclk_option;
|
||||
unsigned char res76[0x14];
|
||||
unsigned int epll_sysclk_configuration;
|
||||
unsigned int epll_sysclk_status;
|
||||
unsigned int epll_sysclk_option;
|
||||
unsigned char res77[0x14];
|
||||
unsigned int bpll_sysclk_configuration;
|
||||
unsigned int bpll_sysclk_status;
|
||||
unsigned int bpll_sysclk_option;
|
||||
unsigned char res78[0x14];
|
||||
unsigned int cpll_sysclk_configuration;
|
||||
unsigned int cpll_sysclk_status;
|
||||
unsigned int cpll_sysclk_option;
|
||||
unsigned char res79[0x14];
|
||||
unsigned int dpll_sysclk_configuration;
|
||||
unsigned int dpll_sysclk_status;
|
||||
unsigned int dpll_sysclk_option;
|
||||
unsigned char res700[0x14];
|
||||
unsigned int ipll_sysclk_configuration;
|
||||
unsigned int ipll_sysclk_status;
|
||||
unsigned int ipll_sysclk_option;
|
||||
unsigned char res903[0x14];
|
||||
unsigned int kpll_sysclk_configuration;
|
||||
unsigned int kpll_sysclk_status;
|
||||
unsigned int kpll_sysclk_option;
|
||||
unsigned char res80[0x14];
|
||||
unsigned int mplluser_sysclk_configuration;
|
||||
unsigned int mplluser_sysclk_status;
|
||||
unsigned int mplluser_sysclk_option;
|
||||
unsigned char res81[0x54];
|
||||
unsigned int bplluser_sysclk_configuration;
|
||||
unsigned int bplluser_sysclk_status;
|
||||
unsigned int bplluser_sysclk_option;
|
||||
unsigned char res701[0x14];
|
||||
unsigned int rplluser_sysclk_configuration;
|
||||
unsigned int rplluser_sysclk_status;
|
||||
unsigned int rplluser_sysclk_option;
|
||||
unsigned char res702[0x14];
|
||||
unsigned int splluser_sysclk_configuration;
|
||||
unsigned int splluser_sysclk_status;
|
||||
unsigned int splluser_sysclk_option;
|
||||
unsigned char res82[0x34];
|
||||
unsigned int top_bus_configuration;
|
||||
unsigned int top_bus_status;
|
||||
unsigned int top_bus_option;
|
||||
unsigned char res83[0x14];
|
||||
unsigned int top_retention_configuration;
|
||||
unsigned int top_retention_status;
|
||||
unsigned int top_retention_option;
|
||||
unsigned char res84[0x14];
|
||||
unsigned int top_pwr_configuration;
|
||||
unsigned int top_pwr_status;
|
||||
unsigned int top_pwr_option;
|
||||
unsigned char res85[0x34];
|
||||
unsigned int top_bus_coreblk_configuration;
|
||||
unsigned int top_bus_coreblk_status;
|
||||
unsigned int top_bus_coreblk_option;
|
||||
unsigned char res86[0x14];
|
||||
unsigned int top_retention_coreblk_configuration;
|
||||
unsigned int top_retention_coreblk_status;
|
||||
unsigned int top_retention_coreblk_option;
|
||||
unsigned char res87[0x14];
|
||||
unsigned int top_pwr_coreblk_configuration;
|
||||
unsigned int top_pwr_coreblk_status;
|
||||
unsigned int top_pwr_coreblk_option;
|
||||
unsigned char res88[0x34];
|
||||
unsigned int logic_reset_configuration;
|
||||
unsigned int logic_reset_status;
|
||||
unsigned int logic_reset_option;
|
||||
unsigned char res89[0x14];
|
||||
unsigned int oscclk_gate_configuration;
|
||||
unsigned int oscclk_gate_status;
|
||||
unsigned int oscclk_gate_option;
|
||||
unsigned char res90[0x54];
|
||||
unsigned int logic_reset_coreblk_configuration;
|
||||
unsigned int logic_reset_coreblk_status;
|
||||
unsigned int logic_reset_coreblk_option;
|
||||
unsigned char res91[0x14];
|
||||
unsigned int oscclk_gate_coreblk_configuration;
|
||||
unsigned int oscclk_gate_coreblk_status;
|
||||
unsigned int oscclk_gate_coreblk_option;
|
||||
unsigned char res99[0x174];
|
||||
unsigned int intram_mem_configuration;
|
||||
unsigned int intram_mem_status;
|
||||
unsigned int intram_mem_option;
|
||||
unsigned char res100[0x14];
|
||||
unsigned int introm_mem_configuration;
|
||||
unsigned int introm_mem_status;
|
||||
unsigned int introm_mem_option;
|
||||
unsigned char res101[0xb4];
|
||||
unsigned int pad_retention_dram_configuration;
|
||||
unsigned int pad_retention_dram_status;
|
||||
unsigned int pad_retention_dram_option;
|
||||
unsigned char res106[0x14];
|
||||
unsigned int pad_retention_mau_configuration;
|
||||
unsigned int pad_retention_mau_status;
|
||||
unsigned int pad_retention_mau_option;
|
||||
unsigned char res107[0x14];
|
||||
unsigned int pad_retention_jtag_configuration;
|
||||
unsigned int pad_retention_jtag_status;
|
||||
unsigned int pad_retention_jtag_option;
|
||||
unsigned char res92[0x74];
|
||||
unsigned int pad_retention_dram_configuration_2;
|
||||
unsigned int pad_retention_dram_status_2;
|
||||
unsigned int pad_retention_dram_option_2;
|
||||
unsigned char res111[0x14];
|
||||
unsigned int pad_retention_uart_configuration;
|
||||
unsigned int pad_retention_uart_status;
|
||||
unsigned int pad_retention_uart_option;
|
||||
unsigned char res112[0x14];
|
||||
unsigned int pad_retention_mmca_configuration;
|
||||
unsigned int pad_retention_mmca_status;
|
||||
unsigned int pad_retention_mmca_option;
|
||||
unsigned char res113[0x14];
|
||||
unsigned int pad_retention_mmcb_configuration;
|
||||
unsigned int pad_retention_mmcb_status;
|
||||
unsigned int pad_retention_mmcb_option;
|
||||
unsigned char res93[0x14];
|
||||
unsigned int pad_retention_mmcc_configuration;
|
||||
unsigned int pad_retention_mmcc_status;
|
||||
unsigned int pad_retention_mmcc_option;
|
||||
unsigned char res94[0x14];
|
||||
unsigned int pad_retention_hsi_configuration;
|
||||
unsigned int pad_retention_hsi_status;
|
||||
unsigned int pad_retention_hsi_option;
|
||||
unsigned char res114[0x14];
|
||||
unsigned int pad_retention_ebia_configuration;
|
||||
unsigned int pad_retention_ebia_status;
|
||||
unsigned int pad_retention_ebia_option;
|
||||
unsigned char res115[0x14];
|
||||
unsigned int pad_retention_ebib_configuration;
|
||||
unsigned int pad_retention_ebib_status;
|
||||
unsigned int pad_retention_ebib_option;
|
||||
unsigned char res116[0x14];
|
||||
unsigned int pad_retention_spi_configuration;
|
||||
unsigned int pad_retention_spi_status;
|
||||
unsigned int pad_retention_spi_option;
|
||||
unsigned char res117[0x14];
|
||||
unsigned int pad_retention_dram_coreblk_configuration;
|
||||
unsigned int pad_retention_dram_coreblk_status;
|
||||
unsigned int pad_retention_dram_coreblk_option;
|
||||
unsigned char res118[0x14];
|
||||
unsigned int pad_isolation_configuration;
|
||||
unsigned int pad_isolation_status;
|
||||
unsigned int pad_isolation_option;
|
||||
unsigned char res119[0x74];
|
||||
unsigned int pad_isolation_coreblk_configuration;
|
||||
unsigned int pad_isolation_coreblk_status;
|
||||
unsigned int pad_isolation_coreblk_option;
|
||||
unsigned char res120[0x74];
|
||||
unsigned int pad_alv_sel_configuration;
|
||||
unsigned int pad_alv_sel_status;
|
||||
unsigned int pad_alv_sel_option0;
|
||||
unsigned int ps_hold_control;
|
||||
unsigned char res130[0xf0];
|
||||
unsigned int xusbxti_configuration;
|
||||
unsigned int xusbxti_status;
|
||||
unsigned int xusbxti_option;
|
||||
unsigned char res910[0x10];
|
||||
unsigned int xusbxti_duration3;
|
||||
unsigned int xxti_configuration;
|
||||
unsigned int xxti_status;
|
||||
unsigned int xxti_option;
|
||||
unsigned char res131[0x10];
|
||||
unsigned int xxti_duration3;
|
||||
unsigned char res132[0x1c0];
|
||||
unsigned int ext_regulator_configuration;
|
||||
unsigned int ext_regulator_status;
|
||||
unsigned int ext_regulator_option;
|
||||
unsigned char res133[0x10];
|
||||
unsigned int ext_regulator_duration3;
|
||||
unsigned char res134[0x1e0];
|
||||
unsigned int gpio_mode_configuration;
|
||||
unsigned int gpio_mode_status;
|
||||
unsigned int gpio_mode_option;
|
||||
unsigned char res135[0xf4];
|
||||
unsigned int gpio_mode_coreblk_configuration;
|
||||
unsigned int gpio_mode_coreblk_status;
|
||||
unsigned int gpio_mode_coreblk_option;
|
||||
unsigned char res136[0xd4];
|
||||
unsigned int gpio_mode_mau_configuration;
|
||||
unsigned int gpio_mode_mau_status;
|
||||
unsigned int gpio_mode_mau_option;
|
||||
unsigned char res137[0x14];
|
||||
unsigned int top_asb_reset_configuration;
|
||||
unsigned int top_asb_reset_status;
|
||||
unsigned int top_asb_reset_option;
|
||||
unsigned char res138[0x14];
|
||||
unsigned int top_asb_isolation_configuration;
|
||||
unsigned int top_asb_isolation_status;
|
||||
unsigned int top_asb_isolation_option;
|
||||
unsigned char res139[0x5d4];
|
||||
unsigned int gscl_configuration;
|
||||
unsigned int gscl_status;
|
||||
unsigned int gscl_option;
|
||||
unsigned char res140[0x14];
|
||||
unsigned int isp_configuration;
|
||||
unsigned int isp_status;
|
||||
unsigned int isp_option;
|
||||
unsigned char res141[0x34];
|
||||
unsigned int mfc_configuration;
|
||||
unsigned int mfc_status;
|
||||
unsigned int mfc_option;
|
||||
unsigned char res142[0x14];
|
||||
unsigned int g3d_configuration;
|
||||
unsigned int g3d_status;
|
||||
unsigned int g3d_option;
|
||||
unsigned char res143[0x34];
|
||||
unsigned int disp1_configuration;
|
||||
unsigned int disp1_status;
|
||||
unsigned int disp1_option;
|
||||
unsigned char res144[0x14];
|
||||
unsigned int mau_configuration;
|
||||
unsigned int mau_status;
|
||||
unsigned int mau_option;
|
||||
unsigned char res800[0x14];
|
||||
unsigned int g2d_configuration;
|
||||
unsigned int g2d_status;
|
||||
unsigned int g2d_option;
|
||||
unsigned char res801[0x14];
|
||||
unsigned int msc_configuration;
|
||||
unsigned int msc_status;
|
||||
unsigned int msc_option;
|
||||
unsigned char res802[0x14];
|
||||
unsigned int fsys_configuration;
|
||||
unsigned int fsys_status;
|
||||
unsigned int fsys_option;
|
||||
unsigned char res803[0x14];
|
||||
unsigned int fsys2_configuration;
|
||||
unsigned int fsys2_status;
|
||||
unsigned int fsys2_option;
|
||||
unsigned char res804[0x14];
|
||||
unsigned int psgen_configuration;
|
||||
unsigned int psgen_status;
|
||||
unsigned int psgen_option;
|
||||
unsigned char res805[0x14];
|
||||
unsigned int peric_configuration;
|
||||
unsigned int peric_status;
|
||||
unsigned int peric_option;
|
||||
unsigned char res806[0x14];
|
||||
unsigned int wcore_configuration;
|
||||
unsigned int wcore_status;
|
||||
unsigned int wcore_option;
|
||||
unsigned char res145[0x234];
|
||||
unsigned int cmu_clkstop_gscl_configuration;
|
||||
unsigned int cmu_clkstop_gscl_status;
|
||||
unsigned int cmu_clkstop_gscl_option;
|
||||
unsigned char res146[0x14];
|
||||
unsigned int cmu_clkstop_isp_configuration;
|
||||
unsigned int cmu_clkstop_isp_status;
|
||||
unsigned int cmu_clkstop_isp_option;
|
||||
unsigned char res147[0x34];
|
||||
unsigned int cmu_clkstop_mfc_configuration;
|
||||
unsigned int cmu_clkstop_mfc_status;
|
||||
unsigned int cmu_clkstop_mfc_option;
|
||||
unsigned char res148[0x14];
|
||||
unsigned int cmu_clkstop_g3d_configuration;
|
||||
unsigned int cmu_clkstop_g3d_status;
|
||||
unsigned int cmu_clkstop_g3d_option;
|
||||
unsigned char res149[0x34];
|
||||
unsigned int cmu_clkstop_disp1_configuration;
|
||||
unsigned int cmu_clkstop_disp1_status;
|
||||
unsigned int cmu_clkstop_disp1_option;
|
||||
unsigned char res150[0x14];
|
||||
unsigned int cmu_clkstop_mau_configuration;
|
||||
unsigned int cmu_clkstop_mau_status;
|
||||
unsigned int cmu_clkstop_mau_option;
|
||||
unsigned char res807[0x14];
|
||||
unsigned int cmu_clkstop_g2d_configuration;
|
||||
unsigned int cmu_clkstop_g2d_status;
|
||||
unsigned int cmu_clkstop_g2d_option;
|
||||
unsigned char res808[0x14];
|
||||
unsigned int cmu_clkstop_msc_configuration;
|
||||
unsigned int cmu_clkstop_msc_status;
|
||||
unsigned int cmu_clkstop_msc_option;
|
||||
unsigned char res809[0x14];
|
||||
unsigned int cmu_clkstop_fsys_configuration;
|
||||
unsigned int cmu_clkstop_fsys_status;
|
||||
unsigned int cmu_clkstop_fsys_option;
|
||||
unsigned char res810[0x14];
|
||||
unsigned int cmu_clkstop_fsys2_configuration;
|
||||
unsigned int cmu_clkstop_fsys2_status;
|
||||
unsigned int cmu_clkstop_fsys2_option;
|
||||
unsigned char res811[0x14];
|
||||
unsigned int cmu_clkstop_psgen_configuration;
|
||||
unsigned int cmu_clkstop_psgen_status;
|
||||
unsigned int cmu_clkstop_psgen_option;
|
||||
unsigned char res812[0x14];
|
||||
unsigned int cmu_clkstop_peric_configuration;
|
||||
unsigned int cmu_clkstop_peric_status;
|
||||
unsigned int cmu_clkstop_peric_option;
|
||||
unsigned char res813[0x14];
|
||||
unsigned int cmu_clkstop_wcore_configuration;
|
||||
unsigned int cmu_clkstop_wcore_status;
|
||||
unsigned int cmu_clkstop_wcore_option;
|
||||
unsigned char res151[0x14];
|
||||
unsigned int cmu_sysclk_toppwr_configuration;
|
||||
unsigned int cmu_sysclk_toppwr_status;
|
||||
unsigned int cmu_sysclk_toppwr_option;
|
||||
unsigned char res920[0x18];
|
||||
unsigned int cmu_sysclk_gscl_status;
|
||||
unsigned int cmu_sysclk_gscl_option;
|
||||
unsigned char res152[0x18];
|
||||
unsigned int cmu_sysclk_isp_status;
|
||||
unsigned int cmu_sysclk_isp_option;
|
||||
unsigned char res153[0x38];
|
||||
unsigned int cmu_sysclk_mfc_status;
|
||||
unsigned int cmu_sysclk_mfc_option;
|
||||
unsigned char res154[0x18];
|
||||
unsigned int cmu_sysclk_g3d_status;
|
||||
unsigned int cmu_sysclk_g3d_option;
|
||||
unsigned char res155[0x38];
|
||||
unsigned int cmu_sysclk_disp1_status;
|
||||
unsigned int cmu_sysclk_disp1_option;
|
||||
unsigned char res156[0x18];
|
||||
unsigned int cmu_sysclk_mau_status;
|
||||
unsigned int cmu_sysclk_mau_option;
|
||||
unsigned char res814[0x18];
|
||||
unsigned int cmu_sysclk_g2d_status;
|
||||
unsigned int cmu_sysclk_g2d_option;
|
||||
unsigned char res815[0x18];
|
||||
unsigned int cmu_sysclk_msc_status;
|
||||
unsigned int cmu_sysclk_msc_option;
|
||||
unsigned char res922[0x18];
|
||||
unsigned int cmu_sysclk_fsys_status;
|
||||
unsigned int cmu_sysclk_fsys_option;
|
||||
unsigned char res816[0x18];
|
||||
unsigned int cmu_sysclk_fsys2_status;
|
||||
unsigned int cmu_sysclk_fsys2_option;
|
||||
unsigned char res817[0x18];
|
||||
unsigned int cmu_sysclk_psgen_status;
|
||||
unsigned int cmu_sysclk_psgen_option;
|
||||
unsigned char res950[0x18];
|
||||
unsigned int cmu_sysclk_peric_status;
|
||||
unsigned int cmu_sysclk_peric_option;
|
||||
unsigned char res818[0x18];
|
||||
unsigned int cmu_sysclk_wcore_status;
|
||||
unsigned int cmu_sysclk_wcore_option;
|
||||
unsigned char res819[0x18];
|
||||
unsigned int cmu_sysclk_coreblk_toppwr_status;
|
||||
unsigned int cmu_sysclk_coreblk_toppwr_option;
|
||||
unsigned char res157[0x414];
|
||||
unsigned int cmu_reset_gscl_configuration;
|
||||
unsigned int cmu_reset_gscl_status;
|
||||
unsigned int cmu_reset_gscl_option;
|
||||
unsigned char res158[0x14];
|
||||
unsigned int cmu_reset_isp_configuration;
|
||||
unsigned int cmu_reset_isp_status;
|
||||
unsigned int cmu_reset_isp_option;
|
||||
unsigned char res159[0x34];
|
||||
unsigned int cmu_reset_mfc_configuration;
|
||||
unsigned int cmu_reset_mfc_status;
|
||||
unsigned int cmu_reset_mfc_option;
|
||||
unsigned char res160[0x14];
|
||||
unsigned int cmu_reset_g3d_configuration;
|
||||
unsigned int cmu_reset_g3d_status;
|
||||
unsigned int cmu_reset_g3d_option;
|
||||
unsigned char res161[0x34];
|
||||
unsigned int cmu_reset_disp1_configuration;
|
||||
unsigned int cmu_reset_disp1_status;
|
||||
unsigned int cmu_reset_disp1_option;
|
||||
unsigned char res162[0x14];
|
||||
unsigned int cmu_reset_mau_configuration;
|
||||
unsigned int cmu_reset_mau_status;
|
||||
unsigned int cmu_reset_mau_option;
|
||||
unsigned char res163[0x14];
|
||||
unsigned int version_info;
|
||||
unsigned int i2s_bypass;
|
||||
unsigned int kfc_swreset_mask_from_eagle;
|
||||
unsigned char res164[0xf4];
|
||||
unsigned int cmu_reset_g2d_configuration;
|
||||
unsigned int cmu_reset_g2d_status;
|
||||
unsigned int cmu_reset_g2d_option;
|
||||
unsigned char res165[0x14];
|
||||
unsigned int cmu_reset_msc_configuration;
|
||||
unsigned int cmu_reset_msc_status;
|
||||
unsigned int cmu_reset_msc_option;
|
||||
unsigned char res166[0x14];
|
||||
unsigned int cmu_reset_fsys_configuration;
|
||||
unsigned int cmu_reset_fsys_status;
|
||||
unsigned int cmu_reset_fsys_option;
|
||||
unsigned char res167[0x14];
|
||||
unsigned int cmu_reset_fsys2_configuration;
|
||||
unsigned int cmu_reset_fsys2_status;
|
||||
unsigned int cmu_reset_fsys2_option;
|
||||
unsigned char res168[0x14];
|
||||
unsigned int cmu_reset_psgen_configuration;
|
||||
unsigned int cmu_reset_psgen_status;
|
||||
unsigned int cmu_reset_psgen_option;
|
||||
unsigned char res169[0x14];
|
||||
unsigned int cmu_reset_peric_configuration;
|
||||
unsigned int cmu_reset_peric_status;
|
||||
unsigned int cmu_reset_peric_option;
|
||||
unsigned char res170[0x14];
|
||||
unsigned int cmu_reset_wcore_configuration;
|
||||
unsigned int cmu_reset_wcore_status;
|
||||
unsigned int cmu_reset_wcore_option;
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
|
||||
|
||||
Reference in New Issue
Block a user