From 953b6095fcaf045f877bb71bb70bea2a062732b8 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Thu, 29 Jul 2021 20:02:41 -0700 Subject: [PATCH 01/13] arm: kirkwood: GoFlex Home: Add DM Ethernet, remove IDE, and add DM SATA configs Add DM_ETH, SATA_MV and associated configs to goflexhome_defconfig. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- configs/goflexhome_defconfig | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 7207fa27e0f..17adeca92fe 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -16,7 +16,6 @@ CONFIG_CONSOLE_MUX=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="GoFlexHome> " # CONFIG_CMD_FLASH is not set -CONFIG_CMD_IDE=y CONFIG_CMD_NAND=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -48,3 +47,7 @@ CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_CMD_SATA=y +CONFIG_SATA_MV=y +CONFIG_DM_ETH=y +CONFIG_NET_RANDOM_ETHADDR=y From 296c32b243888af0846afd829bdcdf8157763b4e Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Thu, 29 Jul 2021 20:02:42 -0700 Subject: [PATCH 02/13] arm: kirkwood: GoFlex Home: Add DM SATA configs Enable DM SATA in board file. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- include/configs/goflexhome.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h index a18e7869b08..2e89d72285d 100644 --- a/include/configs/goflexhome.h +++ b/include/configs/goflexhome.h @@ -72,4 +72,10 @@ #define CONFIG_PHY_BASE_ADR 0 #endif /* CONFIG_CMD_NET */ +/* SATA driver configuration */ +#ifdef CONFIG_SATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_LBA48 +#endif /* CONFIG_SATA */ + #endif /* _CONFIG_GOFLEXHOME_H */ From 293a8de6fa0fdc70f6de6d7fb8d70d46e342e42c Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Thu, 29 Jul 2021 20:02:43 -0700 Subject: [PATCH 03/13] arm: kirkwood: GoFlex Home: Use Ethernet PHY name and address from device tree In DM Ethernet, the old "egiga0" name is no longer valid, so replace these with Ethernet PHY names from device tree. Also, read Ethernet PHY address from device tree. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- board/Seagate/goflexhome/goflexhome.c | 57 +++++++++++++++++++++------ 1 file changed, 45 insertions(+), 12 deletions(-) diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index af8cab7bdc7..52be64fb8c2 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -1,5 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2021 + * Tony Dinh + * Suriyan Ramasami + * * Copyright (C) 2013 Suriyan Ramasami * * Based on dockstar.c originally written by @@ -107,36 +111,65 @@ int board_init(void) return 0; } +static int fdt_get_phy_addr(const char *path) +{ + const void *fdt = gd->fdt_blob; + const u32 *reg; + const u32 *val; + int node, phandle, addr; + + /* Find the node by its full path */ + node = fdt_path_offset(fdt, path); + if (node >= 0) { + /* Look up phy-handle */ + val = fdt_getprop(fdt, node, "phy-handle", NULL); + if (val) { + phandle = fdt32_to_cpu(*val); + if (!phandle) + return -1; + /* Follow it to its node */ + node = fdt_node_offset_by_phandle(fdt, phandle); + if (node) { + /* Look up reg */ + reg = fdt_getprop(fdt, node, "reg", NULL); + if (reg) { + addr = fdt32_to_cpu(*reg); + return addr; + } + } + } + } + return -1; +} + #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { u16 reg; - u16 devadr; - char *name = "egiga0"; + int phyaddr; + char *name = "ethernet-controller@72000"; + char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0"; if (miiphy_set_current_dev(name)) return; - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { - printf("Err..%s could not read PHY dev address\n", - __func__); + phyaddr = fdt_get_phy_addr(eth0_path); + if (phyaddr < 0) return; - } /* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); /* reset the phy */ - miiphy_reset(name, devadr); + miiphy_reset(name, phyaddr); printf("88E1116 Initialized on %s\n", name); } From 29795302b942e6ee41c9d95f7e6e29f57d108d42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Jul 2021 14:22:52 +0200 Subject: [PATCH 04/13] arm: mvebu: a38x: Detect CONFIG_SYS_TCLK from SAR register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/include/mach/soc.h | 13 ++++++++----- include/configs/clearfog.h | 1 - include/configs/controlcenterdc.h | 2 -- include/configs/db-88f6820-amc.h | 2 -- include/configs/db-88f6820-gp.h | 2 -- include/configs/helios4.h | 1 - include/configs/turris_omnia.h | 1 - include/configs/x530.h | 2 -- 8 files changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 3f3b15aa8ab..cb323aa59a7 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -33,11 +33,6 @@ #define MV_88F68XX_A0_ID 0x4 #define MV_88F68XX_B0_ID 0xa -/* TCLK Core Clock definition */ -#ifndef CONFIG_SYS_TCLK -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ -#endif - /* SOC specific definations */ #define INTREG_BASE 0xd0000000 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) @@ -170,6 +165,9 @@ #define BOOT_FROM_SPI 0x32 #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 + +#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \ + 200000000 : 250000000) #elif defined(CONFIG_ARMADA_MSYS) /* SAR values for MSYS */ #define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) @@ -207,4 +205,9 @@ #define BOOT_FROM_SPI 0x3 #endif +/* TCLK Core Clock definition */ +#ifndef CONFIG_SYS_TCLK +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#endif + #endif /* _MVEBU_SOC_H */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index fbdd2f0a244..705217067b3 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -17,7 +17,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h index 171bd189d3b..3b17f75d209 100644 --- a/include/configs/controlcenterdc.h +++ b/include/configs/controlcenterdc.h @@ -20,8 +20,6 @@ * U-Boot into it. */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - #define CONFIG_LOADADDR 1000000 /* diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h index 757fbc0b9bc..83f5b71839e 100644 --- a/include/configs/db-88f6820-amc.h +++ b/include/configs/db-88f6820-amc.h @@ -10,8 +10,6 @@ * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ - /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h index 9a34fa67691..1ab42328fb6 100644 --- a/include/configs/db-88f6820-gp.h +++ b/include/configs/db-88f6820-gp.h @@ -10,8 +10,6 @@ * High Level Configuration Options (easy to change) */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - /* I2C */ #define CONFIG_SYS_I2C_LEGACY #define CONFIG_SYS_I2C_MVTWSI diff --git a/include/configs/helios4.h b/include/configs/helios4.h index 1368080f036..b5814ed55cf 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -17,7 +17,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 2553da12097..8646633ea4c 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -16,7 +16,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/x530.h b/include/configs/x530.h index 515c6e7ff45..64d68276234 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -12,8 +12,6 @@ #define CONFIG_DISPLAY_BOARDINFO_LATE -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - /* * NS16550 Configuration */ From 2ddf554b8648d892efc5733e7486cec5e93dc269 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Jul 2021 14:22:53 +0200 Subject: [PATCH 05/13] arm: mvebu: a37x: Detect CONFIG_SYS_TCLK from SAR register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/include/mach/soc.h | 3 +++ include/configs/db-88f6720.h | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index cb323aa59a7..eb6906ad802 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -145,6 +145,9 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 + +#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ + 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 410a40af3e6..18f4707e6be 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -15,7 +15,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ /* I2C */ #define CONFIG_SYS_I2C_LEGACY From 7dd26bbff8489da75ea2b80f0ebede03ee05de3c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Jul 2021 14:22:54 +0200 Subject: [PATCH 06/13] arm: mvebu: msys: Set CONFIG_SYS_TCLK globally MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This mvebu msys platform always uses fixed 200 MHz TCLK. So specify this CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of manual configuration in every board file. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/include/mach/soc.h | 2 ++ include/configs/crs3xx-98dx3236.h | 1 - include/configs/db-xc3-24g4xg.h | 1 - 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index eb6906ad802..e29c0f32c3d 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -187,6 +187,8 @@ #define BOOT_FROM_NAND 0x1 #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3 + +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ #else /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) diff --git a/include/configs/crs3xx-98dx3236.h b/include/configs/crs3xx-98dx3236.h index e2ba7b81263..3feaa60edad 100644 --- a/include/configs/crs3xx-98dx3236.h +++ b/include/configs/crs3xx-98dx3236.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h index 0e9ccd9b441..f04ae487b76 100644 --- a/include/configs/db-xc3-24g4xg.h +++ b/include/configs/db-xc3-24g4xg.h @@ -11,7 +11,6 @@ */ #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI From 808cea90f5ab86fcdd9b0190fdb4c70cd6a060fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Jul 2021 14:22:55 +0200 Subject: [PATCH 07/13] arm: mvebu: axp: Set CONFIG_SYS_TCLK globally MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This mvebu axp platform always uses fixed 250 MHz TCLK. So specify this CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of manual configuration in every board file. Now every #if-#else case of soc.h file defines CONFIG_SYS_TCLK, so remove useless default CONFIG_SYS_TCLK value from the end of soc.h file. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/include/mach/soc.h | 3 --- include/configs/db-mv784mp-gp.h | 1 - include/configs/ds414.h | 1 - include/configs/maxbcm.h | 1 - include/configs/theadorable.h | 1 - 5 files changed, 7 deletions(-) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index e29c0f32c3d..8e8a4058550 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -208,10 +208,7 @@ #define BOOT_FROM_UART 0x2 #define BOOT_FROM_SPI 0x3 -#endif -/* TCLK Core Clock definition */ -#ifndef CONFIG_SYS_TCLK #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ #endif diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index b3c4079ae13..dd0c3cb7ad9 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -16,7 +16,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* I2C */ #define CONFIG_SYS_I2C_LEGACY diff --git a/include/configs/ds414.h b/include/configs/ds414.h index 4475de24a9d..5d401281c7e 100644 --- a/include/configs/ds414.h +++ b/include/configs/ds414.h @@ -18,7 +18,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* I2C */ #define CONFIG_SYS_I2C_LEGACY diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index c456921ea19..fc2393204be 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -15,7 +15,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* I2C */ #define CONFIG_SYS_I2C_LEGACY diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h index c6a2cfe9310..760713d3ef8 100644 --- a/include/configs/theadorable.h +++ b/include/configs/theadorable.h @@ -15,7 +15,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ /* * The debugging version enables USB support via defconfig. From 8ac303d49f891e11a5c0c4cce7a09a518cfb041b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sat, 31 Jul 2021 14:22:56 +0200 Subject: [PATCH 08/13] arm: kirkwood: Do not overwrite CONFIG_SYS_TCLK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Config option CONFIG_SYS_TCLK is set by kw88f6281.h and kw88f6192.h files to correct SOC/platform value. So do not overwrite it in board config include files. Kirkwood 88F6180 and 88F6192 uses 166 MHz TCLK and Kirkwood 88F6281 uses 200 MHz TCLK. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-kirkwood/include/mach/kw88f6281.h | 2 -- include/configs/lacie_kw.h | 5 ----- include/configs/lsxl.h | 2 -- 3 files changed, 9 deletions(-) diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h index 33e74142078..87406081cf5 100644 --- a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h @@ -15,8 +15,6 @@ #define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE /* TCLK Core Clock definition */ -#ifndef CONFIG_SYS_TCLK #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ -#endif #endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h index 420c1d49b08..88f784f1f0f 100644 --- a/include/configs/lacie_kw.h +++ b/include/configs/lacie_kw.h @@ -39,11 +39,6 @@ #endif #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -/* - * Core clock definition - */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - /* * SDRAM configuration */ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 0c0ab2486e2..a4a4739d0dd 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -13,11 +13,9 @@ #if defined(CONFIG_LSCHLV2) #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg #define CONFIG_MACH_TYPE 3006 -#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */ #elif defined(CONFIG_LSXHL) #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg #define CONFIG_MACH_TYPE 2663 -/* CONFIG_SYS_TCLK is 200000000 by default */ #else #error "unknown board" #endif From 7940d9628a0b70c09efbcb04cb6af10bc7dd9fea Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Sat, 31 Jul 2021 20:29:35 -0700 Subject: [PATCH 09/13] arm: mvebu: sata_mv failed to identify HDDs during cold start During cold start, with some HDDs, mv_sata_identify() does not populate the ID words on the 1st ATA ID command. In fact, the first ATA ID command will only power up the drive, and then the ATA ID command processing is lost in the process. Tests with: - Seagate ST9250320AS 250GB HDD and Seagate ST4000DM004-2CV104 4TB HDD. - Zyxel NSA310S (Kirkwood 88F6702), Marvell Dreamplug (Kirkwood 88F6281), Seagate GoFlex Home (Kirkwood 88F6281), Pogoplug V4 (Kirkwood 88F6192). Observation: - The Seagate ST9250320AS 250GB took about 3 seconds to spin up. - The Seagate ST4000DM004-2CV104 4TB took about 8 seconds to spin up. - mv_sata_identify() did not populate the ID words after the call to mv_ata_exec_ata_cmd_nondma(). - Attempt to insert a long delay of 30 seconds, ie. mdelay(30_000), after the call to ata_wait_register() inside mv_ata_exec_ata_cmd_nondma() did not help with the 4TB drive. The ID words were still empty after that 30s delay. Patch Description: - Added a second ATA ID command in mv_sata_identify(), which will be executed if the 1st ATA ID command did not return with valid ID words. - Use the HDD drive capacity in the ID words as a successful indicator of ATA ID command. - In the scenario where a box is rebooted, the 1st ATA ID command is always successful, so there is no extra time wasted. - In the scenario where a box is cold started, the 1st ATA command is the power up command. The 2nd ATA ID command alleviates the uncertainty of how long we have to wait for the ID words to be populated by the SATA controller. Reviewed-by: Stefan Roese Signed-off-by: Tony Dinh --- drivers/ata/sata_mv.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 1012cb53742..dadb2c7c2e7 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -809,6 +809,7 @@ static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port, static int mv_sata_identify(struct udevice *dev, int port, u16 *id) { struct sata_fis_h2d h2d; + int len; memset(&h2d, 0, sizeof(struct sata_fis_h2d)); @@ -818,8 +819,32 @@ static int mv_sata_identify(struct udevice *dev, int port, u16 *id) /* Give device time to get operational */ mdelay(10); - return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id, - ATA_ID_WORDS * 2, READ_CMD); + /* During cold start, with some HDDs, the first ATA ID command does + * not populate the ID words. In fact, the first ATA ID + * command will only power up the drive, and then the ATA ID command + * processing is lost in the process. + */ + len = mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id, + ATA_ID_WORDS * 2, READ_CMD); + + /* If drive capacity has been filled in, then it was successfully + * identified (the drive has been powered up before, i.e. + * this function is invoked during a reboot) + */ + if (ata_id_n_sectors(id) != 0) + return len; + + /* Issue the 2nd ATA ID command to make sure the ID words are + * populated properly. + */ + mdelay(10); + len = mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id, + ATA_ID_WORDS * 2, READ_CMD); + if (ata_id_n_sectors(id) != 0) + return len; + + printf("Err: Failed to identify SATA device %d\n", port); + return -ENODEV; } static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id) From 4cd61c43fd513a8a0558db2d0d237d612e2d5e73 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 9 Aug 2021 09:53:13 +0200 Subject: [PATCH 10/13] arm: a37xx: pci: Fix handling PIO config error responses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Returning fabricated CRS value (0xFFFF0001) by PCIe Root Complex to OS is allowed only for 4-byte PCI_VENDOR_ID config read request and only when CRSSVE bit in Root Port PCIe device is enabled. In all other error PCIe Root Complex must return all-ones. So implement this logic in pci-aardvark.c driver properly. aardvark HW does not have Root Port PCIe device and U-Boot does not implement emulation of this device. So expect that CRSSVE bit is set as U-Boot can already handle CRS value for PCI_VENDOR_ID config read request. More callers of pci_bus_read_config() function in U-Boot do not check for return value, but check readback value. Therefore always fill readback value in pcie_advk_read_config() function. On error fill all-ones of correct size as it is required for PCIe Root Complex. And also correctly propagates error from failed config write request to return value of pcie_advk_write_config() function. Most U-Boot callers ignores this return value, but it is a good idea to return correct value from function. These issues about return value of failed config read requests, including special handling of CRS were reported by Lorenzo and Bjorn for Linux kernel driver pci-aardvark together with quotes from PCIe r4.0 spec, see details: https://lore.kernel.org/linux-pci/20210624213345.3617-1-pali@kernel.org/t/#u Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- drivers/pci/pci-aardvark.c | 52 +++++++++++++++++++------------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 1b9bae7cca7..815b26162f1 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -177,7 +177,6 @@ #define LINK_MAX_RETRIES 10 #define LINK_WAIT_TIMEOUT 100000 -#define CFG_RD_UR_VAL 0xFFFFFFFF #define CFG_RD_CRS_VAL 0xFFFF0001 /** @@ -263,12 +262,12 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie) * pcie_advk_check_pio_status() - Validate PIO status and get the read result * * @pcie: Pointer to the PCI bus - * @read: Read from or write to configuration space - true(read) false(write) - * @read_val: Pointer to the read result, only valid when read is true + * @allow_crs: Only for read requests, if CRS response is allowed + * @read_val: Pointer to the read result * */ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, - bool read, + bool allow_crs, uint *read_val) { uint reg; @@ -286,22 +285,16 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie, break; } /* Get the read result */ - if (read) + if (read_val) *read_val = advk_readl(pcie, PIO_RD_DATA); /* No error */ strcomp_status = NULL; break; case PIO_COMPLETION_STATUS_UR: - if (read) { - /* For reading, UR is not an error status. */ - *read_val = CFG_RD_UR_VAL; - strcomp_status = NULL; - } else { - strcomp_status = "UR"; - } + strcomp_status = "UR"; break; case PIO_COMPLETION_STATUS_CRS: - if (read) { + if (allow_crs && read_val) { /* For reading, CRS is not an error status. */ *read_val = CFG_RD_CRS_VAL; strcomp_status = NULL; @@ -352,6 +345,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, enum pci_size_t size) { struct pcie_advk *pcie = dev_get_priv(bus); + bool allow_crs; uint reg; int ret; @@ -364,13 +358,17 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, return 0; } + allow_crs = (offset == PCI_VENDOR_ID) && (size == 4); + if (advk_readl(pcie, PIO_START)) { dev_err(pcie->dev, "Previous PIO read/write transfer is still running\n"); - if (offset != PCI_VENDOR_ID) - return -EINVAL; - *valuep = CFG_RD_CRS_VAL; - return 0; + if (allow_crs) { + *valuep = CFG_RD_CRS_VAL; + return 0; + } + *valuep = pci_get_ff(size); + return -EINVAL; } /* Program the control register */ @@ -392,16 +390,20 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, advk_writel(pcie, 1, PIO_START); if (!pcie_advk_wait_pio(pcie)) { - if (offset != PCI_VENDOR_ID) - return -EINVAL; - *valuep = CFG_RD_CRS_VAL; - return 0; + if (allow_crs) { + *valuep = CFG_RD_CRS_VAL; + return 0; + } + *valuep = pci_get_ff(size); + return -EINVAL; } /* Check PIO status and get the read result */ - ret = pcie_advk_check_pio_status(pcie, true, ®); - if (ret) + ret = pcie_advk_check_pio_status(pcie, allow_crs, ®); + if (ret) { + *valuep = pci_get_ff(size); return ret; + } dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, reg); @@ -511,9 +513,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, } /* Check PIO status */ - pcie_advk_check_pio_status(pcie, false, ®); - - return 0; + return pcie_advk_check_pio_status(pcie, false, NULL); } /** From 7e1c0d0dca7fc382bb0a857e15019e7033b80fd2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 9 Aug 2021 17:44:35 +0200 Subject: [PATCH 11/13] arm: mvebu: Hang if ddr3_init() fails MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If ddr3_init() fails then DDR was not initialized and we cannot load and execute U-Boot. We cannot continue, we cannot do anything in this case, so hang. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/spl.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 3b6bc389709..f0cf60bb148 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -345,7 +345,11 @@ void board_init_f(ulong dummy) serdes_phy_config(); /* Setup DDR */ - ddr3_init(); + ret = ddr3_init(); + if (ret) { + debug("ddr3_init() failed: %d\n", ret); + hang(); + } #endif /* Initialize Auto Voltage Scaling */ From 9176f4fa983c188dda9411d99151a8a302f0a1d8 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Mon, 9 Aug 2021 23:10:42 -0700 Subject: [PATCH 12/13] arm: kirkwood: Dockstar: Update board maintainer Change maintainer to me. Eric no longer has this board and wishes to see someone maintaining it actively. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- board/Seagate/dockstar/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/Seagate/dockstar/MAINTAINERS b/board/Seagate/dockstar/MAINTAINERS index f259e58ae6e..0f6243e257c 100644 --- a/board/Seagate/dockstar/MAINTAINERS +++ b/board/Seagate/dockstar/MAINTAINERS @@ -1,5 +1,5 @@ DOCKSTAR BOARD -M: Eric Cooper +M: Tony Dinh S: Maintained F: board/Seagate/dockstar/ F: include/configs/dockstar.h From e21c74f24be5b6d0387d79cb8cf66de0b9b6b0d3 Mon Sep 17 00:00:00 2001 From: Tony Dinh Date: Mon, 9 Aug 2021 23:53:17 -0700 Subject: [PATCH 13/13] arm: kirkwood: Goflex Home: Update board maintainer Change maintainer to me. Suriyan no longer has this board and wishes to see someone maintaining it actively. Signed-off-by: Tony Dinh Reviewed-by: Stefan Roese --- board/Seagate/goflexhome/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/Seagate/goflexhome/MAINTAINERS b/board/Seagate/goflexhome/MAINTAINERS index 6d6a1ff4e35..a71b4ba1fee 100644 --- a/board/Seagate/goflexhome/MAINTAINERS +++ b/board/Seagate/goflexhome/MAINTAINERS @@ -1,5 +1,5 @@ GOFLEXHOME BOARD -M: Suriyan Ramasami +M: Tony Dinh S: Maintained F: board/Seagate/goflexhome/ F: include/configs/goflexhome.h