riscv: dts: sync mpfs-icicle devicetree with linux
The "notable" disappearances are: - the pac193x stanza - there's nothing in mainline linux w.r.t. bindings for this & what is going to appear in mainline linux is going to be incompatible with what is currently in U-Boot. - operating points - these operating points should not be set at the soc.dtsi level as they may not be possible depending on the design programmed to the FPGA - clock output names - there are defines for the clock indices, these should not be needed - the dt maintainers in linux NAKed using defines for IRQ numbers - the qspi nand, which is not part of the icicle's default configuration is removed. Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com> Tested-by: Padmarao Begari <padmarao.begari@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Rick Chen <rick@andestech.com>
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committed by
Leo Yu-Chi Liang

parent
5566cf2a6d
commit
4e99899bd5
@@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2020 Microchip Technology Inc.
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* Padmarao Begari <padmarao.begari@microchip.com>
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* Daire McNamara,<daire.mcnamara@microchip.com>
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* Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
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@@ -45,4 +45,27 @@
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#define CLK_RTCREF 33
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#define CLK_MSSPLL 34
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/* Clock Conditioning Circuitry Clock IDs */
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#define CLK_CCC_PLL0 0
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#define CLK_CCC_PLL1 1
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#define CLK_CCC_DLL0 2
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#define CLK_CCC_DLL1 3
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#define CLK_CCC_PLL0_OUT0 4
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#define CLK_CCC_PLL0_OUT1 5
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#define CLK_CCC_PLL0_OUT2 6
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#define CLK_CCC_PLL0_OUT3 7
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#define CLK_CCC_PLL1_OUT0 8
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#define CLK_CCC_PLL1_OUT1 9
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#define CLK_CCC_PLL1_OUT2 10
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#define CLK_CCC_PLL1_OUT3 11
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#define CLK_CCC_DLL0_OUT0 12
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#define CLK_CCC_DLL0_OUT1 13
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#define CLK_CCC_DLL1_OUT0 14
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#define CLK_CCC_DLL1_OUT1 15
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#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
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