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clk: imx: clk-imx8mn Fix nand and spi clock parent

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The osc_24m is the clock-output-name and not the one that
is used as internal name reference from the strcmp. The clock
that use osc_24m, will not be able to reparent it as they should.
We need anyway register the osc_24m clock fixed factor in the clock
tree.

Fixes: 710c4ffb89 ("clk: imx: clk-imx8mn add gpmi nand clocks")
Fixes: 85b1c11989 ("clk: imx: Add ECSPI to iMX8MN")
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
This commit is contained in:
Michael Trimarchi
2024-07-07 10:19:58 +02:00
committed by Fabio Estevam
parent 5024a96db8
commit 50cdd3f74a
1 changed files with 11 additions and 4 deletions
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15
drivers/clk/imx/clk-imx8mn.c
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@@ -57,15 +57,15 @@ static const char *imx8mn_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", }; "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
#if CONFIG_IS_ENABLED(DM_SPI) #if CONFIG_IS_ENABLED(DM_SPI)
static const char *imx8mn_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", static const char *imx8mn_ecspi1_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", }; "sys_pll2_250m", "audio_pll2_out", };
static const char *imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", static const char *imx8mn_ecspi2_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", }; "sys_pll2_250m", "audio_pll2_out", };
static const char *imx8mn_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", static const char *imx8mn_ecspi3_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll1_40m",
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", "audio_pll2_out", }; "sys_pll2_250m", "audio_pll2_out", };
#endif #endif
@@ -105,7 +105,7 @@ static const char *imx8mn_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sy
static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m", static const char *imx8mn_qspi_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll2_333m", "sys_pll2_500m",
"audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", }; "audio_pll2_out", "sys_pll1_266m", "sys_pll3_out", "sys_pll1_100m", };
static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", static const char * const imx8mn_nand_sels[] = {"clock-osc-24m", "sys_pll2_500m", "audio_pll1_out",
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
"sys_pll2_250m", "video_pll_out", }; "sys_pll2_250m", "video_pll_out", };
@@ -119,7 +119,9 @@ static const char * const imx8mn_usb_phy_sels[] = {"clock-osc-24m", "sys_pll1_10
static int imx8mn_clk_probe(struct udevice *dev) static int imx8mn_clk_probe(struct udevice *dev)
{ {
struct clk osc_24m_clk;
void __iomem *base; void __iomem *base;
int ret;
base = (void *)ANATOP_BASE_ADDR; base = (void *)ANATOP_BASE_ADDR;
@@ -238,6 +240,11 @@ static int imx8mn_clk_probe(struct udevice *dev)
clk_dm(IMX8MN_SYS_PLL2_1000M, clk_dm(IMX8MN_SYS_PLL2_1000M,
imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1)); imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
ret = clk_get_by_name(dev, "osc_24m", &osc_24m_clk);
if (ret)
return ret;
clk_dm(IMX8MN_CLK_24M, dev_get_clk_ptr(osc_24m_clk.dev));
base = dev_read_addr_ptr(dev); base = dev_read_addr_ptr(dev);
if (!base) if (!base)
return -EINVAL; return -EINVAL;