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ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 support

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Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
2008-07-18 12:24:41 +02:00
parent 086511fc96
commit 60204d06ed
4 changed files with 23 additions and 52 deletions
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22
include/asm-ppc/xilinx_irq.h
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@@ -19,18 +19,18 @@
#ifndef XILINX_IRQ_H
#define XILINX_IRQ_H
#define intc XPAR_INTC_0_BASEADDR
#define ISR (intc+(0*4)) /* Interrupt Status Register */
#define IPR (intc+(1*4)) /* Interrupt Pending Register */
#define IER (intc+(2*4)) /* Interrupt Enable Register */
#define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */
#define SIE (intc+(4*4)) /* Set Interrupt Enable bits */
#define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */
#define IVR (intc+(6*4)) /* Interrupt Vector Register */
#define MER (intc+(7*4)) /* Master Enable Register */
#define intc XPAR_INTC_0_BASEADDR
#define ISR (intc + (0 * 4)) /* Interrupt Status Register */
#define IPR (intc + (1 * 4)) /* Interrupt Pending Register */
#define IER (intc + (2 * 4)) /* Interrupt Enable Register */
#define IAR (intc + (3 * 4)) /* Interrupt Acknowledge Register */
#define SIE (intc + (4 * 4)) /* Set Interrupt Enable bits */
#define CIE (intc + (5 * 4)) /* Clear Interrupt Enable bits */
#define IVR (intc + (6 * 4)) /* Interrupt Vector Register */
#define MER (intc + (7 * 4)) /* Master Enable Register */
#define IRQ_MASK(irq) (1<<(irq&0x1f))
#define IRQ_MASK(irq) (1 << (irq & 0x1f))
#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
#define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS
#endif