From 7ddb8d999ac716d0acf5757ae27c12c167d69048 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 2 Mar 2025 21:59:11 +0100
Subject: [PATCH 01/24] arm64: renesas: Add TFA BL31 handoff support on Renesas
 R-Car Gen4

Implement custom U_BOOT_FIT_LOADABLE_HANDLER and armv8_switch_to_el2_prep()
handling in case the TFA was loaded. The loadables handler sets up custom
handoff structure used by Renesas TFA fork in fixed location in DRAM and
indicates the TFA has been loaded.

The custom armv8_switch_to_el2_prep() handling tests whether the TFA BL31
was previously loaded and the custom handoff structure was set up, and if
so, jumps to TFA BL31 which switches from EL3 to EL2 and then returns to
U-Boot just past bl in armv8_switch_to_el2() to finish starting the Linux
kernel.

The jump to Linux through TFA works in such a way that the custom
armv8_switch_to_el2_prep() handler configures the custom handoff structure
such that the target jump address of the TFA BL31 on exit is set to the
armv8_switch_to_el2() + 4, which is just past the bl, and just before the
U-Boot code which implements the Linux kernel boot from either EL. The
registers passed through the TFA BL31 are all the registers passed into
armv8_switch_to_el2_prep() to assure maximum compatibility with all the
boot modes. The armv8_switch_to_el2_prep() handler jumps to the TFA BL31,
which does its setup, drops EL from EL3 to EL2 and finally jumps to the
armv8_switch_to_el2() + 4 entry point, which then allows U-Boot to boot
the Linux kernel the usual way.

In order to build suitable kernel fitImage, build TFA first, upstream
is currently under review:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/35799
Or if necessary, downstream repository:
remote: https://github.com/renesas-rcar/arm-trusted-firmware.git
branch: rcar_gen4_v2.7_v4x

```
$ git clean -fqdx
$ MBEDTLS_DIR=/path/to/mbedtls/ make -j$(nproc) bl31 \
	PLAT=rcar_gen4 ARCH=aarch64 LSI=V4H SPD=none \
	CTX_INCLUDE_AARCH32_REGS=0 MBEDTLS_COMMON_MK=1 \
	PTP_NONSECURE_ACCESS=1 LOG_LEVEL=20 DEBUG=0 \
	ENABLE_ASSERTIONS=0 E=0
```

Build Linux kernel Image and device tree from current mainline Linux
kernel repository, obtain 'Image' and 'r8a779g0-white-hawk.dtb' .

Bundle the files together using provided fit-image.its fitImage description:
```
$ mkimage -f fit-image.its fitImage
```

To start the kernel fiImage generated in previous step, load fitImage
to DRAM and use the 'bootm' command to start it:
=> load 0x58000000 ... fitImage && bootm 0x58000000

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 board/renesas/common/gen4-common.c | 126 +++++++++++++++++++++++++++++
 1 file changed, 126 insertions(+)

diff --git a/board/renesas/common/gen4-common.c b/board/renesas/common/gen4-common.c
index 52a0639073b..f7d129be4c8 100644
--- a/board/renesas/common/gen4-common.c
+++ b/board/renesas/common/gen4-common.c
@@ -7,11 +7,13 @@
 
 #include <asm/arch/renesas.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/armv8/mmu.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/mach-types.h>
 #include <asm/processor.h>
 #include <asm/system.h>
+#include <image.h>
 #include <linux/errno.h>
 
 #define RST_BASE	0xE6160000 /* Domain0 */
@@ -88,3 +90,127 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 {
 	return 0;
 }
+
+/* R-Car Gen4 TFA BL31 handoff structure and handling. */
+struct param_header {
+	u8			type;
+	u8			version;
+	u16			size;
+	u32			attr;
+};
+
+struct tfa_image_info {
+	struct param_header	h;
+	uintptr_t		image_base;
+	u32			image_size;
+	u32			image_max_size;
+};
+
+struct aapcs64_params {
+	u64			arg0;
+	u64			arg1;
+	u64			arg2;
+	u64			arg3;
+	u64			arg4;
+	u64			arg5;
+	u64			arg6;
+	u64			arg7;
+};
+
+struct entry_point_info {
+	struct param_header	h;
+	uintptr_t		pc;
+	u32			spsr;
+	struct aapcs64_params	args;
+};
+
+struct bl2_to_bl31_params_mem {
+	struct tfa_image_info	bl32_image_info;
+	struct tfa_image_info	bl33_image_info;
+	struct entry_point_info	bl33_ep_info;
+	struct entry_point_info	bl32_ep_info;
+};
+
+/* Default jump address, return to U-Boot */
+#define BL33_BASE	0x44100000
+/* Custom parameters address passed to TFA by ICUMXA loader */
+#define PARAMS_BASE	0x46422200
+
+/* Usually such a structure is produced by ICUMXA and passed in at 0x46422200 */
+static const struct bl2_to_bl31_params_mem blinfo_template = {
+	.bl33_ep_info.h.type = 1,	/* PARAM_EP */
+	.bl33_ep_info.h.version = 2,	/* Version 2 */
+	.bl33_ep_info.h.size = sizeof(struct entry_point_info),
+	.bl33_ep_info.h.attr = 0x81,	/* Executable | Non-Secure */
+	.bl33_ep_info.spsr = 0x2c9,	/* Mode=EL2, SP=ELX, Exceptions=OFF */
+	.bl33_ep_info.pc = BL33_BASE,
+
+	.bl33_image_info.h.type = 1,	/* PARAM_EP */
+	.bl33_image_info.h.version = 2,	/* Version 2 */
+	.bl33_image_info.h.size = sizeof(struct image_info),
+	.bl33_image_info.h.attr = 0,
+	.bl33_image_info.image_base = BL33_BASE,
+};
+
+static bool tfa_bl31_image_loaded;
+static ulong tfa_bl31_image_addr;
+
+static void tfa_bl31_image_process(ulong image, size_t size)
+{
+	/* Custom parameters address passed to TFA by ICUMXA loader */
+	struct bl2_to_bl31_params_mem *blinfo = (struct bl2_to_bl31_params_mem *)PARAMS_BASE;
+
+	/* Not in EL3, do nothing. */
+	if (current_el() != 3)
+		return;
+
+	/* Clear a page and copy template */
+	memset((void *)PARAMS_BASE, 0, PAGE_SIZE);
+	memcpy(blinfo, &blinfo_template, sizeof(*blinfo));
+	tfa_bl31_image_addr = image;
+	tfa_bl31_image_loaded = true;
+}
+
+U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TFA_BL31, tfa_bl31_image_process);
+
+void armv8_switch_to_el2_prep(u64 args, u64 mach_nr, u64 fdt_addr,
+			      u64 arg4, u64 entry_point, u64 es_flag)
+{
+	typedef void __noreturn (*image_entry_noargs_t)(void);
+	image_entry_noargs_t image_entry =
+		(image_entry_noargs_t)(void *)tfa_bl31_image_addr;
+	struct bl2_to_bl31_params_mem *blinfo =
+		(struct bl2_to_bl31_params_mem *)PARAMS_BASE;
+
+	/* Not in EL3, do nothing. */
+	if (current_el() != 3)
+		return;
+
+	/*
+	 * Destination address in arch/arm/cpu/armv8/transition.S
+	 * right past the first bl in armv8_switch_to_el2() to let
+	 * the rest of U-Boot pre-Linux code run. The code does run
+	 * without stack pointer!
+	 */
+	const u64 ep = ((u64)(uintptr_t)&armv8_switch_to_el2) + 4;
+
+	/* If TFA BL31 was not part of the fitImage, do regular boot. */
+	if (!tfa_bl31_image_loaded)
+		return;
+
+	/*
+	 * Set up kernel entry point and parameters:
+	 * x0 is FDT address, x1..x3 must be 0
+	 */
+	blinfo->bl33_ep_info.pc = ep;
+	blinfo->bl33_ep_info.args.arg0 = args;
+	blinfo->bl33_ep_info.args.arg1 = mach_nr;
+	blinfo->bl33_ep_info.args.arg2 = fdt_addr;
+	blinfo->bl33_ep_info.args.arg3 = arg4;
+	blinfo->bl33_ep_info.args.arg4 = entry_point;
+	blinfo->bl33_ep_info.args.arg5 = es_flag;
+	blinfo->bl33_image_info.image_base = ep;
+
+	/* Jump to TFA BL31 */
+	image_entry();
+}

From 9292a3047181a62f00c8f97db2b46a146f803bff Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 2 Mar 2025 23:30:02 +0100
Subject: [PATCH 02/24] arm64: renesas: Enable fallback PSCI on Renesas R-Car
 R8A779G0 V4H White Hawk

Enable fallback PSCI provider on Renesas R-Car R8A779G0 V4H White Hawk board.

This fallback PSCI provider provides basic PSCI interface which can be used
by the Linux kernel, but does not provide support for bringing up additional
CPU cores or any other functionality, except for SoC level reset.

This fallback PSCI provider is intended as a fallback in case a proper PSCI
provider is not started before the Linux kernel is started. Linux kernel on
ARMv8a will fail to boot in case a PSCI provider is not available, and this
basic fallback PSCI provider assures such a boot failure cannot occur, even
if that means the system will boot in degraded mode with only one CPU core
available, that is still sufficient to perform recovery.

In the common case, a proper PSCI provider should be started as part of
the Linux kernel fitImage, as the BL31 loadable, and replace this basic
fallback PSCI provider before the Linux kernel is started.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 configs/r8a779g0_whitehawk_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig
index b49a81dcd49..8dcf8e35ee0 100644
--- a/configs/r8a779g0_whitehawk_defconfig
+++ b/configs/r8a779g0_whitehawk_defconfig
@@ -3,6 +3,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_RCAR_GEN4=y
+CONFIG_ARM_SMCCC=y
+CONFIG_ARMV8_PSCI=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0xFFFE0000
 CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a779g0-white-hawk"

From 56490b1e0121112072392c41de419d91f8258dc2 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 16 Mar 2025 14:50:41 +0100
Subject: [PATCH 03/24] ARM: renesas: Drop stale common Makefile description

Remove stale Makefile description, this used to be valid for the
original Makefile from which the common Makefile was made generic,
but is no longer applicable to the common Makefile.

Fixes: c7d2d7f90a91 ("ARM: renesas: Simplify board Makefiles")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 board/renesas/common/Makefile | 2 --
 1 file changed, 2 deletions(-)

diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile
index 347be5cc93c..5e51b691178 100644
--- a/board/renesas/common/Makefile
+++ b/board/renesas/common/Makefile
@@ -1,6 +1,4 @@
 #
-# board/renesas/whitehawk/Makefile
-#
 # Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
 #
 # SPDX-License-Identifier: GPL-2.0+

From 92659829aa19024c8e6b880efdb562678b0b743f Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 16 Mar 2025 14:51:09 +0100
Subject: [PATCH 04/24] arm64: renesas: Drop stale R-Car V4H SPL implementation
 description

The R-Car V4H SPL implementation was originally running on the Cortex-R52
core, but this is no longer the case. Majority of the SPL now runs on the
Cortex-A76 core. Drop the stale description.

Fixes: ec53fdee5bec ("arm64: renesas: Add Renesas R-Car V4H SPL implementation")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 board/renesas/common/gen4-spl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/renesas/common/gen4-spl.c b/board/renesas/common/gen4-spl.c
index e46ef0a3075..ebfefab7253 100644
--- a/board/renesas/common/gen4-spl.c
+++ b/board/renesas/common/gen4-spl.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * R-Car Gen4 Cortex-R52 SPL
+ * R-Car Gen4 SPL
  *
  * Copyright (C) 2024 Marek Vasut <marek.vasut+renesas@mailbox.org>
  */

From 15111aeb9c7ac7a8cbe6444090098a440d2bbb4f Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 16 Mar 2025 14:51:38 +0100
Subject: [PATCH 05/24] arm64: dts: renesas: Make OTP available in SPL on
 R8A779G0 V4H

The DBSC5 DRAM controller driver needs access to OTP fuses to discern
Renesas R-Car V4H-3, V4H-5 and V4H-7 SoC variants based on OTP fuse
programming. Make OTP block DT node available in U-Boot SPL DT so the
DBSC5 driver can determine its base address and read out the OTP fuses.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 arch/arm/dts/r8a779g0-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/r8a779g0-u-boot.dtsi b/arch/arm/dts/r8a779g0-u-boot.dtsi
index 10051c9dbfe..cc9d99b0f34 100644
--- a/arch/arm/dts/r8a779g0-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-u-boot.dtsi
@@ -147,6 +147,10 @@
 	bootph-all;
 };
 
+&otp {
+	bootph-all;
+};
+
 &pfc {
 	bootph-all;
 };

From 6c219e184f9efffed88dbd82dac94c24ebb00347 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 16 Mar 2025 14:51:39 +0100
Subject: [PATCH 06/24] ram: renesas: dbsc5: Fix bitrate MD pin parsing

Fix copy paste error in MD pin handling for 5500 Mbps and 4800 Mbps case,
each should be handled by MD[19,17] == 2 and MD[19,17] == 3 respectively.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 drivers/ram/renesas/dbsc5/dram.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index 210a68f6496..939775d4d16 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -4450,10 +4450,10 @@ static int renesas_dbsc5_dram_probe(struct udevice *dev)
 	} else if (md == 1) {
 		priv->ddr_mbps = 6000;
 		priv->ddr_mbpsdiv = 1;
-	} else if (md == 1) {
+	} else if (md == 2) {
 		priv->ddr_mbps = 5500;
 		priv->ddr_mbpsdiv = 1;
-	} else if (md == 1) {
+	} else if (md == 3) {
 		priv->ddr_mbps = 4800;
 		priv->ddr_mbpsdiv = 1;
 	}

From 9a106f15fac20790c272023845ec10e46281bef2 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 16 Mar 2025 14:51:40 +0100
Subject: [PATCH 07/24] ram: renesas: dbsc5: Fix JS1 index calculation

The JS1 index is calculated correctly, but the limiter cannot
be the max() function because the index should be lower than
JS1_USABLEC_SPEC_HI and the max() function would unconditionally
override the JS1 index to JS1_USABLEC_SPEC_HI. Use clamp() to
limit the JS1 index instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 drivers/ram/renesas/dbsc5/dram.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index 939775d4d16..289d1224673 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -2192,7 +2192,7 @@ static void dbsc5_ddrtbl_calc(struct renesas_dbsc5_dram_priv *priv)
 		if (js1[i].fx3 * 2 * priv->ddr_mbpsdiv >= priv->ddr_mbps * 3)
 			break;
 
-	priv->js1_ind = max(i, JS1_USABLEC_SPEC_HI);
+	priv->js1_ind = clamp(i, 0, JS1_USABLEC_SPEC_HI);
 
 	priv->RL = js1[priv->js1_ind].RLset1;
 	priv->WL = js1[priv->js1_ind].WLsetA;

From da7662f6bb02806690dac6b25a6e582ed21254d0 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 16 Mar 2025 14:51:41 +0100
Subject: [PATCH 08/24] ram: renesas: dbsc5: Fix DBTR11 calculation

Reinstate missing increment by two in DBTR11 calculation based
on the original DBSC5 initialization code rev.0.80. The original
code did ... ODTLon - (js2[JS2_tODTon_min] - 1) + 1 , which was
incorrectly converted into ODTLon - js2[JS2_tODTon_min], but
should have been converted to ODTLon - js2[JS2_tODTon_min] + 2.
Add the missing +2 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 drivers/ram/renesas/dbsc5/dram.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index 289d1224673..0616658e9f8 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -2635,7 +2635,7 @@ static void dbsc5_dbsc_regset(struct udevice *dev)
 	 */
 	dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(11),
 			priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] -
-			js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min]);
+			js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min] + 2);
 
 	/* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */
 	dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(12),

From 9ae94d2aedbbd38dc681f89b82f8ce4f2c3ee387 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 16 Mar 2025 14:51:42 +0100
Subject: [PATCH 09/24] ram: renesas: dbsc5: Synchronize initialization code to
 rev.1.10

Update the DRAM initialization code to match DBSC5 initialization code
rev.1.10 , which is currently the latest version available. This makes
DRAM initialization operational on Renesas R-Car V4H R8A779G0 rev.3.0.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 drivers/ram/renesas/dbsc5/dram.c | 67 +++++++++++++++-----------------
 1 file changed, 31 insertions(+), 36 deletions(-)

diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index 0616658e9f8..1b70faff7f7 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -220,6 +220,7 @@ static const u16 jedec_spec2_tRFC_ab[] = {
 #define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS		DDR_REGDEF(0x00, 0x09, 0x103F)
 #define PHY_WDQLVL_STATUS_OBS			DDR_REGDEF(0x00, 0x20, 0x1043)
 #define PHY_DATA_DC_CAL_START			DDR_REGDEF(0x18, 0x01, 0x104D)
+#define PHY_SLV_DLY_CTRL_GATE_DISABLE		DDR_REGDEF(0x10, 0x01, 0x104E)
 #define PHY_REGULATOR_EN_CNT			DDR_REGDEF(0x18, 0x06, 0x1050)
 #define PHY_VREF_INITIAL_START_POINT		DDR_REGDEF(0x00, 0x09, 0x1055)
 #define PHY_VREF_INITIAL_STOP_POINT		DDR_REGDEF(0x10, 0x09, 0x1055)
@@ -469,7 +470,7 @@ static const u32 DDR_PHY_SLICE_REGSET_V4H[DDR_PHY_SLICE_REGSET_NUM_V4H] = {
 	0x00000000, 0x00500050, 0x00500050, 0x00500050,
 	0x00500050, 0x0D000050, 0x10100004, 0x06102010,
 	0x61619041, 0x07097000, 0x00644180, 0x00803280,
-	0x00808001, 0x13010100, 0x02000016, 0x10001003,
+	0x00808001, 0x13010101, 0x02000016, 0x10001003,
 	0x06093E42, 0x0F063D01, 0x011700C8, 0x04100140,
 	0x00000100, 0x000001D1, 0x05000068, 0x00030402,
 	0x01400000, 0x80800300, 0x00160010, 0x76543210,
@@ -512,8 +513,8 @@ static const u32 DDR_PHY_ADR_G_REGSET_V4H[DDR_PHY_ADR_G_REGSET_NUM_V4H] = {
 	0x00040101, 0x00000000, 0x00000000, 0x00000064,
 	0x00000000, 0x00000000, 0x39421B42, 0x00010124,
 	0x00520052, 0x00000052, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x00000000,
-	0x00000000, 0x00000000, 0x00000000, 0x07030102,
+	0x00010001, 0x00000000, 0x00000000, 0x00010001,
+	0x00000000, 0x00000000, 0x00010001, 0x07030102,
 	0x01030307, 0x00000054, 0x00004096, 0x08200820,
 	0x08200820, 0x08200820, 0x08200820, 0x00000820,
 	0x004103B8, 0x0000003F, 0x000C0006, 0x00000000,
@@ -1294,7 +1295,7 @@ static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_572 = {
 };
 
 static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_572 = {
-	PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x03
+	PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02
 };
 
 static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_400[] = {
@@ -1713,14 +1714,17 @@ static void dbsc5_clk_wait_dbpdstat1(struct udevice *dev, u32 status)
 {
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
-	u32 i, ch, reg;
+	u32 i, ch, chk, reg;
 
 	for (i = 0; i < 2; i++) {
 		do {
 			reg = status;
-			r_foreach_vch(dev, ch)
+			chk = 0;
+			r_foreach_vch(dev, ch) {
 				reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT1(ch));
-		} while (reg != status);
+				chk |= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch));
+			}
+		} while (reg != status && !(chk & BIT(0)));
 	}
 }
 
@@ -3491,13 +3495,10 @@ static void dbsc5_manual_write_dca(struct udevice *dev)
 {
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 	const u32 rank = priv->ch_have_this_cs[1] ? 0x2 : 0x1;
-	u32 slv_dly_center[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-	u32 slv_dly_center_cyc;
-	u32 slv_dly_center_dly;
+	u32 phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+	u32 phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT];
 	u32 slv_dly_min[DRAM_CH_CNT][SLICE_CNT];
 	u32 slv_dly_max[DRAM_CH_CNT][SLICE_CNT];
-	u32 slv_dly_min_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-	u32 slv_dly_max_tmp[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
 	u32 phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT];
 	u32 phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT];
 	u32 phy_dcc_code_mid;
@@ -3521,18 +3522,9 @@ static void dbsc5_manual_write_dca(struct udevice *dev)
 		dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs);
 		r_foreach_vch(dev, ch) {
 			for (slice = 0; slice < SLICE_CNT; slice++) {
-				slv_dly_center[ch][cs][slice] =
-					dbsc5_ddr_getval_slice(dev, ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY);
-				slv_dly_center_cyc = slv_dly_center[ch][cs][slice] & 0x180;
-				slv_dly_center_dly = slv_dly_center[ch][cs][slice] & 0x7F;
-				slv_dly_min_tmp[ch][cs][slice] =
-					slv_dly_center_cyc |
-					(slv_dly_center_dly * ratio_min / ratio_min_div);
-				slv_dly_max_tmp[ch][cs][slice] = slv_dly_center_cyc;
-				if ((slv_dly_center_dly * ratio_max) > (0x7F * ratio_max_div))
-					slv_dly_max_tmp[ch][cs][slice] |= 0x7F;
-				else
-					slv_dly_max_tmp[ch][cs][slice] |= slv_dly_center_dly * ratio_max / ratio_max_div;
+				phy_slv_dly[ch][cs][slice] =
+					dbsc5_ddr_getval_slice(dev, ch, slice,
+							       PHY_CLK_WRDQS_SLAVE_DELAY);
 			}
 		}
 	}
@@ -3540,22 +3532,22 @@ static void dbsc5_manual_write_dca(struct udevice *dev)
 	r_foreach_vch(dev, ch) {
 		for (slice = 0; slice < SLICE_CNT; slice++) {
 			if (rank == 0x2) {
-				if (slv_dly_max_tmp[ch][0][slice] < slv_dly_max_tmp[ch][1][slice])
-					slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][1][slice];
-				else
-					slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice];
-
-				if (slv_dly_min_tmp[ch][0][slice] < slv_dly_min_tmp[ch][1][slice])
-					slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice];
-				else
-					slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][1][slice];
+				/* Calculate average between ranks */
+				phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] +
+							      phy_slv_dly[ch][1][slice]) / 2;
 			} else {
-				slv_dly_max[ch][slice] = slv_dly_max_tmp[ch][0][slice];
-				slv_dly_min[ch][slice] = slv_dly_min_tmp[ch][0][slice];
+				phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice];
 			}
+			/* Determine the search range */
+			slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_min / ratio_min_div;
+			slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_max / ratio_max_div;
+			if (slv_dly_max[ch][slice] > 0x7F)
+				slv_dly_max[ch][slice] = 0x7F;
 		}
 	}
 
+	dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x1);
+
 	for (i = 0; i <= 0x7F; i++) {
 		r_foreach_vch(dev, ch) {
 			for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -3621,13 +3613,16 @@ static void dbsc5_manual_write_dca(struct udevice *dev)
 			for (slice = 0; slice < SLICE_CNT; slice++) {
 				dbsc5_ddr_setval_slice(dev, ch, slice,
 						       PHY_CLK_WRDQS_SLAVE_DELAY,
-						       slv_dly_center[ch][cs][slice]);
+						       phy_slv_dly[ch][cs][slice]);
 				dbsc5_ddr_setval_slice(dev, ch, slice,
 						       SC_PHY_WCK_CALC, 0x1);
 				dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1);
 			}
 		}
 	}
+
+	dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x0);
+
 	dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x1);
 
 	r_foreach_vch(dev, ch) {

From 74e28113618f362d2f8ee2edd874fd1789efceb7 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 16 Mar 2025 14:51:43 +0100
Subject: [PATCH 10/24] ram: renesas: dbsc5: Add V4H-3/V4H-5/V4H-7 OTP based
 detection

Add auto-detection and handling of Renesas R-Car V4H-3 and V4H-5
in addition to V4H-7 SoC variants based on OTP fuse programming.
The V4H-3 and V4H-5 variants have reduced DRAM frequency options.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 drivers/ram/renesas/dbsc5/dbsc5.c |  3 +-
 drivers/ram/renesas/dbsc5/dbsc5.h |  1 +
 drivers/ram/renesas/dbsc5/dram.c  | 48 ++++++++++++++++++++-----------
 3 files changed, 35 insertions(+), 17 deletions(-)

diff --git a/drivers/ram/renesas/dbsc5/dbsc5.c b/drivers/ram/renesas/dbsc5/dbsc5.c
index d24b7c5c30a..4cbc6aeda43 100644
--- a/drivers/ram/renesas/dbsc5/dbsc5.c
+++ b/drivers/ram/renesas/dbsc5/dbsc5.c
@@ -59,7 +59,8 @@ int renesas_dbsc5_bind(struct udevice *dev)
 
 struct renesas_dbsc5_data r8a779g0_dbsc5_data = {
 	.clock_node = "renesas,r8a779g0-cpg-mssr",
-	.reset_node = "renesas,r8a779g0-rst"
+	.reset_node = "renesas,r8a779g0-rst",
+	.otp_node = "renesas,r8a779g0-otp",
 };
 
 static const struct udevice_id renesas_dbsc5_ids[] = {
diff --git a/drivers/ram/renesas/dbsc5/dbsc5.h b/drivers/ram/renesas/dbsc5/dbsc5.h
index c410eb0c5ed..bf22fcb8c11 100644
--- a/drivers/ram/renesas/dbsc5/dbsc5.h
+++ b/drivers/ram/renesas/dbsc5/dbsc5.h
@@ -23,6 +23,7 @@
 struct renesas_dbsc5_data {
 	const char		*clock_node;
 	const char		*reset_node;
+	const char		*otp_node;
 };
 
 #endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */
diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index 1b70faff7f7..c5c57858aac 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -4364,16 +4364,20 @@ static int renesas_dbsc5_dram_probe(struct udevice *dev)
 {
 #define RST_MODEMR0			0x0
 #define RST_MODEMR1			0x4
+#define OTP_MONITOR17			0x1144
 	struct renesas_dbsc5_data *data = (struct renesas_dbsc5_data *)dev_get_driver_data(dev);
 	ofnode cnode = ofnode_by_compatible(ofnode_null(), data->clock_node);
 	ofnode rnode = ofnode_by_compatible(ofnode_null(), data->reset_node);
+	ofnode onode = ofnode_by_compatible(ofnode_null(), data->otp_node);
 	struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev);
 	void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET;
 	void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET;
 	phys_addr_t rregs = ofnode_get_addr(rnode);
 	const u32 modemr0 = readl(rregs + RST_MODEMR0);
 	const u32 modemr1 = readl(rregs + RST_MODEMR1);
-	u32 breg, reg, md, sscg;
+	phys_addr_t oregs = ofnode_get_addr(onode);
+	const u32 otpmon17 = readl(oregs + OTP_MONITOR17);
+	u32 breg, reg, md, sscg, product;
 	u32 ch, cs;
 
 	/* Get board data */
@@ -4428,29 +4432,41 @@ static int renesas_dbsc5_dram_probe(struct udevice *dev)
 
 	/* Decode DDR operating frequency from MD[37:36,19,17] pins */
 	md = ((modemr0 & BIT(19)) >> 18) | ((modemr0 & BIT(17)) >> 17);
+	product = otpmon17 & 0xff;
 	sscg = (modemr1 >> 4) & 0x03;
 	if (sscg == 2) {
 		printf("MD[37:36] setting 0x%x not supported!", sscg);
 		hang();
 	}
 
-	if (md == 0) {
-		if (sscg == 0) {
-			priv->ddr_mbps = 6400;
-			priv->ddr_mbpsdiv = 1;
-		} else {
-			priv->ddr_mbps = 19000;
-			priv->ddr_mbpsdiv = 3;
-		}
-	} else if (md == 1) {
-		priv->ddr_mbps = 6000;
-		priv->ddr_mbpsdiv = 1;
-	} else if (md == 2) {
-		priv->ddr_mbps = 5500;
-		priv->ddr_mbpsdiv = 1;
-	} else if (md == 3) {
+	if (product == 0x2) {			/* V4H-3 */
 		priv->ddr_mbps = 4800;
 		priv->ddr_mbpsdiv = 1;
+	} else if (product == 0x1) {		/* V4H-5 */
+		if (md == 3)
+			priv->ddr_mbps = 4800;
+		else
+			priv->ddr_mbps = 5000;
+		priv->ddr_mbpsdiv = 1;
+	} else {				/* V4H-7 */
+		if (md == 0) {
+			if (sscg == 0) {
+				priv->ddr_mbps = 6400;
+				priv->ddr_mbpsdiv = 1;
+			} else {
+				priv->ddr_mbps = 19000;
+				priv->ddr_mbpsdiv = 3;
+			}
+		} else if (md == 1) {
+			priv->ddr_mbps = 6000;
+			priv->ddr_mbpsdiv = 1;
+		} else if (md == 2) {
+			priv->ddr_mbps = 5500;
+			priv->ddr_mbpsdiv = 1;
+		} else if (md == 3) {
+			priv->ddr_mbps = 4800;
+			priv->ddr_mbpsdiv = 1;
+		}
 	}
 
 	priv->ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2,

From 885fd621a309a2c3f8e8d41bdc8ff893221dc478 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sun, 16 Mar 2025 14:51:44 +0100
Subject: [PATCH 11/24] ram: renesas: dbsc5: Make struct
 renesas_dbsc5_board_config public

Make struct renesas_dbsc5_board_config {} definition public via
include/dbsc5.h, so this structure can be defined in board files
and passed into the DBSC5 DRAM driver by overriding weak function
dbsc5_get_board_data() on board level.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
 drivers/ram/renesas/dbsc5/dram.c | 48 +--------------------------
 include/dbsc5.h                  | 56 ++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+), 47 deletions(-)
 create mode 100644 include/dbsc5.h

diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c
index c5c57858aac..6f78afb0ab5 100644
--- a/drivers/ram/renesas/dbsc5/dram.c
+++ b/drivers/ram/renesas/dbsc5/dram.c
@@ -4,6 +4,7 @@
  */
 
 #include <asm/io.h>
+#include <dbsc5.h>
 #include <dm.h>
 #include <errno.h>
 #include <hang.h>
@@ -12,13 +13,6 @@
 #include <linux/sizes.h>
 #include "dbsc5.h"
 
-/* The number of channels V4H has */
-#define DRAM_CH_CNT			4
-/* The number of slices V4H has */
-#define SLICE_CNT			2
-/* The number of chip select V4H has */
-#define CS_CNT				2
-
 /* Number of array elements in Data Slice */
 #define DDR_PHY_SLICE_REGSET_SIZE_V4H	0x100
 /* Number of array elements in Data Slice */
@@ -1375,46 +1369,6 @@ static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = {
 
 #define CLK_DIV(a, diva, b, divb)	(((a) * (divb)) / ((b) * (diva)))
 
-struct renesas_dbsc5_board_config {
-	/* Channels in use */
-	u8 bdcfg_phyvalid;
-	/* Read vref (SoC) training range */
-	u32 bdcfg_vref_r;
-	/* Write vref (MR14, MR15) training range */
-	u16 bdcfg_vref_w;
-	/* CA vref (MR12) training range */
-	u16 bdcfg_vref_ca;
-	/* RFM required check */
-	bool bdcfg_rfm_chk;
-
-	/* Board parameter about channels */
-	struct {
-		/*
-		 * 0x00:  4Gb dual channel die /  2Gb single channel die
-		 * 0x01:  6Gb dual channel die /  3Gb single channel die
-		 * 0x02:  8Gb dual channel die /  4Gb single channel die
-		 * 0x03: 12Gb dual channel die /  6Gb single channel die
-		 * 0x04: 16Gb dual channel die /  8Gb single channel die
-		 * 0x05: 24Gb dual channel die / 12Gb single channel die
-		 * 0x06: 32Gb dual channel die / 16Gb single channel die
-		 * 0x07: 24Gb single channel die
-		 * 0x08: 32Gb single channel die
-		 * 0xFF: NO_MEMORY
-		 */
-		u8 bdcfg_ddr_density[CS_CNT];
-		/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
-		u32 bdcfg_ca_swap;
-		/* SoC dqsX([1][0]) -> MEM dqsY: */
-		u8 bdcfg_dqs_swap;
-		/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm:  (8 means DM) */
-		u32 bdcfg_dq_swap[SLICE_CNT];
-		/* SoC dm -> MEM dqY/dm:  (8 means DM) */
-		u8 bdcfg_dm_swap[SLICE_CNT];
-		/* SoC ckeX([1][0]) -> MEM csY */
-		u8 bdcfg_cs_swap;
-	} ch[4];
-};
-
 struct renesas_dbsc5_dram_priv {
 	void __iomem	*regs;
 	void __iomem	*cpg_regs;
diff --git a/include/dbsc5.h b/include/dbsc5.h
new file mode 100644
index 00000000000..cec937d89e7
--- /dev/null
+++ b/include/dbsc5.h
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024-2025 Renesas Electronics Corp.
+ */
+
+#ifndef __INCLUDE_DBSC5_H__
+#define __INCLUDE_DBSC5_H__
+
+/* The number of channels V4H has */
+#define DRAM_CH_CNT			4
+/* The number of slices V4H has */
+#define SLICE_CNT			2
+/* The number of chip select V4H has */
+#define CS_CNT				2
+
+struct renesas_dbsc5_board_config {
+	/* Channels in use */
+	u8 bdcfg_phyvalid;
+	/* Read vref (SoC) training range */
+	u32 bdcfg_vref_r;
+	/* Write vref (MR14, MR15) training range */
+	u16 bdcfg_vref_w;
+	/* CA vref (MR12) training range */
+	u16 bdcfg_vref_ca;
+	/* RFM required check */
+	bool bdcfg_rfm_chk;
+
+	/* Board parameter about channels */
+	struct {
+		/*
+		 * 0x00:  4Gb dual channel die /  2Gb single channel die
+		 * 0x01:  6Gb dual channel die /  3Gb single channel die
+		 * 0x02:  8Gb dual channel die /  4Gb single channel die
+		 * 0x03: 12Gb dual channel die /  6Gb single channel die
+		 * 0x04: 16Gb dual channel die /  8Gb single channel die
+		 * 0x05: 24Gb dual channel die / 12Gb single channel die
+		 * 0x06: 32Gb dual channel die / 16Gb single channel die
+		 * 0x07: 24Gb single channel die
+		 * 0x08: 32Gb single channel die
+		 * 0xFF: NO_MEMORY
+		 */
+		u8 bdcfg_ddr_density[CS_CNT];
+		/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
+		u32 bdcfg_ca_swap;
+		/* SoC dqsX([1][0]) -> MEM dqsY: */
+		u8 bdcfg_dqs_swap;
+		/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm:  (8 means DM) */
+		u32 bdcfg_dq_swap[SLICE_CNT];
+		/* SoC dm -> MEM dqY/dm:  (8 means DM) */
+		u8 bdcfg_dm_swap[SLICE_CNT];
+		/* SoC ckeX([1][0]) -> MEM csY */
+		u8 bdcfg_cs_swap;
+	} ch[4];
+};
+
+#endif	/* __INCLUDE_DBSC5_H__ */

From 60ea8a94d60eeb296b1631f3914d11ef0621b1dc Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@mailbox.org>
Date: Sat, 8 Mar 2025 21:49:42 +0100
Subject: [PATCH 12/24] net: miiphybb: Convert documentation to rst

Convert the current miiphybb documentation to rst. Rename
the README.bitbangMII to bitbangmii.rst in the process.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 doc/README.bitbangMII      | 39 --------------------
 doc/develop/bitbangmii.rst | 75 ++++++++++++++++++++++++++++++++++++++
 doc/develop/index.rst      |  1 +
 3 files changed, 76 insertions(+), 39 deletions(-)
 delete mode 100644 doc/README.bitbangMII
 create mode 100644 doc/develop/bitbangmii.rst

diff --git a/doc/README.bitbangMII b/doc/README.bitbangMII
deleted file mode 100644
index 05ab20376f3..00000000000
--- a/doc/README.bitbangMII
+++ /dev/null
@@ -1,39 +0,0 @@
-This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to
-support an arbitrary number of mii buses. This feature is useful when your
-board uses different mii buses for different phys and all (or a part) of these
-buses are implemented via bit-banging mode.
-
-The driver requires that the following macros should be defined into the board
-configuration file:
-
-CONFIG_BITBANGMII	- Enable the miiphybb driver
-
-The board code needs to fill the bb_miiphy_buses[] array with a record for
-each required bus and declare the bb_miiphy_buses_num variable with the
-number of mii buses. The record (struct bb_miiphy_bus) has the following
-fields/callbacks (see miiphy.h for details):
-
-char name[]	       - The symbolic name that must be equal to the MII bus
-			 registered name
-int (*init)()	       - Initialization function called at startup time (just
-			 before the Ethernet initialization)
-int (*mdio_active)()   - Activate the MDIO pin as output
-int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
-int (*set_mdio)()      - Write the MDIO pin
-int (*get_mdio)()      - Read the MDIO pin
-int (*set_mdc)()       - Write the MDC pin
-int (*delay)()	       - Delay function
-void *priv	       - Private data used by board specific code
-
-The board code will look like:
-
-struct bb_miiphy_bus bb_miiphy_buses[] = {
- { .name = "miibus#1", .init = b1_init, .mdio_active = b1_mdio_active, ... },
- { .name = "miibus#2", .init = b2_init, .mdio_active = b2_mdio_active, ... },
- ...
-};
-int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
-			  sizeof(bb_miiphy_buses[0]);
-
-2009 Industrie Dial Face S.p.A.
-     Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
diff --git a/doc/develop/bitbangmii.rst b/doc/develop/bitbangmii.rst
new file mode 100644
index 00000000000..35a4a0cb7f9
--- /dev/null
+++ b/doc/develop/bitbangmii.rst
@@ -0,0 +1,75 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+.. Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>, Industrie Dial Face S.p.A., 2009
+
+Bit-banged MII bus support
+==========================
+
+The miiphybb ( Bit-banged MII bus driver ) supports an arbitrary number of
+MII buses. This feature is useful when a driver uses different MII buses for
+different PHYs and all (or a part) of these buses are implemented via
+bit-banging mode.
+
+The driver requires that the following macro is defined in the board
+configuration file:
+
+* CONFIG_BITBANGMII - Enable the miiphybb driver
+
+The driver code needs to allocate a regular MDIO device using mdio_alloc()
+and assign .read and .write accessors which wrap bb_miiphy_read() and
+bb_miiphy_write() functions respectively. The bb_miiphy_read() and
+bb_miiphy_write() functions take a pointer to a callback structure,
+struct bb_miiphy_bus_ops. The struct bb_miiphy_bus_ops has the following
+fields/callbacks (see miiphy.h for details):
+
+.. code-block:: c
+
+    int (*mdio_active)()   // Activate the MDIO pin as output
+    int (*mdio_tristate)() // Activate the MDIO pin as input/tristate pin
+    int (*set_mdio)()      // Write the MDIO pin
+    int (*get_mdio)()      // Read the MDIO pin
+    int (*set_mdc)()       // Write the MDC pin
+    int (*delay)()         // Delay function
+
+The driver code will look like:
+
+.. code-block:: c
+
+    static const struct bb_miiphy_bus_ops ravb_bb_miiphy_bus_ops = {
+        .mdio_active      = ravb_bb_mdio_active,
+        .mdio_tristate    = ravb_bb_mdio_tristate,
+        .set_mdio         = ravb_bb_set_mdio,
+        .get_mdio         = ravb_bb_get_mdio,
+        .set_mdc          = ravb_bb_set_mdc,
+        .delay            = ravb_bb_delay,
+    };
+
+    static int ravb_bb_miiphy_read(struct mii_dev *miidev, int addr,
+                                   int devad, int reg)
+    {
+        return bb_miiphy_read(miidev, &ravb_bb_miiphy_bus_ops,
+                              addr, devad, reg);
+    }
+
+    static int ravb_bb_miiphy_write(struct mii_dev *miidev, int addr,
+                                    int devad, int reg, u16 value)
+    {
+        return bb_miiphy_write(miidev, &ravb_bb_miiphy_bus_ops,
+                               addr, devad, reg, value);
+    }
+
+    static int ravb_probe(struct udevice *dev)
+    {
+        struct mii_dev *mdiodev;
+    ...
+        mdiodev = mdio_alloc();
+        if (!mdiodev)
+            return -ENOMEM;
+
+        mdiodev->read = ravb_bb_miiphy_read;
+        mdiodev->write = ravb_bb_miiphy_write;
+        mdiodev->priv = eth;
+        snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
+
+        ret = mdio_register(mdiodev);
+    ...
+    }
diff --git a/doc/develop/index.rst b/doc/develop/index.rst
index d9f2a838207..c907f8c9c2c 100644
--- a/doc/develop/index.rst
+++ b/doc/develop/index.rst
@@ -9,6 +9,7 @@ General
 .. toctree::
    :maxdepth: 1
 
+   bitbangmii
    board_best_practices
    codingstyle
    designprinciples

From 214a87757ac70d5b6523142136678a53e7d4232f Mon Sep 17 00:00:00 2001
From: Sam Edwards <cfsworks@gmail.com>
Date: Sat, 15 Mar 2025 15:18:09 -0700
Subject: [PATCH 13/24] arm: riscv: efi: Export _start symbol from crt0_*_efi
 stubs

While the _start label is only intended for use locally to populate the
(hand-written) PE header, the linker script includes ENTRY(_start) which
designates it as the entry point in the output ELF, resulting in linker
warnings under some linkers (e.g. LLVM's lld) due to _start not being a
globally-visible symbol. Since  ELF is only an intermediary build
format, and the aforementioned PE header correctly points to _start, the
ENTRY(_start) directive could easily be removed to silence this warning.

However, since some developers who are debugging EFI by analyzing the
intermediary ELF may appreciate having correct entry-point information,
this patch instead promotes the _start labels to global symbols,
silencing the linker warning and making the intermediary ELF reflect the
true entry point.

This patch doesn't affect the final output binaries in any way.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
---
 arch/arm/lib/crt0_aarch64_efi.S | 1 +
 arch/arm/lib/crt0_arm_efi.S     | 1 +
 arch/riscv/lib/crt0_riscv_efi.S | 1 +
 3 files changed, 3 insertions(+)

diff --git a/arch/arm/lib/crt0_aarch64_efi.S b/arch/arm/lib/crt0_aarch64_efi.S
index e21b54fdbcb..003d5f83041 100644
--- a/arch/arm/lib/crt0_aarch64_efi.S
+++ b/arch/arm/lib/crt0_aarch64_efi.S
@@ -144,6 +144,7 @@ section_table:
 		 IMAGE_SCN_CNT_INITIALIZED_DATA)
 
 	.align		12
+	.globl		_start
 _start:
 	stp		x29, x30, [sp, #-32]!
 	mov		x29, sp
diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S
index 91b0fe12c51..1e7de5c3343 100644
--- a/arch/arm/lib/crt0_arm_efi.S
+++ b/arch/arm/lib/crt0_arm_efi.S
@@ -143,6 +143,7 @@ section_table:
 		 IMAGE_SCN_CNT_INITIALIZED_DATA)
 
 	.align		12
+	.globl		_start
 _start:
 	stmfd		sp!, {r0-r2, lr}
 
diff --git a/arch/riscv/lib/crt0_riscv_efi.S b/arch/riscv/lib/crt0_riscv_efi.S
index 9eacbe4a859..f170e4b26d6 100644
--- a/arch/riscv/lib/crt0_riscv_efi.S
+++ b/arch/riscv/lib/crt0_riscv_efi.S
@@ -179,6 +179,7 @@ section_table:
 		 IMAGE_SCN_CNT_INITIALIZED_DATA)
 
 	.align		12
+	.globl		_start
 _start:
 	addi		sp, sp, -(SIZE_LONG * 3)
 	SAVE_LONG(a0, 0)

From 408a20e099eda6ad1ba9813aca4c523ba8de3ea6 Mon Sep 17 00:00:00 2001
From: Sam Edwards <cfsworks@gmail.com>
Date: Sat, 15 Mar 2025 15:18:10 -0700
Subject: [PATCH 14/24] efi_loader: Move .dynamic out of .text in EFI

EFI applications need to be relocatable. Ordinarily, this is achieved
through a PE-format .reloc section, but since that requires toolchain
tricks to achieve, U-Boot's EFI applications instead embed ELF-flavored
relocation information and use it for self-relocation; thus, the
.dynamic section needs to be preserved.

Before this patch, it was tacked on to the end of .text, but this was
not proper: A .text section is SHT_PROGBITS, while the .dynamic section
is SHT_DYNAMIC. Attempting to combine them like this creates a section
type mismatch. While GNU ld doesn't seem to complain, LLVM's lld
considers this a fatal linking error.

This patch moves .dynamic out to its own section, so that the output ELF
has the correct types. (They're all mashed together when converting to
binary anyway, so this patch causes no change in the final .efi output.)

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Cc: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 lib/efi_loader/elf_efi.ldsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/efi_loader/elf_efi.ldsi b/lib/efi_loader/elf_efi.ldsi
index 190a88fb69e..4fa5ca43872 100644
--- a/lib/efi_loader/elf_efi.ldsi
+++ b/lib/efi_loader/elf_efi.ldsi
@@ -21,10 +21,10 @@ SECTIONS
 		*(.gnu.linkonce.t.*)
 		*(.srodata)
 		*(.rodata*)
-		. = ALIGN(16);
-		*(.dynamic);
-		. = ALIGN(512);
 	}
+	. = ALIGN(16);
+	.dynamic : { *(.dynamic) }
+	. = ALIGN(512);
 	.rela.dyn : { *(.rela.dyn) }
 	.rela.plt : { *(.rela.plt) }
 	.rela.got : { *(.rela.got) }

From 7f2fe3dda4ea5384eac4afadb8a4fe5d695e2ce1 Mon Sep 17 00:00:00 2001
From: Sam Edwards <cfsworks@gmail.com>
Date: Sat, 15 Mar 2025 15:18:11 -0700
Subject: [PATCH 15/24] scripts/Makefile.lib: efi: Preserve the .dynstr section
 as well

This section is required by .dynamic and llvm-objcopy will exit with a
fatal error if it is not also preserved in the output.

Signed-off-by: Sam Edwards <CFSworks@gmail.com>
---
 scripts/Makefile.lib | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 18993435eae..275c308154b 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -513,8 +513,8 @@ $(obj)/%_efi.S: $(obj)/%.efi
 	$(call cmd,S_efi)
 
 quiet_cmd_efi_objcopy = OBJCOPY $@
-cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j .sdata -j .data -j \
-		.dynamic -j .dynsym  -j .rel* -j .rela* -j .reloc \
+cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j .sdata -j .data \
+		-j .dynamic -j .dynstr  -j .dynsym -j .rel* -j .reloc \
 		$(if $(EFI_TARGET),$(EFI_TARGET),-O binary) $^ $@
 
 $(obj)/%.efi: $(obj)/%_efi.so

From ca3bea3fc415ce40dc58f1bea9327f6fa12928bb Mon Sep 17 00:00:00 2001
From: Michal Simek <michal.simek@amd.com>
Date: Thu, 6 Mar 2025 11:12:30 +0100
Subject: [PATCH 16/24] cmd: version: Get information about GCC and LD back

U-Boot version command is no longer showing information about GCC and LD.
The reason is that version.h has been removed that's why CC_VERSION_STRING
and LD_VERSION_STRING are not pass.
Values are generated to generated/version_autogenerated.h which is sourced
in version.h.

Fixes: 54ecce2cbf90 ("version: Separate our version string from the version command")
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
 cmd/version.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cmd/version.c b/cmd/version.c
index 53db1a0b6bd..62406608eb0 100644
--- a/cmd/version.c
+++ b/cmd/version.c
@@ -6,6 +6,7 @@
 
 #include <command.h>
 #include <display_options.h>
+#include <version.h>
 #include <version_string.h>
 #include <linux/compiler.h>
 #ifdef CONFIG_SYS_COREBOOT

From 2ac91756ad9124a607af81fda1eafc436934ad4a Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: Thu, 20 Feb 2025 11:00:13 +0100
Subject: [PATCH 17/24] scripts: typos in event_dump.py

%s/even spies/event spies/
%s/EFL/ELF/

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 scripts/event_dump.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/event_dump.py b/scripts/event_dump.py
index 24dfe2bda91..61bb3a8eb92 100755
--- a/scripts/event_dump.py
+++ b/scripts/event_dump.py
@@ -107,7 +107,7 @@ def main(argv):
     Args:
         argv (list of str): List of program arguments, excluding arvg[0]
     """
-    epilog = 'Show a list of even spies in a U-Boot EFL file'
+    epilog = 'Show a list of event spies in a U-Boot ELF file'
     parser = ArgumentParser(epilog=epilog)
     parser.add_argument('elf', type=str, help='ELF file to decode')
     parser.add_argument('-e', '--endian', type=str, default='auto',

From 301c2ab729447b0f7c602e054c3f22a5a9df1b24 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Thu, 27 Feb 2025 12:27:19 -0700
Subject: [PATCH 18/24] qconfig: Correct unhashable-type error with
 --scan-source

This gives an error with newer Python version, so fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 tools/qconfig.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/qconfig.py b/tools/qconfig.py
index 259adbe1bc9..c96a305a48f 100755
--- a/tools/qconfig.py
+++ b/tools/qconfig.py
@@ -1453,7 +1453,7 @@ def do_scan_source(path, do_update):
     print('\nCONFIG options used as Proper in Makefiles but without a non-xPL_ variant:')
     not_found = check_not_found(all_uses, MODE_PROPER)
     show_uses(not_found)
-    proper_not_found |= {not_found.keys()}
+    proper_not_found |= not_found.keys()
 
     # Scan the source code
     all_uses, _ = scan_src_files(src_list)
@@ -1471,7 +1471,7 @@ def do_scan_source(path, do_update):
     print('\nCONFIG options used as Proper in source but without a non-xPL_ variant:')
     not_found = check_not_found(all_uses, MODE_PROPER)
     show_uses(not_found)
-    proper_not_found |= {not_found.keys()}
+    proper_not_found |= not_found.keys()
 
     print('\nCONFIG options used as SPL but without an xPL_ variant:')
     for item in sorted(spl_not_found):

From 15ba2b7356af035bc7dfd5c279e9658291fc7cf3 Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: Tue, 4 Mar 2025 17:04:03 +0100
Subject: [PATCH 19/24] dumpimage: fix handling of StarFive SPL too long

The header of the StarFive U-Boot SPL file u-boot-spl.normal.out has a
field indicating the payload size. When copying U-Boot SPL from a
partition the copied file might be too long.

Currently in this situation a misleading error message 'Incorrect CRC32' is
written.

We must use the payload size and not the file size when calculating the
CRC32.

Write a warning if the file is too long indicating the correct size. This
enables the user to truncate the file accordingly.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
 tools/sfspl.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tools/sfspl.c b/tools/sfspl.c
index c76420ce21b..516e96e8dd9 100644
--- a/tools/sfspl.c
+++ b/tools/sfspl.c
@@ -70,11 +70,14 @@ static int sfspl_verify_header(unsigned char *buf, int size,
 		printf("Truncated file\n");
 		return EXIT_FAILURE;
 	}
+	if ((size_t)size > hdr_size + file_size)
+		printf("File too long, expected %u bytes\n",
+		       hdr_size + file_size);
 	if (hdr->version != DEFAULT_VERSION) {
 		printf("Unknown file format version\n");
 		return EXIT_FAILURE;
 	}
-	crc_check = crc32(0, &buf[hdr_size], size - hdr_size);
+	crc_check = crc32(0, &buf[hdr_size], file_size);
 	if (crc_check != crc) {
 		printf("Incorrect CRC32\n");
 		return EXIT_FAILURE;

From 69fb899133b6c374eff11b13482371bec6898a01 Mon Sep 17 00:00:00 2001
From: Hendrik Donner <hd@os-cillation.de>
Date: Thu, 6 Mar 2025 21:15:39 +0100
Subject: [PATCH 20/24] checkpatch.pl: Report an error for CONFIG_xPL_BUILD in
 device trees

The defines for the different build phases shouldn't be used in device
trees, currently they aren't even defined for device tree pre processing,
resulting in build errors.

Link: https://lists.denx.de/pipermail/u-boot/2025-March/582787.html
Signed-off-by: Hendrik Donner <hd@os-cillation.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 scripts/checkpatch.pl | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index f9f8891c0c4..414019c5b89 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2692,6 +2692,12 @@ sub u_boot_line {
 		ERROR("PRE_SCHEMA",
 		      "Driver model schema uses 'bootph-...' tags now\n" . $herecurr);
 	}
+
+	# Do not allow CONFIG_xPL_BUILD in device trees
+	if ($realfile =~ /\.dtsi?$/ && $line =~ /^\+.*CONFIG_(X|S|T|V)PL_BUILD.*/) {
+		ERROR("CONFIG_xPL_BUILD",
+		      "Do not use CONFIG_xPL_BUILD in device trees\n" . $herecurr);
+	}
 }
 
 sub exclude_global_initialisers {

From 7ad543619463e8817b3044041ac74749a217bbe0 Mon Sep 17 00:00:00 2001
From: Stefan Eichenberger <stefan.eichenberger@toradex.com>
Date: Wed, 19 Mar 2025 17:16:23 +0100
Subject: [PATCH 21/24] board: verdin-am62: remove spl_perform_fixups

spl_perform_fixups is redundant in the current implementation. SPLs call
dram_init during spl_enable_cache in arch/arm/mach-k3/common.c. In
U-Boot, dram_init and dram_init_banksize are automatically called in
init_sequence_f. Therefore, SPLs and U-Boot always determine the correct
RAM size. During Linux boot, fdt_fixup_memory_banks adjusts the RAM size
in the Linux device tree, ensuring correct RAM usage.

dram_init() calls get_ram_size() for the Verdin AM62, which determines
the correct RAM size through read/write operations. However, due to the
K3 bootflow placing ATF in RAM and requiring cache coherence, calling
get_ram_size() with caches enabled prevents ATF boot. Removing this call
restores ATF boot functionality.

This fixes a regression introduced in commit 4164289db882 ("board:
verdin-am62: fix missing memory fixup call") which prevents some of our
Verdin AM62 modules from booting.

Fixes: 4164289db882 ("board: verdin-am62: fix missing memory fixup call")
Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com>
---
 board/toradex/verdin-am62/verdin-am62.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
index a1c471111a0..7b2eecbf659 100644
--- a/board/toradex/verdin-am62/verdin-am62.c
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -112,13 +112,6 @@ int board_late_init(void)
 #define CORE_VOLTAGE			0x80000000
 #define MCU_CTRL_LFXOSC_32K_BYPASS_VAL	BIT(4)
 
-#if IS_ENABLED(CONFIG_XPL_BUILD)
-void spl_perform_fixups(struct spl_image_info *spl_image)
-{
-	fixup_memory_node(spl_image);
-}
-#endif
-
 #ifdef CONFIG_SPL_BOARD_INIT
 void spl_board_init(void)
 {

From 0916053ebc566245b06d0a179533f6622b6ad392 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marex@denx.de>
Date: Wed, 19 Mar 2025 23:07:52 +0100
Subject: [PATCH 22/24] usb: dwc3: gadget: Fix match_ep callback for NXP UUU
 tool

The UUU tool excepts the interrupt-in endpoint to be ep1in, otherwise
it crashes. This is a result of the previous hard-coded EP setup in
drivers/usb/gadget/epautoconf.c which did special-case EP allocation
for SPL builds, and which was since converted to this callback, but
without the special-case EP allocation in SPL part.

This reinstates the SPL part in an isolated manner, only for NXP iMX
SoCs, only for SPL builds, and only for the ep1in interrupt-in endpoint.

Fixes: 1918b8010c32 ("usb: dwc3: gadget: Convert epautoconf workaround to match_ep callback")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Link: https://lore.kernel.org/r/20250319220805.219001-1-marex@denx.de
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
---
 drivers/usb/dwc3/gadget.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index e5a383407a2..477ecd02098 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1631,8 +1631,25 @@ usb_ep *dwc3_gadget_match_ep(struct usb_gadget *gadget,
 		return dwc3_find_ep(gadget, "ep1in");
 	if (usb_endpoint_is_bulk_out(desc))
 		return dwc3_find_ep(gadget, "ep2out");
-	if (usb_endpoint_is_int_in(desc))
+	if (usb_endpoint_is_int_in(desc)) {
+		/*
+		 * Special workaround for NXP UUU tool in SPL.
+		 *
+		 * The tool excepts the interrupt-in endpoint to be ep1in,
+		 * otherwise it crashes. This is a result of the previous
+		 * hard-coded EP setup in drivers/usb/gadget/epautoconf.c
+		 * which did special-case EP allocation for SPL builds,
+		 * and which was since converted to this callback, but
+		 * without the special-case EP allocation in SPL part.
+		 *
+		 * This reinstates the SPL part in an isolated manner,
+		 * only for NXP iMX SoCs, only for SPL builds, and only
+		 * for the ep1in interrupt-in endpoint.
+		 */
+		if (IS_ENABLED(CONFIG_MACH_IMX) && IS_ENABLED(CONFIG_XPL_BUILD))
+			return dwc3_find_ep(gadget, "ep1in");
 		return dwc3_find_ep(gadget, "ep3in");
+	}
 
 	return NULL;
 }

From 67be24906feb6efecce70cd5bfdc2ba8f06d3d5b Mon Sep 17 00:00:00 2001
From: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Date: Fri, 14 Mar 2025 12:57:02 +0200
Subject: [PATCH 23/24] lmb: change the return code on lmb_alloc_addr()

Ben reports a failure to boot the kernel on hardware that starts its
physical memory from 0x0.
The reason is that lmb_alloc_addr(), which is supposed to reserve a
specific address, takes the address as the first argument, but then also
returns the address for success or failure and treats 0 as a failure.

Since we already know the address change the prototype to return an int.

Reported-by: Ben Schneider <ben@bens.haus>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tested-by: Ben Schneider <ben@bens.haus>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
---
 fs/fs.c                     |  2 +-
 include/lmb.h               |  6 ++---
 lib/efi_loader/efi_memory.c |  3 +--
 lib/lmb.c                   |  6 ++---
 test/lib/lmb.c              | 53 +++++++++++++++++++------------------
 5 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/fs/fs.c b/fs/fs.c
index 99ddcc5e37b..1ed7c0f2d2c 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -554,7 +554,7 @@ static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset,
 
 	lmb_dump_all();
 
-	if (lmb_alloc_addr(addr, read_len, LMB_NONE) == addr)
+	if (!lmb_alloc_addr(addr, read_len, LMB_NONE))
 		return 0;
 
 	log_err("** Reading file would overwrite reserved memory **\n");
diff --git a/include/lmb.h b/include/lmb.h
index 09297a4f530..0d316c64c0a 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -135,9 +135,9 @@ phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr,
  * parameter. The base parameter is used to specify the base address
  * of the requested region.
  *
- * Return: Base address on success, 0 on error.
+ * Return: 0 on success -1 on error
  */
-phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags);
+int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags);
 
 /**
  * lmb_is_reserved_flags() - Test if address is in reserved region with flag
@@ -175,7 +175,7 @@ void lmb_pop(struct lmb *store);
 
 static inline int lmb_read_check(phys_addr_t addr, phys_size_t len)
 {
-	return lmb_alloc_addr(addr, len, LMB_NONE) == addr ? 0 : -1;
+	return lmb_alloc_addr(addr, len, LMB_NONE);
 }
 
 /**
diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c
index 6d00b186250..c39b53922bb 100644
--- a/lib/efi_loader/efi_memory.c
+++ b/lib/efi_loader/efi_memory.c
@@ -491,8 +491,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type,
 			return EFI_NOT_FOUND;
 
 		addr = map_to_sysmem((void *)(uintptr_t)*memory);
-		addr = (u64)lmb_alloc_addr(addr, len, flags);
-		if (!addr)
+		if (lmb_alloc_addr(addr, len, flags))
 			return EFI_NOT_FOUND;
 		break;
 	default:
diff --git a/lib/lmb.c b/lib/lmb.c
index 93fc1bea07c..61bb13dc4e2 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -714,7 +714,7 @@ phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr,
 	return alloc;
 }
 
-phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags)
+int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags)
 {
 	long rgn;
 	struct lmb_region *lmb_memory = lmb.available_mem.data;
@@ -731,11 +731,11 @@ phys_addr_t lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags)
 				      base + size - 1, 1)) {
 			/* ok, reserve the memory */
 			if (!lmb_reserve(base, size, flags))
-				return base;
+				return 0;
 		}
 	}
 
-	return 0;
+	return -1;
 }
 
 /* Return number of bytes from a given address that are free */
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index fcb5f1af532..01b1c7fdedd 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -531,21 +531,21 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 
 	/* Try to allocate a page twice */
 	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
-	ut_asserteq(b, alloc_addr_a);
-	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
 	ut_asserteq(b, 0);
+	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
+	ut_asserteq(b, -1);
 	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
-	ut_asserteq(b, alloc_addr_a);
+	ut_asserteq(b, 0);
 	b = lmb_alloc_addr(alloc_addr_a, 0x2000, LMB_NONE);
-	ut_asserteq(b, alloc_addr_a);
+	ut_asserteq(b, 0);
 	ret = lmb_free(alloc_addr_a, 0x2000);
 	ut_asserteq(ret, 0);
 	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
-	ut_asserteq(b, alloc_addr_a);
+	ut_asserteq(b, 0);
 	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE);
-	ut_asserteq(b, 0);
+	ut_asserteq(b, -1);
 	b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE);
-	ut_asserteq(b, 0);
+	ut_asserteq(b, -1);
 	ret = lmb_free(alloc_addr_a, 0x1000);
 	ut_asserteq(ret, 0);
 
@@ -561,22 +561,22 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 
 	/* allocate blocks */
 	a = lmb_alloc_addr(ram, alloc_addr_a - ram, LMB_NONE);
-	ut_asserteq(a, ram);
+	ut_asserteq(a, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 3, ram, 0x8010000,
 		   alloc_addr_b, 0x10000, alloc_addr_c, 0x10000);
 	b = lmb_alloc_addr(alloc_addr_a + 0x10000,
 			   alloc_addr_b - alloc_addr_a - 0x10000, LMB_NONE);
-	ut_asserteq(b, alloc_addr_a + 0x10000);
+	ut_asserteq(b, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x10010000,
 		   alloc_addr_c, 0x10000, 0, 0);
 	c = lmb_alloc_addr(alloc_addr_b + 0x10000,
 			   alloc_addr_c - alloc_addr_b - 0x10000, LMB_NONE);
-	ut_asserteq(c, alloc_addr_b + 0x10000);
+	ut_asserteq(c, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
 		   0, 0, 0, 0);
 	d = lmb_alloc_addr(alloc_addr_c + 0x10000,
 			   ram_end - alloc_addr_c - 0x10000, LMB_NONE);
-	ut_asserteq(d, alloc_addr_c + 0x10000);
+	ut_asserteq(d, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size,
 		   0, 0, 0, 0);
 
@@ -586,57 +586,58 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram)
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, ram_size,
 		   0, 0, 0, 0);
 
-	ret = lmb_free(d, ram_end - alloc_addr_c - 0x10000);
+	/* free thge allocation from d */
+	ret = lmb_free(alloc_addr_c + 0x10000, ram_end - alloc_addr_c - 0x10000);
 	ut_asserteq(ret, 0);
 
 	/* allocate at 3 points in free range */
 
 	d = lmb_alloc_addr(ram_end - 4, 4, LMB_NONE);
-	ut_asserteq(d, ram_end - 4);
+	ut_asserteq(d, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000,
-		   d, 4, 0, 0);
-	ret = lmb_free(d, 4);
+		   ram_end - 4, 4, 0, 0);
+	ret = lmb_free(ram_end - 4, 4);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
 		   0, 0, 0, 0);
 
 	d = lmb_alloc_addr(ram_end - 128, 4, LMB_NONE);
-	ut_asserteq(d, ram_end - 128);
+	ut_asserteq(d, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000,
-		   d, 4, 0, 0);
-	ret = lmb_free(d, 4);
+		   ram_end - 128, 4, 0, 0);
+	ret = lmb_free(ram_end - 128, 4);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
 		   0, 0, 0, 0);
 
 	d = lmb_alloc_addr(alloc_addr_c + 0x10000, 4, LMB_NONE);
-	ut_asserteq(d, alloc_addr_c + 0x10000);
+	ut_asserteq(d, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010004,
 		   0, 0, 0, 0);
-	ret = lmb_free(d, 4);
+	ret = lmb_free(alloc_addr_c + 0x10000, 4);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000,
 		   0, 0, 0, 0);
 
-	/* allocate at the bottom */
-	ret = lmb_free(a, alloc_addr_a - ram);
+	/* allocate at the bottom a was assigned to ram at the top */
+	ret = lmb_free(ram, alloc_addr_a - ram);
 	ut_asserteq(ret, 0);
 	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + 0x8000000,
 		   0x10010000, 0, 0, 0, 0);
 
 	d = lmb_alloc_addr(ram, 4, LMB_NONE);
-	ut_asserteq(d, ram);
-	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, d, 4,
+	ut_asserteq(d, 0);
+	ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 4,
 		   ram + 0x8000000, 0x10010000, 0, 0);
 
 	/* check that allocating outside memory fails */
 	if (ram_end != 0) {
 		ret = lmb_alloc_addr(ram_end, 1, LMB_NONE);
-		ut_asserteq(ret, 0);
+		ut_asserteq(ret, -1);
 	}
 	if (ram != 0) {
 		ret = lmb_alloc_addr(ram - 1, 1, LMB_NONE);
-		ut_asserteq(ret, 0);
+		ut_asserteq(ret, -1);
 	}
 
 	lmb_pop(&store);

From 3d8be1f5ec30180748259a251efe4f63c8b4b329 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 24 Mar 2025 20:00:24 -0600
Subject: [PATCH 24/24] Prepare v2025.05-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>
---
 Makefile                      | 2 +-
 doc/develop/release_cycle.rst | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 0694c425438..7d83ce16721 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
 VERSION = 2025
 PATCHLEVEL = 04
 SUBLEVEL =
-EXTRAVERSION = -rc4
+EXTRAVERSION = -rc5
 NAME =
 
 # *DOCUMENTATION*
diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst
index dc5bb340ff2..e736dc0616e 100644
--- a/doc/develop/release_cycle.rst
+++ b/doc/develop/release_cycle.rst
@@ -76,7 +76,7 @@ For the next scheduled release, release candidates were made on::
 
 * U-Boot v2025.04-rc4 was released on Mon 10 March 2025.
 
-.. * U-Boot v2025.04-rc5 was released on Mon 24 March 2025.
+* U-Boot v2025.04-rc5 was released on Mon 24 March 2025.
 
 Please note that the following dates are planned only and may be deviated from
 as needed.