rockchip: spl: Enable caches to speed up checksum validation
FIT checksum validation is very slow in SPL due to D-cache not being enabled. Enable caches in SPL on ARM64 SoCs to speed up FIT checksum validation, from seconds to milliseconds. This change enables caches in SPL on all Rockchip ARM64 boards, the Kconfig options SPL_SYS_ICACHE_OFF and SPL_SYS_DCACHE_OFF can be used to disable caches for a specific board or SoC if needed. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
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committed by
Kever Yang

parent
3e15dee38d
commit
6d8cdfd153
@@ -3,7 +3,7 @@
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <hang.h>
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@@ -136,6 +136,20 @@ void board_init_f(ulong dummy)
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}
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gd->ram_top = gd->ram_base + get_effective_memsize();
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gd->ram_top = board_get_usable_ram_top(gd->ram_size);
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if (IS_ENABLED(CONFIG_ARM64) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
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gd->relocaddr = gd->ram_top;
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arch_reserve_mmu();
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enable_caches();
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}
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#endif
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preloader_console_init();
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}
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void spl_board_prepare_for_boot(void)
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{
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if (!IS_ENABLED(CONFIG_ARM64) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
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return;
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cleanup_before_linux();
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}
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