Merge tag 'u-boot-stm32-20250428' of https://source.denx.de/u-boot/custodians/u-boot-stm
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/25970 - Add OF_UPSTREAM flag support for STi, STM32 MCU and MPU platforms. - Add ETZPC as system bus for STM32MP1 platforms - Add RIFSC as sytem bus for STM32MP2 platforms - Update STM32MP2 board/machine support: - update cmd_stm32key. - update cmd_stm32prog. - update STM32MP25 configs. - add leds and buttons support. - add boot_mode support (USB/PXE/MMC/NOR/NAND). - add bootcmd support. - enable MMC support.
This commit is contained in:
Tom Rini
@@ -530,17 +530,6 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
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dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
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dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
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stm32429i-eval.dtb \
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stm32f469-disco.dtb
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dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
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stm32f769-disco.dtb \
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stm32746g-eval.dtb
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dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
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stm32h743i-eval.dtb \
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stm32h750i-art-pi.dtb
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dtb-$(CONFIG_MACH_SUN4I) += \
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sun4i-a10-inet-3f.dtb \
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sun4i-a10-inet-3w.dtb
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@@ -1087,29 +1076,9 @@ dtb-$(CONFIG_ASPEED_AST2600) += \
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ast2600-sbp1.dtb \
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ast2600-x4tf.dtb
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dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
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dtb-$(CONFIG_STM32MP13X) += \
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stm32mp135f-dk.dtb
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dtb-$(CONFIG_STM32MP15X) += \
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stm32mp157a-dk1.dtb \
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stm32mp157a-dk1-scmi.dtb \
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stm32mp157a-icore-stm32mp1-ctouch2.dtb \
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stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
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stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
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stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
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stm32mp157c-dk2.dtb \
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stm32mp157c-dk2-scmi.dtb \
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stm32mp157c-ed1.dtb \
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stm32mp157c-ed1-scmi.dtb \
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stm32mp157c-ev1.dtb \
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stm32mp157c-ev1-scmi.dtb \
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stm32mp157c-odyssey.dtb
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dtb-$(CONFIG_STM32MP25X) += \
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stm32mp257f-ev1.dtb
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dtb-$(CONFIG_SOC_K3_AM654) += \
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k3-am654-r5-base-board.dtb
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@@ -1,72 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ST_PINCFG_H_
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#define _ST_PINCFG_H_
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/* Alternate functions */
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#define ALT1 1
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#define ALT2 2
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#define ALT3 3
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#define ALT4 4
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#define ALT5 5
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#define ALT6 6
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#define ALT7 7
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/* Output enable */
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#define OE (1 << 27)
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/* Pull Up */
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#define PU (1 << 26)
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/* Open Drain */
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#define OD (1 << 25)
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#define RT (1 << 23)
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#define INVERTCLK (1 << 22)
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#define CLKNOTDATA (1 << 21)
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#define DOUBLE_EDGE (1 << 20)
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#define CLK_A (0 << 18)
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#define CLK_B (1 << 18)
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#define CLK_C (2 << 18)
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#define CLK_D (3 << 18)
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/* User-frendly defines for Pin Direction */
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/* oe = 0, pu = 0, od = 0 */
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#define IN (0)
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/* oe = 0, pu = 1, od = 0 */
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#define IN_PU (PU)
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/* oe = 1, pu = 0, od = 0 */
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#define OUT (OE)
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/* oe = 1, pu = 0, od = 1 */
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#define BIDIR (OE | OD)
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/* oe = 1, pu = 1, od = 1 */
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#define BIDIR_PU (OE | PU | OD)
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/* RETIME_TYPE */
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/*
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* B Mode
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* Bypass retime with optional delay parameter
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*/
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#define BYPASS (0)
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/*
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* R0, R1, R0D, R1D modes
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* single-edge data non inverted clock, retime data with clk
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*/
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#define SE_NICLK_IO (RT)
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/*
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* RIV0, RIV1, RIV0D, RIV1D modes
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* single-edge data inverted clock, retime data with clk
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*/
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#define SE_ICLK_IO (RT | INVERTCLK)
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/*
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* R0E, R1E, R0ED, R1ED modes
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* double-edge data, retime data with clk
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*/
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#define DE_IO (RT | DOUBLE_EDGE)
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/*
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* CIV0, CIV1 modes with inverted clock
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* Retiming the clk pins will park clock & reduce the noise within the core.
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*/
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#define ICLK (RT | CLKNOTDATA | INVERTCLK)
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/*
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* CLK0, CLK1 modes with non-inverted clock
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* Retiming the clk pins will park clock & reduce the noise within the core.
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*/
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#define NICLK (RT | CLKNOTDATA)
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#endif /* _ST_PINCFG_H_ */
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@@ -1,323 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 STMicroelectronics R&D Limited
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*/
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#include <dt-bindings/clock/stih407-clks.h>
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/ {
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* A9 PLL.
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*/
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clockgen-a9@92b0000 {
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compatible = "st,clkgen-c32";
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reg = <0x92b0000 0xffff>;
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clockgen_a9_pll: clockgen-a9-pll {
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#clock-cells = <1>;
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compatible = "st,stih407-clkgen-plla9";
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clocks = <&clk_sysin>;
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clock-output-names = "clockgen-a9-pll-odf";
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};
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};
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/*
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* ARM CPU related clocks.
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*/
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clk_m_a9: clk-m-a9@92b0000 {
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#clock-cells = <0>;
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compatible = "st,stih407-clkgen-a9-mux";
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reg = <0x92b0000 0x10000>;
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clocks = <&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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clockgen-a@90ff000 {
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compatible = "st,clkgen-c32";
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reg = <0x90ff000 0x1000>;
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-a0-pll-ofd-0";
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clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
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};
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clk_s_a0_flexgen: clk-s-a0-flexgen {
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compatible = "st,flexgen";
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#clock-cells = <1>;
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clocks = <&clk_s_a0_pll 0>,
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<&clk_sysin>;
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clock-output-names = "clk-ic-lmi0";
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clock-critical = <CLK_IC_LMI0>;
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};
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};
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clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
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#clock-cells = <1>;
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compatible = "st,quadfs-pll";
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reg = <0x9103000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-fs0-ch0",
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"clk-s-c0-fs0-ch1",
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"clk-s-c0-fs0-ch2",
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"clk-s-c0-fs0-ch3";
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clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
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};
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clk_s_c0: clockgen-c@9103000 {
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compatible = "st,clkgen-c32";
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reg = <0x9103000 0x1000>;
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clk_s_c0_pll0: clk-s-c0-pll0 {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-pll0-odf-0";
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clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
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};
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clk_s_c0_pll1: clk-s-c0-pll1 {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll1";
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-c0-pll1-odf-0";
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};
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clk_s_c0_flexgen: clk-s-c0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen";
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clocks = <&clk_s_c0_pll0 0>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_c0_quadfs 0>,
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<&clk_s_c0_quadfs 1>,
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<&clk_s_c0_quadfs 2>,
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<&clk_s_c0_quadfs 3>,
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<&clk_sysin>;
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clock-output-names = "clk-icn-gpu",
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"clk-fdma",
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"clk-nand",
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"clk-hva",
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"clk-proc-stfe",
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"clk-proc-tp",
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"clk-rx-icn-dmu",
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"clk-rx-icn-hva",
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"clk-icn-cpu",
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"clk-tx-icn-dmu",
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"clk-mmc-0",
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"clk-mmc-1",
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"clk-jpegdec",
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"clk-ext2fa9",
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"clk-ic-bdisp-0",
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"clk-ic-bdisp-1",
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"clk-pp-dmu",
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"clk-vid-dmu",
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"clk-dss-lpc",
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"clk-st231-aud-0",
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"clk-st231-gp-1",
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"clk-st231-dmu",
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"clk-icn-lmi",
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"clk-tx-icn-disp-1",
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"clk-icn-sbc",
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"clk-stfe-frc2",
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"clk-eth-phy",
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"clk-eth-ref-phyclk",
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"clk-flash-promip",
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"clk-main-disp",
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"clk-aux-disp",
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"clk-compo-dvp";
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clock-critical = <CLK_PROC_STFE>,
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<CLK_ICN_CPU>,
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<CLK_TX_ICN_DMU>,
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<CLK_EXT2F_A9>,
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<CLK_ICN_LMI>,
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<CLK_ICN_SBC>;
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/*
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* ARM Peripheral clock for timers
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*/
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&clk_s_c0_flexgen 13>;
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clock-output-names = "clk-m-a9-ext2f-div2";
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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};
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clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
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#clock-cells = <1>;
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compatible = "st,quadfs";
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reg = <0x9104000 0x1000>;
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clocks = <&clk_sysin>;
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clock-output-names = "clk-s-d0-fs0-ch0",
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"clk-s-d0-fs0-ch1",
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"clk-s-d0-fs0-ch2",
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"clk-s-d0-fs0-ch3";
|
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};
|
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clockgen-d0@9104000 {
|
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compatible = "st,clkgen-c32";
|
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reg = <0x9104000 0x1000>;
|
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|
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clk_s_d0_flexgen: clk-s-d0-flexgen {
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#clock-cells = <1>;
|
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compatible = "st,flexgen-audio", "st,flexgen";
|
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|
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clocks = <&clk_s_d0_quadfs 0>,
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<&clk_s_d0_quadfs 1>,
|
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<&clk_s_d0_quadfs 2>,
|
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<&clk_s_d0_quadfs 3>,
|
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<&clk_sysin>;
|
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|
||||
clock-output-names = "clk-pcm-0",
|
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"clk-pcm-1",
|
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"clk-pcm-2",
|
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"clk-spdiff";
|
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};
|
||||
};
|
||||
|
||||
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
|
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#clock-cells = <1>;
|
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compatible = "st,quadfs";
|
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reg = <0x9106000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d2-fs0-ch0",
|
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"clk-s-d2-fs0-ch1",
|
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"clk-s-d2-fs0-ch2",
|
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"clk-s-d2-fs0-ch3";
|
||||
};
|
||||
|
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clockgen-d2@9106000 {
|
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compatible = "st,clkgen-c32";
|
||||
reg = <0x9106000 0x1000>;
|
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|
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clk_s_d2_flexgen: clk-s-d2-flexgen {
|
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#clock-cells = <1>;
|
||||
compatible = "st,flexgen-video", "st,flexgen";
|
||||
|
||||
clocks = <&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 1>,
|
||||
<&clk_s_d2_quadfs 2>,
|
||||
<&clk_s_d2_quadfs 3>,
|
||||
<&clk_sysin>,
|
||||
<&clk_sysin>,
|
||||
<&clk_tmdsout_hdmi>;
|
||||
|
||||
clock-output-names = "clk-pix-main-disp",
|
||||
"clk-pix-pip",
|
||||
"clk-pix-gdp1",
|
||||
"clk-pix-gdp2",
|
||||
"clk-pix-gdp3",
|
||||
"clk-pix-gdp4",
|
||||
"clk-pix-aux-disp",
|
||||
"clk-denc",
|
||||
"clk-pix-hddac",
|
||||
"clk-hddac",
|
||||
"clk-sddac",
|
||||
"clk-pix-dvo",
|
||||
"clk-dvo",
|
||||
"clk-pix-hdmi",
|
||||
"clk-tmds-hdmi",
|
||||
"clk-ref-hdmiphy";
|
||||
};
|
||||
};
|
||||
|
||||
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d3-fs0-ch0",
|
||||
"clk-s-d3-fs0-ch1",
|
||||
"clk-s-d3-fs0-ch2",
|
||||
"clk-s-d3-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d3@9107000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clk_s_d3_flexgen: clk-s-d3-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
|
||||
clocks = <&clk_s_d3_quadfs 0>,
|
||||
<&clk_s_d3_quadfs 1>,
|
||||
<&clk_s_d3_quadfs 2>,
|
||||
<&clk_s_d3_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-stfe-frc1",
|
||||
"clk-tsout-0",
|
||||
"clk-tsout-1",
|
||||
"clk-mchi",
|
||||
"clk-vsens-compo",
|
||||
"clk-frc1-remote",
|
||||
"clk-lpc-0",
|
||||
"clk-lpc-1";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -7,37 +7,35 @@
|
||||
|
||||
/{
|
||||
soc {
|
||||
st_dwc3: dwc3@8f94000 {
|
||||
dwc3: dwc3@9900000 {
|
||||
dr_mode = "peripheral";
|
||||
phys = <&usb2_picophy0>;
|
||||
};
|
||||
};
|
||||
|
||||
clk_usb: clk-usb {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
ohci0: usb@9a03c00 {
|
||||
compatible = "generic-ohci";
|
||||
clocks = <&clk_usb>;
|
||||
};
|
||||
|
||||
ehci0: usb@9a03e00 {
|
||||
compatible = "generic-ehci";
|
||||
clocks = <&clk_usb>;
|
||||
};
|
||||
|
||||
ohci1: usb@9a83c00 {
|
||||
compatible = "generic-ohci";
|
||||
clocks = <&clk_usb>;
|
||||
};
|
||||
|
||||
ehci1: usb@9a83e00 {
|
||||
compatible = "generic-ehci";
|
||||
clocks = <&clk_usb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dwc3 {
|
||||
dr_mode = "peripheral";
|
||||
phys = <&usb2_picophy0>;
|
||||
};
|
||||
|
||||
&ehci0 {
|
||||
compatible = "st,st-ehci-300x", "generic-ehci";
|
||||
clocks = <&clk_usb>;
|
||||
};
|
||||
|
||||
&ehci1 {
|
||||
compatible = "st,st-ehci-300x", "generic-ehci";
|
||||
clocks = <&clk_usb>;
|
||||
};
|
||||
|
||||
&ohci0 {
|
||||
compatible = "st,st-ehci-300x", "generic-ehci";
|
||||
clocks = <&clk_usb>;
|
||||
};
|
||||
|
||||
&ohci1 {
|
||||
compatible = "st,st-ehci-300x", "generic-ehci";
|
||||
clocks = <&clk_usb>;
|
||||
};
|
||||
|
||||
@@ -1,214 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2016 STMicroelectronics (R&D) Limited.
|
||||
* Author: Patrice Chotard <patrice.chotard@foss.st.com>
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "stih410.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "STiH410 B2260";
|
||||
compatible = "st,stih410-b2260", "st,stih410";
|
||||
|
||||
chosen {
|
||||
bootargs = "clk_ignore_unused";
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x40000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial1 = &uart1;
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
user_green_1 {
|
||||
label = "User_green_1";
|
||||
gpios = <&pio1 3 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
user_green_2 {
|
||||
label = "User_green_2";
|
||||
gpios = <&pio4 1 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
user_green_3 {
|
||||
label = "User_green_3";
|
||||
gpios = <&pio2 1 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
user_green_4 {
|
||||
label = "User_green_4";
|
||||
gpios = <&pio2 5 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
sound: sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "STI-B2260";
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
simple-audio-card,dai-link@0 {
|
||||
reg = <0>;
|
||||
/* DAC */
|
||||
format = "i2s";
|
||||
mclk-fs = <128>;
|
||||
cpu {
|
||||
sound-dai = <&sti_uni_player0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&sti_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/* Low speed expansion connector */
|
||||
uart0: serial@9830000 {
|
||||
label = "LS-UART0";
|
||||
pinctrl-names = "default", "no-hw-flowctrl";
|
||||
pinctrl-0 = <&pinctrl_serial0_hw_flowctrl>;
|
||||
pinctrl-1 = <&pinctrl_serial0>;
|
||||
rts-gpios = <&pio17 3 GPIO_ACTIVE_LOW>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Low speed expansion connector */
|
||||
uart1: serial@9831000 {
|
||||
label = "LS-UART1";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Low speed expansion connector */
|
||||
spi0: spi@9844000 {
|
||||
label = "LS-SPI0";
|
||||
cs-gpios = <&pio30 3 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Low speed expansion connector */
|
||||
i2c0: i2c@9840000 {
|
||||
label = "LS-I2C0";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Low speed expansion connector */
|
||||
i2c1: i2c@9841000 {
|
||||
label = "LS-I2C1";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* high speed expansion connector */
|
||||
i2c2: i2c@9842000 {
|
||||
label = "HS-I2C2";
|
||||
pinctrl-0 = <&pinctrl_i2c2_alt2_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* high speed expansion connector */
|
||||
i2c3: i2c@9843000 {
|
||||
label = "HS-I2C3";
|
||||
pinctrl-0 = <&pinctrl_i2c3_alt3_0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: sdhci@9060000 {
|
||||
pinctrl-0 = <&pinctrl_sd0>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* high speed expansion connector */
|
||||
mmc1: sdhci@9080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm0: pwm@9810000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm1: pwm@9510000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2_picophy1: phy2@0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3@0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci0: usb@9a03c00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ehci0: usb@9a03e00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ohci1: usb@9a83c00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ehci1: usb@9a83e00 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
st_dwc3: dwc3@8f94000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet0: dwmac@9630000 {
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
|
||||
|
||||
snps,phy-bus-name = "stmmac";
|
||||
snps,phy-bus-id = <0>;
|
||||
snps,phy-addr = <0>;
|
||||
snps,reset-gpio = <&pio0 7 0>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sti_uni_player0: sti-uni-player@8d80000 {
|
||||
status = "okay";
|
||||
};
|
||||
/* SSC11 to HDMI */
|
||||
hdmiddc: i2c@9541000 {
|
||||
/* HDMI V1.3a supports Standard mode only */
|
||||
clock-frequency = <100000>;
|
||||
st,i2c-min-scl-pulse-width-us = <0>;
|
||||
st,i2c-min-sda-pulse-width-us = <5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
miphy28lp_phy: miphy28lp@0 {
|
||||
|
||||
phy_port1: port@9b2a000 {
|
||||
st,osc-force-ext;
|
||||
};
|
||||
};
|
||||
|
||||
sata1: sata@9b28000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,333 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2014 STMicroelectronics R&D Limited
|
||||
*/
|
||||
#include <dt-bindings/clock/stih410-clks.h>
|
||||
/ {
|
||||
/*
|
||||
* Fixed 30MHz oscillator inputs to SoC
|
||||
*/
|
||||
clk_sysin: clk-sysin {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <30000000>;
|
||||
clock-output-names = "CLK_SYSIN";
|
||||
};
|
||||
|
||||
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
compatible = "st,stih410-clk", "simple-bus";
|
||||
|
||||
/*
|
||||
* A9 PLL.
|
||||
*/
|
||||
clockgen-a9@92b0000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x92b0000 0xffff>;
|
||||
|
||||
clockgen_a9_pll: clockgen-a9-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,stih407-clkgen-plla9";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clockgen-a9-pll-odf";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* ARM CPU related clocks.
|
||||
*/
|
||||
clk_m_a9: clk-m-a9@92b0000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
|
||||
reg = <0x92b0000 0x10000>;
|
||||
|
||||
clocks = <&clockgen_a9_pll 0>,
|
||||
<&clockgen_a9_pll 0>,
|
||||
<&clk_s_c0_flexgen 13>,
|
||||
<&clk_m_a9_ext2f_div2>;
|
||||
/*
|
||||
* ARM Peripheral clock for timers
|
||||
*/
|
||||
arm_periph_clk: clk-m-a9-periphs {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_m_a9>;
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
clockgen-a@90ff000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x90ff000 0x1000>;
|
||||
|
||||
clk_s_a0_pll: clk-s-a0-pll {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgen-pll0";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-a0-pll-ofd-0";
|
||||
clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
|
||||
};
|
||||
|
||||
clk_s_a0_flexgen: clk-s-a0-flexgen {
|
||||
compatible = "st,flexgen";
|
||||
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&clk_s_a0_pll 0>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-ic-lmi0",
|
||||
"clk-ic-lmi1";
|
||||
clock-critical = <CLK_IC_LMI0>;
|
||||
};
|
||||
};
|
||||
|
||||
clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs-pll";
|
||||
reg = <0x9103000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-c0-fs0-ch0",
|
||||
"clk-s-c0-fs0-ch1",
|
||||
"clk-s-c0-fs0-ch2",
|
||||
"clk-s-c0-fs0-ch3";
|
||||
clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
|
||||
};
|
||||
|
||||
clk_s_c0: clockgen-c@9103000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9103000 0x1000>;
|
||||
|
||||
clk_s_c0_pll0: clk-s-c0-pll0 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgen-pll0";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-c0-pll0-odf-0";
|
||||
clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
|
||||
};
|
||||
|
||||
clk_s_c0_pll1: clk-s-c0-pll1 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,clkgen-pll1";
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-c0-pll1-odf-0";
|
||||
};
|
||||
|
||||
clk_s_c0_flexgen: clk-s-c0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
|
||||
clocks = <&clk_s_c0_pll0 0>,
|
||||
<&clk_s_c0_pll1 0>,
|
||||
<&clk_s_c0_quadfs 0>,
|
||||
<&clk_s_c0_quadfs 1>,
|
||||
<&clk_s_c0_quadfs 2>,
|
||||
<&clk_s_c0_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-icn-gpu",
|
||||
"clk-fdma",
|
||||
"clk-nand",
|
||||
"clk-hva",
|
||||
"clk-proc-stfe",
|
||||
"clk-proc-tp",
|
||||
"clk-rx-icn-dmu",
|
||||
"clk-rx-icn-hva",
|
||||
"clk-icn-cpu",
|
||||
"clk-tx-icn-dmu",
|
||||
"clk-mmc-0",
|
||||
"clk-mmc-1",
|
||||
"clk-jpegdec",
|
||||
"clk-ext2fa9",
|
||||
"clk-ic-bdisp-0",
|
||||
"clk-ic-bdisp-1",
|
||||
"clk-pp-dmu",
|
||||
"clk-vid-dmu",
|
||||
"clk-dss-lpc",
|
||||
"clk-st231-aud-0",
|
||||
"clk-st231-gp-1",
|
||||
"clk-st231-dmu",
|
||||
"clk-icn-lmi",
|
||||
"clk-tx-icn-disp-1",
|
||||
"clk-icn-sbc",
|
||||
"clk-stfe-frc2",
|
||||
"clk-eth-phy",
|
||||
"clk-eth-ref-phyclk",
|
||||
"clk-flash-promip",
|
||||
"clk-main-disp",
|
||||
"clk-aux-disp",
|
||||
"clk-compo-dvp",
|
||||
"clk-tx-icn-hades",
|
||||
"clk-rx-icn-hades",
|
||||
"clk-icn-reg-16",
|
||||
"clk-pp-hades",
|
||||
"clk-clust-hades",
|
||||
"clk-hwpe-hades",
|
||||
"clk-fc-hades";
|
||||
clock-critical = <CLK_PROC_STFE>,
|
||||
<CLK_ICN_CPU>,
|
||||
<CLK_TX_ICN_DMU>,
|
||||
<CLK_EXT2F_A9>,
|
||||
<CLK_ICN_LMI>,
|
||||
<CLK_ICN_SBC>;
|
||||
|
||||
/*
|
||||
* ARM Peripheral clock for timers
|
||||
*/
|
||||
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
|
||||
clocks = <&clk_s_c0_flexgen 13>;
|
||||
|
||||
clock-output-names = "clk-m-a9-ext2f-div2";
|
||||
|
||||
clock-div = <2>;
|
||||
clock-mult = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
reg = <0x9104000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d0-fs0-ch0",
|
||||
"clk-s-d0-fs0-ch1",
|
||||
"clk-s-d0-fs0-ch2",
|
||||
"clk-s-d0-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d0@9104000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9104000 0x1000>;
|
||||
|
||||
clk_s_d0_flexgen: clk-s-d0-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen-audio", "st,flexgen";
|
||||
|
||||
clocks = <&clk_s_d0_quadfs 0>,
|
||||
<&clk_s_d0_quadfs 1>,
|
||||
<&clk_s_d0_quadfs 2>,
|
||||
<&clk_s_d0_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-pcm-0",
|
||||
"clk-pcm-1",
|
||||
"clk-pcm-2",
|
||||
"clk-spdiff",
|
||||
"clk-pcmr10-master",
|
||||
"clk-usb2-phy";
|
||||
};
|
||||
};
|
||||
|
||||
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
reg = <0x9106000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d2-fs0-ch0",
|
||||
"clk-s-d2-fs0-ch1",
|
||||
"clk-s-d2-fs0-ch2",
|
||||
"clk-s-d2-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d2@9106000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9106000 0x1000>;
|
||||
|
||||
clk_s_d2_flexgen: clk-s-d2-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen-video", "st,flexgen";
|
||||
|
||||
clocks = <&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 1>,
|
||||
<&clk_s_d2_quadfs 2>,
|
||||
<&clk_s_d2_quadfs 3>,
|
||||
<&clk_sysin>,
|
||||
<&clk_sysin>,
|
||||
<&clk_tmdsout_hdmi>;
|
||||
|
||||
clock-output-names = "clk-pix-main-disp",
|
||||
"clk-pix-pip",
|
||||
"clk-pix-gdp1",
|
||||
"clk-pix-gdp2",
|
||||
"clk-pix-gdp3",
|
||||
"clk-pix-gdp4",
|
||||
"clk-pix-aux-disp",
|
||||
"clk-denc",
|
||||
"clk-pix-hddac",
|
||||
"clk-hddac",
|
||||
"clk-sddac",
|
||||
"clk-pix-dvo",
|
||||
"clk-dvo",
|
||||
"clk-pix-hdmi",
|
||||
"clk-tmds-hdmi",
|
||||
"clk-ref-hdmiphy";
|
||||
};
|
||||
};
|
||||
|
||||
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,quadfs";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clocks = <&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-s-d3-fs0-ch0",
|
||||
"clk-s-d3-fs0-ch1",
|
||||
"clk-s-d3-fs0-ch2",
|
||||
"clk-s-d3-fs0-ch3";
|
||||
};
|
||||
|
||||
clockgen-d3@9107000 {
|
||||
compatible = "st,clkgen-c32";
|
||||
reg = <0x9107000 0x1000>;
|
||||
|
||||
clk_s_d3_flexgen: clk-s-d3-flexgen {
|
||||
#clock-cells = <1>;
|
||||
compatible = "st,flexgen";
|
||||
|
||||
clocks = <&clk_s_d3_quadfs 0>,
|
||||
<&clk_s_d3_quadfs 1>,
|
||||
<&clk_s_d3_quadfs 2>,
|
||||
<&clk_s_d3_quadfs 3>,
|
||||
<&clk_sysin>;
|
||||
|
||||
clock-output-names = "clk-stfe-frc1",
|
||||
"clk-tsout-0",
|
||||
"clk-tsout-1",
|
||||
"clk-mchi",
|
||||
"clk-vsens-compo",
|
||||
"clk-frc1-remote",
|
||||
"clk-lpc-0",
|
||||
"clk-lpc-1";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,31 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2014 STMicroelectronics Limited.
|
||||
* Author: Peter Griffin <peter.griffin@linaro.org>
|
||||
*/
|
||||
#include "st-pincfg.h"
|
||||
/ {
|
||||
|
||||
soc {
|
||||
pin-controller-rear@922f080 {
|
||||
|
||||
usb0 {
|
||||
pinctrl_usb0: usb2-0 {
|
||||
st,pins {
|
||||
usb-oc-detect = <&pio35 0 ALT1 IN>;
|
||||
usb-pwr-enable = <&pio35 1 ALT1 OUT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb1 {
|
||||
pinctrl_usb1: usb2-1 {
|
||||
st,pins {
|
||||
usb-oc-detect = <&pio35 2 ALT1 IN>;
|
||||
usb-pwr-enable = <&pio35 3 ALT1 OUT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,300 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2014 STMicroelectronics Limited.
|
||||
* Author: Peter Griffin <peter.griffin@linaro.org>
|
||||
*/
|
||||
#include "stih410-clock.dtsi"
|
||||
#include "stih407-family.dtsi"
|
||||
#include "stih410-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
/ {
|
||||
aliases {
|
||||
bdisp0 = &bdisp0;
|
||||
};
|
||||
|
||||
soc {
|
||||
usb2_picophy1: phy2@0 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
reg = <0 0>;
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xf8 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY0_RESET>;
|
||||
reset-names = "global", "port";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb2_picophy2: phy3@0 {
|
||||
compatible = "st,stih407-usb2-phy";
|
||||
reg = <0 0>;
|
||||
#phy-cells = <0>;
|
||||
st,syscfg = <&syscfg_core 0xfc 0xf4>;
|
||||
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
||||
<&picophyreset STIH407_PICOPHY1_RESET>;
|
||||
reset-names = "global", "port";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci0: usb@9a03c00 {
|
||||
compatible = "st,st-ohci-300x";
|
||||
reg = <0x9a03c00 0x100>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
|
||||
<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
|
||||
resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
|
||||
<&softreset STIH407_USB2_PORT0_SOFTRESET>;
|
||||
reset-names = "power", "softreset";
|
||||
phys = <&usb2_picophy1>;
|
||||
phy-names = "usb";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci0: usb@9a03e00 {
|
||||
compatible = "st,st-ehci-300x";
|
||||
reg = <0x9a03e00 0x100>;
|
||||
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0>;
|
||||
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
|
||||
<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
|
||||
resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
|
||||
<&softreset STIH407_USB2_PORT0_SOFTRESET>;
|
||||
reset-names = "power", "softreset";
|
||||
phys = <&usb2_picophy1>;
|
||||
phy-names = "usb";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci1: usb@9a83c00 {
|
||||
compatible = "st,st-ohci-300x";
|
||||
reg = <0x9a83c00 0x100>;
|
||||
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
|
||||
<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
|
||||
resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
|
||||
<&softreset STIH407_USB2_PORT1_SOFTRESET>;
|
||||
reset-names = "power", "softreset";
|
||||
phys = <&usb2_picophy2>;
|
||||
phy-names = "usb";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci1: usb@9a83e00 {
|
||||
compatible = "st,st-ehci-300x";
|
||||
reg = <0x9a83e00 0x100>;
|
||||
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1>;
|
||||
clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
|
||||
<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
|
||||
resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
|
||||
<&softreset STIH407_USB2_PORT1_SOFTRESET>;
|
||||
reset-names = "power", "softreset";
|
||||
phys = <&usb2_picophy2>;
|
||||
phy-names = "usb";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sti-display-subsystem@0 {
|
||||
compatible = "st,sti-display-subsystem";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
reg = <0 0>;
|
||||
assigned-clocks = <&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 1>,
|
||||
<&clk_s_c0_pll1 0>,
|
||||
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
|
||||
<&clk_s_c0_flexgen CLK_MAIN_DISP>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_GDP1>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_GDP2>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_GDP3>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_GDP4>;
|
||||
|
||||
assigned-clock-parents = <0>,
|
||||
<0>,
|
||||
<0>,
|
||||
<&clk_s_c0_pll1 0>,
|
||||
<&clk_s_c0_pll1 0>,
|
||||
<&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 1>,
|
||||
<&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 0>;
|
||||
|
||||
assigned-clock-rates = <297000000>,
|
||||
<297000000>,
|
||||
<0>,
|
||||
<400000000>,
|
||||
<400000000>;
|
||||
|
||||
ranges;
|
||||
|
||||
sti-compositor@9d11000 {
|
||||
compatible = "st,stih407-compositor";
|
||||
reg = <0x9d11000 0x1000>;
|
||||
|
||||
clock-names = "compo_main",
|
||||
"compo_aux",
|
||||
"pix_main",
|
||||
"pix_aux",
|
||||
"pix_gdp1",
|
||||
"pix_gdp2",
|
||||
"pix_gdp3",
|
||||
"pix_gdp4",
|
||||
"main_parent",
|
||||
"aux_parent";
|
||||
|
||||
clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
|
||||
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_GDP1>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_GDP2>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_GDP3>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_GDP4>,
|
||||
<&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 1>;
|
||||
|
||||
reset-names = "compo-main", "compo-aux";
|
||||
resets = <&softreset STIH407_COMPO_SOFTRESET>,
|
||||
<&softreset STIH407_COMPO_SOFTRESET>;
|
||||
st,vtg = <&vtg_main>, <&vtg_aux>;
|
||||
};
|
||||
|
||||
sti-tvout@8d08000 {
|
||||
compatible = "st,stih407-tvout";
|
||||
reg = <0x8d08000 0x1000>;
|
||||
reg-names = "tvout-reg";
|
||||
reset-names = "tvout";
|
||||
resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
|
||||
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
|
||||
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
|
||||
<&clk_s_d0_flexgen CLK_PCM_0>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_HDDAC>,
|
||||
<&clk_s_d2_flexgen CLK_HDDAC>;
|
||||
|
||||
assigned-clock-parents = <&clk_s_d2_quadfs 0>,
|
||||
<&clk_tmdsout_hdmi>,
|
||||
<&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d0_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 0>;
|
||||
};
|
||||
|
||||
sti_hdmi: sti-hdmi@8d04000 {
|
||||
compatible = "st,stih407-hdmi";
|
||||
reg = <0x8d04000 0x1000>;
|
||||
reg-names = "hdmi-reg";
|
||||
#sound-dai-cells = <0>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "irq";
|
||||
clock-names = "pix",
|
||||
"tmds",
|
||||
"phy",
|
||||
"audio",
|
||||
"main_parent",
|
||||
"aux_parent";
|
||||
|
||||
clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
|
||||
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
|
||||
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
|
||||
<&clk_s_d0_flexgen CLK_PCM_0>,
|
||||
<&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 1>;
|
||||
|
||||
hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
|
||||
reset-names = "hdmi";
|
||||
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
|
||||
ddc = <&hdmiddc>;
|
||||
};
|
||||
|
||||
sti-hda@8d02000 {
|
||||
compatible = "st,stih407-hda";
|
||||
status = "disabled";
|
||||
reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
|
||||
reg-names = "hda-reg", "video-dacs-ctrl";
|
||||
clock-names = "pix",
|
||||
"hddac",
|
||||
"main_parent",
|
||||
"aux_parent";
|
||||
clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
|
||||
<&clk_s_d2_flexgen CLK_HDDAC>,
|
||||
<&clk_s_d2_quadfs 0>,
|
||||
<&clk_s_d2_quadfs 1>;
|
||||
};
|
||||
|
||||
sti-hqvdp@9c00000 {
|
||||
compatible = "st,stih407-hqvdp";
|
||||
reg = <0x9C00000 0x100000>;
|
||||
clock-names = "hqvdp", "pix_main";
|
||||
clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
|
||||
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
|
||||
reset-names = "hqvdp";
|
||||
resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
|
||||
st,vtg = <&vtg_main>;
|
||||
};
|
||||
};
|
||||
|
||||
bdisp0:bdisp@9f10000 {
|
||||
compatible = "st,stih407-bdisp";
|
||||
reg = <0x9f10000 0x1000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "bdisp";
|
||||
clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
|
||||
};
|
||||
|
||||
hva@8c85000 {
|
||||
compatible = "st,st-hva";
|
||||
reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
|
||||
reg-names = "hva_registers", "hva_esram";
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "clk_hva";
|
||||
clocks = <&clk_s_c0_flexgen CLK_HVA>;
|
||||
};
|
||||
|
||||
thermal@91a0000 {
|
||||
compatible = "st,stih407-thermal";
|
||||
reg = <0x91a0000 0x28>;
|
||||
clock-names = "thermal";
|
||||
clocks = <&clk_sysin>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
|
||||
delta0@0 {
|
||||
compatible = "st,st-delta";
|
||||
clock-names = "delta",
|
||||
"delta-st231",
|
||||
"delta-flash-promip";
|
||||
clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
|
||||
<&clk_s_c0_flexgen CLK_ST231_DMU>,
|
||||
<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
|
||||
};
|
||||
|
||||
sti-cec@94a087c {
|
||||
compatible = "st,stih-cec";
|
||||
reg = <0x94a087c 0x64>;
|
||||
clocks = <&clk_sysin>;
|
||||
clock-names = "cec-clk";
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cec-irq";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_cec0_default>;
|
||||
resets = <&softreset STIH407_LPM_SOFTRESET>;
|
||||
hdmi-phandle = <&sti_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,284 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2015, STMicroelectronics - All Rights Reserved
|
||||
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32f429.dtsi"
|
||||
#include "stm32f429-pinctrl.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32429i-EVAL board";
|
||||
compatible = "st,stm32429i-eval", "st,stm32f429";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@00000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x2000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_ext_camera: clk-ext-camera {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
dma-ranges = <0xc0000000 0x0 0x10000000>;
|
||||
};
|
||||
|
||||
vdda: regulator-vdda {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vref: regulator-vref {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vref";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_panel: vdd-panel {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_panel";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led-green {
|
||||
gpios = <&gpiog 6 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
led-orange {
|
||||
gpios = <&gpiog 7 1>;
|
||||
};
|
||||
led-red {
|
||||
gpios = <&gpiog 10 1>;
|
||||
};
|
||||
led-blue {
|
||||
gpios = <&gpiog 12 1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
button@0 {
|
||||
label = "Wake up";
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
gpios = <&gpioa 0 0>;
|
||||
};
|
||||
button@1 {
|
||||
label = "Tamper";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpioc 13 0>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_phy: usbphy {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
panel_rgb: panel-rgb {
|
||||
compatible = "ampire,am-480272h3tmqw-t01h";
|
||||
power-supply = <&vdd_panel>;
|
||||
status = "okay";
|
||||
port {
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <<dc_out_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mmc_vcard: mmc_vcard {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "mmc_vcard";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&adc3_in8_pin>;
|
||||
vdda-supply = <&vdda>;
|
||||
vref-supply = <&vref>;
|
||||
status = "okay";
|
||||
adc3: adc@200 {
|
||||
st,adc-channels = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&crc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcmi {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
dcmi_0: endpoint {
|
||||
remote-endpoint = <&ov2640_0>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
ov2640: camera@30 {
|
||||
compatible = "ovti,ov2640";
|
||||
reg = <0x30>;
|
||||
resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>;
|
||||
pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk_ext_camera>;
|
||||
clock-names = "xvclk";
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
ov2640_0: endpoint {
|
||||
remote-endpoint = <&dcmi_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stmpe1600: stmpe1600@42 {
|
||||
compatible = "st,stmpe1600";
|
||||
reg = <0x42>;
|
||||
interrupts = <8 3>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
interrupt-controller;
|
||||
wakeup-source;
|
||||
|
||||
stmpegpio: stmpe_gpio {
|
||||
compatible = "st,stmpe-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iwdg {
|
||||
status = "okay";
|
||||
timeout-sec = <32>;
|
||||
};
|
||||
|
||||
<dc {
|
||||
status = "okay";
|
||||
pinctrl-0 = <<dc_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
ltdc_out_rgb: endpoint {
|
||||
remote-endpoint = <&panel_in_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ðernet_mii>;
|
||||
pinctrl-names = "default";
|
||||
phy-mode = "mii";
|
||||
phy-handle = <&phy1>;
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio {
|
||||
status = "okay";
|
||||
vmmc-supply = <&mmc_vcard>;
|
||||
cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "opendrain";
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
pinctrl-1 = <&sdio_pins_od>;
|
||||
bus-width = <4>;
|
||||
max-frequency = <12500000>;
|
||||
};
|
||||
|
||||
&timers1 {
|
||||
status = "okay";
|
||||
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
timer@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers3 {
|
||||
status = "okay";
|
||||
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm3_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
timer@2 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
dr_mode = "host";
|
||||
phys = <&usbotg_hs_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,186 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32f746.dtsi"
|
||||
#include "stm32f746-pinctrl.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32746g-EVAL board";
|
||||
compatible = "st,stm32746g-eval", "st,stm32f746";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x2000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led-green {
|
||||
gpios = <&gpiof 10 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
led-orange {
|
||||
gpios = <&stmfx_pinctrl 17 1>;
|
||||
};
|
||||
led-red {
|
||||
gpios = <&gpiob 7 1>;
|
||||
};
|
||||
led-blue {
|
||||
gpios = <&stmfx_pinctrl 19 1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
button-0 {
|
||||
label = "Wake up";
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
gpios = <&gpioc 13 0>;
|
||||
};
|
||||
};
|
||||
|
||||
joystick {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&joystick_pins>;
|
||||
pinctrl-names = "default";
|
||||
button-0 {
|
||||
label = "JoySel";
|
||||
linux,code = <KEY_ENTER>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
button-1 {
|
||||
label = "JoyDown";
|
||||
linux,code = <KEY_DOWN>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
button-2 {
|
||||
label = "JoyLeft";
|
||||
linux,code = <KEY_LEFT>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
button-3 {
|
||||
label = "JoyRight";
|
||||
linux,code = <KEY_RIGHT>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
button-4 {
|
||||
label = "JoyUp";
|
||||
linux,code = <KEY_UP>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_phy: usb-phy {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
mmc_vcard: mmc_vcard {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "mmc_vcard";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&crc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins_b>;
|
||||
pinctrl-names = "default";
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
|
||||
stmfx: stmfx@42 {
|
||||
compatible = "st,stmfx-0300";
|
||||
reg = <0x42>;
|
||||
interrupts = <8 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
|
||||
stmfx_pinctrl: pinctrl {
|
||||
compatible = "st,stmfx-0300-pinctrl";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
||||
|
||||
joystick_pins: joystick {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&mmc_vcard>;
|
||||
broken-cd;
|
||||
pinctrl-names = "default", "opendrain";
|
||||
pinctrl-0 = <&sdio_pins_a>;
|
||||
pinctrl-1 = <&sdio_pins_od_a>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&timers5 {
|
||||
/* Override timer5 to act as clockevent */
|
||||
compatible = "st,stm32-timer";
|
||||
interrupts = <50>;
|
||||
status = "okay";
|
||||
/delete-property/#address-cells;
|
||||
/delete-property/#size-cells;
|
||||
/delete-property/clock-names;
|
||||
/delete-node/pwm;
|
||||
/delete-node/timer@4;
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
dr_mode = "otg";
|
||||
phys = <&usbotg_hs_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,447 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
#include <dt-bindings/mfd/stm32f4-rcc.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pinctrl@40020000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x40020000 0x3000>;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&syscfg 0x8>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@40020000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
|
||||
st,bank-name = "GPIOA";
|
||||
};
|
||||
|
||||
gpiob: gpio@40020400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x400 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
|
||||
st,bank-name = "GPIOB";
|
||||
};
|
||||
|
||||
gpioc: gpio@40020800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x800 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
|
||||
st,bank-name = "GPIOC";
|
||||
};
|
||||
|
||||
gpiod: gpio@40020c00 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xc00 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
|
||||
st,bank-name = "GPIOD";
|
||||
};
|
||||
|
||||
gpioe: gpio@40021000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
|
||||
st,bank-name = "GPIOE";
|
||||
};
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1400 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
|
||||
st,bank-name = "GPIOF";
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1800 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
|
||||
st,bank-name = "GPIOG";
|
||||
};
|
||||
|
||||
gpioh: gpio@40021c00 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1c00 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
|
||||
st,bank-name = "GPIOH";
|
||||
};
|
||||
|
||||
gpioi: gpio@40022000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
|
||||
st,bank-name = "GPIOI";
|
||||
};
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2400 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
|
||||
st,bank-name = "GPIOJ";
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2800 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
|
||||
st,bank-name = "GPIOK";
|
||||
};
|
||||
|
||||
usart1_pins_a: usart1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart3_pins_a: usart3-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_fs_pins_a: usbotg-fs-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
|
||||
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
|
||||
<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_fs_pins_b: usbotg-fs-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF12)>, /* OTG_HS_ID */
|
||||
<STM32_PINMUX('B', 14, AF12)>, /* OTG_HS_DM */
|
||||
<STM32_PINMUX('B', 15, AF12)>; /* OTG_HS_DP */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_a: usbotg-hs-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT*/
|
||||
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
|
||||
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
|
||||
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
|
||||
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
|
||||
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
|
||||
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
|
||||
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
|
||||
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
|
||||
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
|
||||
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
|
||||
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet_mii: mii-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_MII_TXD0_ETH_RMII_TXD0 */
|
||||
<STM32_PINMUX('G', 14, AF11)>, /* ETH_MII_TXD1_ETH_RMII_TXD1 */
|
||||
<STM32_PINMUX('C', 2, AF11)>, /* ETH_MII_TXD2 */
|
||||
<STM32_PINMUX('B', 8, AF11)>, /* ETH_MII_TXD3 */
|
||||
<STM32_PINMUX('C', 3, AF11)>, /* ETH_MII_TX_CLK */
|
||||
<STM32_PINMUX('G', 11,AF11)>, /* ETH_MII_TX_EN_ETH_RMII_TX_EN */
|
||||
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
|
||||
<STM32_PINMUX('C', 1, AF11)>, /* ETH_MDC */
|
||||
<STM32_PINMUX('A', 1, AF11)>, /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */
|
||||
<STM32_PINMUX('A', 7, AF11)>, /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */
|
||||
<STM32_PINMUX('C', 4, AF11)>, /* ETH_MII_RXD0_ETH_RMII_RXD0 */
|
||||
<STM32_PINMUX('C', 5, AF11)>, /* ETH_MII_RXD1_ETH_RMII_RXD1 */
|
||||
<STM32_PINMUX('H', 6, AF11)>, /* ETH_MII_RXD2 */
|
||||
<STM32_PINMUX('H', 7, AF11)>; /* ETH_MII_RXD3 */
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
adc3_in8_pin: adc-200 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 10, ANALOG)>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1_pins: pwm1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 8, AF1)>, /* TIM1_CH1 */
|
||||
<STM32_PINMUX('B', 13, AF1)>, /* TIM1_CH1N */
|
||||
<STM32_PINMUX('B', 12, AF1)>; /* TIM1_BKIN */
|
||||
};
|
||||
};
|
||||
|
||||
pwm3_pins: pwm3-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 4, AF2)>, /* TIM3_CH1 */
|
||||
<STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1_SDA */
|
||||
<STM32_PINMUX('B', 6, AF4)>; /* I2C1_SCL */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
ltdc_pins_a: ltdc-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
|
||||
<STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
|
||||
<STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
|
||||
<STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
|
||||
<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
|
||||
<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
|
||||
<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
|
||||
<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
|
||||
<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
|
||||
<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6*/
|
||||
<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
|
||||
<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
|
||||
<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
|
||||
<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
|
||||
<STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
|
||||
<STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
|
||||
<STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
|
||||
<STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
|
||||
<STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
|
||||
<STM32_PINMUX('J', 15, AF14)>, /* LCD_B3*/
|
||||
<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
|
||||
<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
|
||||
<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
|
||||
<STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
|
||||
<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
|
||||
<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
|
||||
<STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
|
||||
<STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
ltdc_pins_b: ltdc-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 6, AF14)>,
|
||||
/* LCD_HSYNC */
|
||||
<STM32_PINMUX('A', 4, AF14)>,
|
||||
/* LCD_VSYNC */
|
||||
<STM32_PINMUX('G', 7, AF14)>,
|
||||
/* LCD_CLK */
|
||||
<STM32_PINMUX('C', 10, AF14)>,
|
||||
/* LCD_R2 */
|
||||
<STM32_PINMUX('B', 0, AF9)>,
|
||||
/* LCD_R3 */
|
||||
<STM32_PINMUX('A', 11, AF14)>,
|
||||
/* LCD_R4 */
|
||||
<STM32_PINMUX('A', 12, AF14)>,
|
||||
/* LCD_R5 */
|
||||
<STM32_PINMUX('B', 1, AF9)>,
|
||||
/* LCD_R6*/
|
||||
<STM32_PINMUX('G', 6, AF14)>,
|
||||
/* LCD_R7 */
|
||||
<STM32_PINMUX('A', 6, AF14)>,
|
||||
/* LCD_G2 */
|
||||
<STM32_PINMUX('G', 10, AF9)>,
|
||||
/* LCD_G3 */
|
||||
<STM32_PINMUX('B', 10, AF14)>,
|
||||
/* LCD_G4 */
|
||||
<STM32_PINMUX('D', 6, AF14)>,
|
||||
/* LCD_B2 */
|
||||
<STM32_PINMUX('G', 11, AF14)>,
|
||||
/* LCD_B3*/
|
||||
<STM32_PINMUX('B', 11, AF14)>,
|
||||
/* LCD_G5 */
|
||||
<STM32_PINMUX('C', 7, AF14)>,
|
||||
/* LCD_G6 */
|
||||
<STM32_PINMUX('D', 3, AF14)>,
|
||||
/* LCD_G7 */
|
||||
<STM32_PINMUX('G', 12, AF9)>,
|
||||
/* LCD_B4 */
|
||||
<STM32_PINMUX('A', 3, AF14)>,
|
||||
/* LCD_B5 */
|
||||
<STM32_PINMUX('B', 8, AF14)>,
|
||||
/* LCD_B6 */
|
||||
<STM32_PINMUX('B', 9, AF14)>,
|
||||
/* LCD_B7 */
|
||||
<STM32_PINMUX('F', 10, AF14)>;
|
||||
/* LCD_DE */
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
spi5_pins: spi5-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('F', 7, AF5)>,
|
||||
/* SPI5_CLK */
|
||||
<STM32_PINMUX('F', 9, AF5)>;
|
||||
/* SPI5_MOSI */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('F', 8, AF5)>;
|
||||
/* SPI5_MISO */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3_pins: i2c3-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 9, AF4)>,
|
||||
/* I2C3_SDA */
|
||||
<STM32_PINMUX('A', 8, AF4)>;
|
||||
/* I2C3_SCL */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
dcmi_pins: dcmi-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
|
||||
<STM32_PINMUX('B', 7, AF13)>, /* DCMI_VSYNC */
|
||||
<STM32_PINMUX('A', 6, AF13)>, /* DCMI_PIXCLK */
|
||||
<STM32_PINMUX('C', 6, AF13)>, /* DCMI_D0 */
|
||||
<STM32_PINMUX('C', 7, AF13)>, /* DCMI_D1 */
|
||||
<STM32_PINMUX('C', 8, AF13)>, /* DCMI_D2 */
|
||||
<STM32_PINMUX('C', 9, AF13)>, /* DCMI_D3 */
|
||||
<STM32_PINMUX('C', 11, AF13)>, /*DCMI_D4 */
|
||||
<STM32_PINMUX('D', 3, AF13)>, /* DCMI_D5 */
|
||||
<STM32_PINMUX('B', 8, AF13)>, /* DCMI_D6 */
|
||||
<STM32_PINMUX('E', 6, AF13)>, /* DCMI_D7 */
|
||||
<STM32_PINMUX('C', 10, AF13)>, /* DCMI_D8 */
|
||||
<STM32_PINMUX('C', 12, AF13)>, /* DCMI_D9 */
|
||||
<STM32_PINMUX('D', 6, AF13)>, /* DCMI_D10 */
|
||||
<STM32_PINMUX('D', 2, AF13)>; /* DCMI_D11 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins: sdio-pins-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
|
||||
<STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
|
||||
<STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins_od: sdio-pins-od-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
|
||||
<STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
|
||||
drive-open-drain;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
can1_pins_a: can1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
can2_pins_a: can2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
can2_pins_b: can2-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,190 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32f429.dtsi"
|
||||
#include "stm32f429-pinctrl.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32F429i-DISCO board";
|
||||
compatible = "st,stm32f429i-disco", "st,stm32f429";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@90000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x90000000 0x800000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led-red {
|
||||
gpios = <&gpiog 14 0>;
|
||||
};
|
||||
led-green {
|
||||
gpios = <&gpiog 13 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
button-0 {
|
||||
label = "User";
|
||||
linux,code = <KEY_HOME>;
|
||||
gpios = <&gpioa 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* This turns on vbus for otg for host mode (dwc2) */
|
||||
vcc5v_otg: vcc5v-otg-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpioc 4 0>;
|
||||
regulator-name = "vcc5_host1";
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <8000000>;
|
||||
};
|
||||
|
||||
&crc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
stmpe811@41 {
|
||||
compatible = "st,stmpe811";
|
||||
reg = <0x41>;
|
||||
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpioa>;
|
||||
/* 3.25 MHz ADC clock speed */
|
||||
st,adc-freq = <1>;
|
||||
/* 12-bit ADC */
|
||||
st,mod-12b = <1>;
|
||||
/* internal ADC reference */
|
||||
st,ref-sel = <0>;
|
||||
/* ADC converstion time: 80 clocks */
|
||||
st,sample-time = <4>;
|
||||
|
||||
stmpe_touchscreen {
|
||||
compatible = "st,stmpe-ts";
|
||||
/* 8 sample average control */
|
||||
st,ave-ctrl = <3>;
|
||||
/* 7 length fractional part in z */
|
||||
st,fraction-z = <7>;
|
||||
/*
|
||||
* 50 mA typical 80 mA max touchscreen drivers
|
||||
* current limit value
|
||||
*/
|
||||
st,i-drive = <1>;
|
||||
/* 1 ms panel driver settling time */
|
||||
st,settling = <3>;
|
||||
/* 5 ms touch detect interrupt delay */
|
||||
st,touch-det-delay = <5>;
|
||||
};
|
||||
|
||||
stmpe_adc {
|
||||
compatible = "st,stmpe-adc";
|
||||
/* forbid to use ADC channels 3-0 (touch) */
|
||||
st,norequest-mask = <0x0F>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
<dc {
|
||||
status = "okay";
|
||||
pinctrl-0 = <<dc_pins_b>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
ltdc_out_rgb: endpoint {
|
||||
remote-endpoint = <&panel_in_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
assigned-clocks = <&rcc 1 CLK_RTC>;
|
||||
assigned-clock-parents = <&rcc 1 CLK_LSI>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi5 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spi5_pins>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>;
|
||||
|
||||
l3gd20: l3gd20@0 {
|
||||
compatible = "st,l3gd20-gyro";
|
||||
spi-max-frequency = <10000000>;
|
||||
st,drdy-int-pin = <2>;
|
||||
interrupt-parent = <&gpioa>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_RISING>,
|
||||
<2 IRQ_TYPE_EDGE_RISING>;
|
||||
reg = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
display: display@1{
|
||||
/* Connect panel-ilitek-9341 to ltdc */
|
||||
compatible = "st,sf-tc240t-9370-t", "ilitek,ili9341";
|
||||
reg = <1>;
|
||||
spi-3wire;
|
||||
spi-max-frequency = <10000000>;
|
||||
dc-gpios = <&gpiod 13 0>;
|
||||
port {
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <<dc_out_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&timers5 {
|
||||
/* Override timer5 to act as clockevent */
|
||||
compatible = "st,stm32-timer";
|
||||
interrupts = <50>;
|
||||
status = "okay";
|
||||
/delete-property/#address-cells;
|
||||
/delete-property/#size-cells;
|
||||
/delete-property/clock-names;
|
||||
/delete-node/pwm;
|
||||
/delete-node/timer@4;
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
compatible = "st,stm32f4x9-fsotg";
|
||||
dr_mode = "host";
|
||||
pinctrl-0 = <&usbotg_fs_pins_b>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,55 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "stm32f4-pinctrl.dtsi"
|
||||
|
||||
&pinctrl {
|
||||
compatible = "st,stm32f429-pinctrl";
|
||||
|
||||
gpioa: gpio@40020000 {
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@40020400 {
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@40020800 {
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@40020c00 {
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@40021000 {
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@40021c00 {
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@40022000 {
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
@@ -1,758 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "armv7-m.dtsi"
|
||||
#include <dt-bindings/clock/stm32fx-clock.h>
|
||||
#include <dt-bindings/mfd/stm32f4-rcc.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
clk_i2s_ckin: i2s-ckin {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
romem: efuse@1fff7800 {
|
||||
compatible = "st,stm32f4-otp";
|
||||
reg = <0x1fff7800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ts_cal1: calib@22c {
|
||||
reg = <0x22c 0x2>;
|
||||
};
|
||||
ts_cal2: calib@22e {
|
||||
reg = <0x22e 0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
timers2: timers@40000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@1 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers3: timers@40000400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000400 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@2 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers4: timers@40000800 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000800 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@3 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers5: timers@40000c00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000C00 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@4 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers6: timers@40001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
timer@5 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers7: timers@40001400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001400 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
timer@6 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers12: timers@40001800 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001800 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@11 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers13: timers@40001c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001C00 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers14: timers@40002000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40002000 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc@40002800 {
|
||||
compatible = "st,stm32-rtc";
|
||||
reg = <0x40002800 0x400>;
|
||||
clocks = <&rcc 1 CLK_RTC>;
|
||||
assigned-clocks = <&rcc 1 CLK_RTC>;
|
||||
assigned-clock-parents = <&rcc 1 CLK_LSE>;
|
||||
interrupt-parent = <&exti>;
|
||||
interrupts = <17 1>;
|
||||
st,syscfg = <&pwrcfg 0x00 0x100>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iwdg: watchdog@40003000 {
|
||||
compatible = "st,stm32-iwdg";
|
||||
reg = <0x40003000 0x400>;
|
||||
clocks = <&clk_lsi>;
|
||||
clock-names = "lsi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32f4-spi";
|
||||
reg = <0x40003800 0x400>;
|
||||
interrupts = <36>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32f4-spi";
|
||||
reg = <0x40003c00 0x400>;
|
||||
interrupts = <51>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
interrupts = <38>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
interrupts = <39>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
|
||||
status = "disabled";
|
||||
dmas = <&dma1 1 4 0x400 0x0>,
|
||||
<&dma1 3 4 0x400 0x0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
usart4: serial@40004c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
interrupts = <52>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart5: serial@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
interrupts = <53>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@40005400 {
|
||||
compatible = "st,stm32f4-i2c";
|
||||
reg = <0x40005400 0x400>;
|
||||
interrupts = <31>,
|
||||
<32>;
|
||||
resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@40005c00 {
|
||||
compatible = "st,stm32f4-i2c";
|
||||
reg = <0x40005c00 0x400>;
|
||||
interrupts = <72>,
|
||||
<73>;
|
||||
resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32f4-bxcan";
|
||||
reg = <0x40006400 0x200>;
|
||||
interrupts = <19>, <20>, <21>, <22>;
|
||||
interrupt-names = "tx", "rx0", "rx1", "sce";
|
||||
resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
|
||||
st,can-primary;
|
||||
st,gcan = <&gcan>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gcan: gcan@40006600 {
|
||||
compatible = "st,stm32f4-gcan", "syscon";
|
||||
reg = <0x40006600 0x200>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
|
||||
};
|
||||
|
||||
can2: can@40006800 {
|
||||
compatible = "st,stm32f4-bxcan";
|
||||
reg = <0x40006800 0x200>;
|
||||
interrupts = <63>, <64>, <65>, <66>;
|
||||
interrupt-names = "tx", "rx0", "rx1", "sce";
|
||||
resets = <&rcc STM32F4_APB1_RESET(CAN2)>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
|
||||
st,can-secondary;
|
||||
st,gcan = <&gcan>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dac: dac@40007400 {
|
||||
compatible = "st,stm32f4-dac-core";
|
||||
reg = <0x40007400 0x400>;
|
||||
resets = <&rcc STM32F4_APB1_RESET(DAC)>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
|
||||
clock-names = "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
dac1: dac@1 {
|
||||
compatible = "st,stm32-dac";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dac2: dac@2 {
|
||||
compatible = "st,stm32-dac";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usart7: serial@40007800 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007800 0x400>;
|
||||
interrupts = <82>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart8: serial@40007c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007c00 0x400>;
|
||||
interrupts = <83>;
|
||||
clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timers1: timers@40010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@0 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers8: timers@40010400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010400 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@7 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <7>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usart1: serial@40011000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
interrupts = <37>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
|
||||
status = "disabled";
|
||||
dmas = <&dma2 2 4 0x400 0x0>,
|
||||
<&dma2 7 4 0x400 0x0>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
usart6: serial@40011400 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40011400 0x400>;
|
||||
interrupts = <71>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc: adc@40012000 {
|
||||
compatible = "st,stm32f4-adc-core";
|
||||
reg = <0x40012000 0x400>;
|
||||
interrupts = <18>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
|
||||
clock-names = "adc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
adc1: adc@0 {
|
||||
compatible = "st,stm32f4-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x0>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
|
||||
interrupt-parent = <&adc>;
|
||||
interrupts = <0>;
|
||||
dmas = <&dma2 0 0 0x400 0x0>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc2: adc@100 {
|
||||
compatible = "st,stm32f4-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x100>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
|
||||
interrupt-parent = <&adc>;
|
||||
interrupts = <1>;
|
||||
dmas = <&dma2 3 1 0x400 0x0>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc3: adc@200 {
|
||||
compatible = "st,stm32f4-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x200>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
|
||||
interrupt-parent = <&adc>;
|
||||
interrupts = <2>;
|
||||
dmas = <&dma2 1 2 0x400 0x0>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
sdio: mmc@40012c00 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00880180>;
|
||||
reg = <0x40012c00 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
|
||||
clock-names = "apb_pclk";
|
||||
interrupts = <49>;
|
||||
max-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@40013000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32f4-spi";
|
||||
reg = <0x40013000 0x400>;
|
||||
interrupts = <35>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@40013400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32f4-spi";
|
||||
reg = <0x40013400 0x400>;
|
||||
interrupts = <84>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscfg: syscon@40013800 {
|
||||
compatible = "st,stm32-syscfg", "syscon";
|
||||
reg = <0x40013800 0x400>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@40013c00 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40013C00 0x400>;
|
||||
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
|
||||
};
|
||||
|
||||
timers9: timers@40014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014000 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@8 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <8>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers10: timers@40014400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014400 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers11: timers@40014800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014800 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi5: spi@40015000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32f4-spi";
|
||||
reg = <0x40015000 0x400>;
|
||||
interrupts = <85>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
|
||||
dmas = <&dma2 3 2 0x400 0x0>,
|
||||
<&dma2 4 2 0x400 0x0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi6: spi@40015400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32f4-spi";
|
||||
reg = <0x40015400 0x400>;
|
||||
interrupts = <86>;
|
||||
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwrcfg: power-config@40007000 {
|
||||
compatible = "st,stm32-power-config", "syscon";
|
||||
reg = <0x40007000 0x400>;
|
||||
};
|
||||
|
||||
ltdc: display-controller@40016800 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x40016800 0x200>;
|
||||
interrupts = <88>, <89>;
|
||||
resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
|
||||
clocks = <&rcc 1 CLK_LCD>;
|
||||
clock-names = "lcd";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crc: crc@40023000 {
|
||||
compatible = "st,stm32f4-crc";
|
||||
reg = <0x40023000 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcc: rcc@40023800 {
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <2>;
|
||||
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
|
||||
reg = <0x40023800 0x400>;
|
||||
clocks = <&clk_hse>, <&clk_i2s_ckin>;
|
||||
st,syscfg = <&pwrcfg>;
|
||||
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
|
||||
assigned-clock-rates = <1000000>;
|
||||
};
|
||||
|
||||
dma1: dma-controller@40026000 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x40026000 0x400>;
|
||||
interrupts = <11>,
|
||||
<12>,
|
||||
<13>,
|
||||
<14>,
|
||||
<15>,
|
||||
<16>,
|
||||
<17>,
|
||||
<47>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
|
||||
#dma-cells = <4>;
|
||||
};
|
||||
|
||||
dma2: dma-controller@40026400 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x40026400 0x400>;
|
||||
interrupts = <56>,
|
||||
<57>,
|
||||
<58>,
|
||||
<59>,
|
||||
<60>,
|
||||
<68>,
|
||||
<69>,
|
||||
<70>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
|
||||
#dma-cells = <4>;
|
||||
st,mem2mem;
|
||||
};
|
||||
|
||||
mac: ethernet@40028000 {
|
||||
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
|
||||
reg = <0x40028000 0x8000>;
|
||||
reg-names = "stmmaceth";
|
||||
interrupts = <61>;
|
||||
interrupt-names = "macirq";
|
||||
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
|
||||
<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
|
||||
<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
|
||||
st,syscon = <&syscfg 0x4>;
|
||||
snps,pbl = <8>;
|
||||
snps,mixed-burst;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma2d: dma2d@4002b000 {
|
||||
compatible = "st,stm32-dma2d";
|
||||
reg = <0x4002b000 0xc00>;
|
||||
interrupts = <90>;
|
||||
resets = <&rcc STM32F4_AHB1_RESET(DMA2D)>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
|
||||
clock-names = "dma2d";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg_hs: usb@40040000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0x40040000 0x40000>;
|
||||
interrupts = <77>;
|
||||
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
|
||||
clock-names = "otg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg_fs: usb@50000000 {
|
||||
compatible = "st,stm32f4x9-fsotg";
|
||||
reg = <0x50000000 0x40000>;
|
||||
interrupts = <67>;
|
||||
clocks = <&rcc 0 39>;
|
||||
clock-names = "otg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dcmi: dcmi@50050000 {
|
||||
compatible = "st,stm32-dcmi";
|
||||
reg = <0x50050000 0x400>;
|
||||
interrupts = <78>;
|
||||
resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
|
||||
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
|
||||
clock-names = "mclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dcmi_pins>;
|
||||
dmas = <&dma2 1 1 0x414 0x3>;
|
||||
dma-names = "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rng: rng@50060800 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x50060800 0x400>;
|
||||
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&systick {
|
||||
clocks = <&rcc 1 SYSTICK>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,213 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2016 - Lee Jones <lee.jones@linaro.org>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32f469.dtsi"
|
||||
#include "stm32f469-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32F469i-DISCO board";
|
||||
compatible = "st,stm32f469i-disco", "st,stm32f469";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x1000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &usart3;
|
||||
};
|
||||
|
||||
mmc_vcard: mmc_vcard {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "mmc_vcard";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_dsi: vdd-dsi {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_dsi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
dma-ranges = <0xc0000000 0x0 0x10000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led-green {
|
||||
gpios = <&gpiog 6 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
led-orange {
|
||||
gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
led-red {
|
||||
gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
led-blue {
|
||||
gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
button-0 {
|
||||
label = "User";
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
/* This turns on vbus for otg for host mode (dwc2) */
|
||||
vcc5v_otg: vcc5v-otg-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpiob 2 GPIO_ACTIVE_HIGH>;
|
||||
regulator-name = "vcc5_host1";
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&rcc {
|
||||
compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <8000000>;
|
||||
};
|
||||
|
||||
&dma2d {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <<dc_out_dsi>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi_out: endpoint {
|
||||
remote-endpoint = <&dsi_panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel@0 {
|
||||
compatible = "orisetech,otm8009a";
|
||||
reg = <0>; /* dsi virtual channel (0..3) */
|
||||
reset-gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
|
||||
power-supply = <&vdd_dsi>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
dsi_panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
<dc {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
ltdc_out_dsi: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timers1 {
|
||||
status = "okay";
|
||||
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
timer@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers3 {
|
||||
status = "okay";
|
||||
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm3_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
timer@2 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&sdio {
|
||||
status = "okay";
|
||||
vmmc-supply = <&mmc_vcard>;
|
||||
cd-gpios = <&gpiog 2 GPIO_ACTIVE_LOW>;
|
||||
broken-cd;
|
||||
pinctrl-names = "default", "opendrain";
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
pinctrl-1 = <&sdio_pins_od>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&timers5 {
|
||||
/* Override timer5 to act as clockevent */
|
||||
compatible = "st,stm32-timer";
|
||||
interrupts = <50>;
|
||||
status = "okay";
|
||||
/delete-property/#address-cells;
|
||||
/delete-property/#size-cells;
|
||||
/delete-property/clock-names;
|
||||
/delete-node/pwm;
|
||||
/delete-node/timer@4;
|
||||
};
|
||||
|
||||
&usart3 {
|
||||
pinctrl-0 = <&usart3_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_fs {
|
||||
dr_mode = "host";
|
||||
pinctrl-0 = <&usbotg_fs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,55 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*/
|
||||
|
||||
#include "stm32f4-pinctrl.dtsi"
|
||||
|
||||
&pinctrl {
|
||||
compatible = "st,stm32f469-pinctrl";
|
||||
|
||||
gpioa: gpio@40020000 {
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@40020400 {
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@40020800 {
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@40020c00 {
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@40021000 {
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@40021c00 {
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@40022000 {
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
gpio-ranges = <&pinctrl 0 144 6>,
|
||||
<&pinctrl 12 156 4>;
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
gpio-ranges = <&pinctrl 3 163 5>;
|
||||
};
|
||||
};
|
||||
@@ -1,18 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/* Copyright (C) STMicroelectronics 2017 - All Rights Reserved */
|
||||
|
||||
#include "stm32f429.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
dsi: dsi@40016c00 {
|
||||
compatible = "st,stm32-dsi";
|
||||
reg = <0x40016c00 0x800>;
|
||||
resets = <&rcc STM32F4_APB2_RESET(DSI)>;
|
||||
reset-names = "apb";
|
||||
clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
|
||||
clock-names = "pclk", "ref";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,415 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
#include <dt-bindings/mfd/stm32f7-rcc.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pinctrl@40020000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x40020000 0x3000>;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&syscfg 0x8>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@40020000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
|
||||
st,bank-name = "GPIOA";
|
||||
};
|
||||
|
||||
gpiob: gpio@40020400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
|
||||
st,bank-name = "GPIOB";
|
||||
};
|
||||
|
||||
gpioc: gpio@40020800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
|
||||
st,bank-name = "GPIOC";
|
||||
};
|
||||
|
||||
gpiod: gpio@40020c00 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xc00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
|
||||
st,bank-name = "GPIOD";
|
||||
};
|
||||
|
||||
gpioe: gpio@40021000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
|
||||
st,bank-name = "GPIOE";
|
||||
};
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
|
||||
st,bank-name = "GPIOF";
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
|
||||
st,bank-name = "GPIOG";
|
||||
};
|
||||
|
||||
gpioh: gpio@40021c00 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x1c00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
|
||||
st,bank-name = "GPIOH";
|
||||
};
|
||||
|
||||
gpioi: gpio@40022000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
|
||||
st,bank-name = "GPIOI";
|
||||
};
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOJ)>;
|
||||
st,bank-name = "GPIOJ";
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x2800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOK)>;
|
||||
st,bank-name = "GPIOK";
|
||||
};
|
||||
|
||||
cec_pins_a: cec-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 15, AF4)>; /* HDMI CEC */
|
||||
slew-rate = <0>;
|
||||
drive-open-drain;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_a: usart1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 10, AF7)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_b: usart1-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 7, AF7)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_b: i2c1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 9, AF4)>, /* I2C1 SDA */
|
||||
<STM32_PINMUX('B', 8, AF4)>; /* I2C1 SCL */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3_pins_a: i2c3-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */
|
||||
<STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_a: usbotg-hs-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
|
||||
<STM32_PINMUX('I', 11, AF10)>, /* OTG_HS_ULPI_DIR */
|
||||
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
|
||||
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
|
||||
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
|
||||
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
|
||||
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
|
||||
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
|
||||
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
|
||||
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
|
||||
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
|
||||
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_b: usbotg-hs-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */
|
||||
<STM32_PINMUX('C', 2, AF10)>, /* OTG_HS_ULPI_DIR */
|
||||
<STM32_PINMUX('C', 0, AF10)>, /* OTG_HS_ULPI_STP */
|
||||
<STM32_PINMUX('A', 5, AF10)>, /* OTG_HS_ULPI_CK */
|
||||
<STM32_PINMUX('A', 3, AF10)>, /* OTG_HS_ULPI_D0 */
|
||||
<STM32_PINMUX('B', 0, AF10)>, /* OTG_HS_ULPI_D1 */
|
||||
<STM32_PINMUX('B', 1, AF10)>, /* OTG_HS_ULPI_D2 */
|
||||
<STM32_PINMUX('B', 10, AF10)>, /* OTG_HS_ULPI_D3 */
|
||||
<STM32_PINMUX('B', 11, AF10)>, /* OTG_HS_ULPI_D4 */
|
||||
<STM32_PINMUX('B', 12, AF10)>, /* OTG_HS_ULPI_D5 */
|
||||
<STM32_PINMUX('B', 13, AF10)>, /* OTG_HS_ULPI_D6 */
|
||||
<STM32_PINMUX('B', 5, AF10)>; /* OTG_HS_ULPI_D7 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_fs_pins_a: usbotg-fs-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 10, AF10)>, /* OTG_FS_ID */
|
||||
<STM32_PINMUX('A', 11, AF10)>, /* OTG_FS_DM */
|
||||
<STM32_PINMUX('A', 12, AF10)>; /* OTG_FS_DP */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins_a: sdio-pins-a-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
|
||||
<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1 CLK */
|
||||
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins_od_a: sdio-pins-od-a-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1 D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1 D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1 D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1 D3 */
|
||||
<STM32_PINMUX('C', 12, AF12)>; /* SDMMC1 CLK */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1 CMD */
|
||||
drive-open-drain;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins_b: sdio-pins-b-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
|
||||
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
|
||||
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
|
||||
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
|
||||
<STM32_PINMUX('D', 6, AF11)>, /* SDMMC2 CLK */
|
||||
<STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pins_od_b: sdio-pins-od-b-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
|
||||
<STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
|
||||
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2 D2 */
|
||||
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2 D3 */
|
||||
<STM32_PINMUX('D', 6, AF11)>; /* SDMMC2 CLK */
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC2 CMD */
|
||||
drive-open-drain;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
can1_pins_a: can1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
can1_pins_b: can1-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 9, AF9)>; /* CAN1_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 8, AF9)>; /* CAN1_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
can1_pins_c: can1-2 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 1, AF9)>; /* CAN1_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
|
||||
bias-pull-up;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
can1_pins_d: can1-3 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('H', 14, AF9)>; /* CAN1_RX */
|
||||
bias-pull-up;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
can2_pins_a: can2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 6, AF9)>; /* CAN2_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
can2_pins_b: can2-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF9)>; /* CAN2_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
can3_pins_a: can3-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 15, AF11)>; /* CAN3_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 8, AF11)>; /* CAN3_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
can3_pins_b: can3-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 4, AF11)>; /* CAN3_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 3, AF11)>; /* CAN3_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
ltdc_pins_a: ltdc-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */
|
||||
<STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */
|
||||
<STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
|
||||
<STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */
|
||||
<STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */
|
||||
<STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */
|
||||
<STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
|
||||
<STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
|
||||
<STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
|
||||
<STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
|
||||
<STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
|
||||
<STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
|
||||
<STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
|
||||
<STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
|
||||
<STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
|
||||
<STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
|
||||
<STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */
|
||||
<STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */
|
||||
<STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */
|
||||
<STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */
|
||||
<STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */
|
||||
<STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
|
||||
<STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
|
||||
<STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
|
||||
<STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
|
||||
<STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
|
||||
<STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */
|
||||
<STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -24,11 +24,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
<dc {
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&fmc {
|
||||
/* Memory configuration from sdram datasheet MT48LC_4M32_B2B5-6A */
|
||||
bank1: bank@0 {
|
||||
@@ -53,8 +48,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
<dc {
|
||||
bootph-all;
|
||||
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
|
||||
};
|
||||
|
||||
&panel_rgb {
|
||||
compatible = "simple-panel";
|
||||
compatible = "rocktech,rk043fn48h", "simple-panel";
|
||||
|
||||
display-timings {
|
||||
timing@0 {
|
||||
|
||||
@@ -1,169 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32f746.dtsi"
|
||||
#include "stm32f746-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32F746-DISCO board";
|
||||
compatible = "st,stm32f746-disco", "st,stm32f746";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xC0000000 0x800000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
no-map;
|
||||
size = <0x80000>;
|
||||
linux,dma-default;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
};
|
||||
|
||||
usbotg_hs_phy: usb-phy {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
/* This turns on vbus for otg fs for host mode (dwc2) */
|
||||
vcc5v_otg_fs: vcc5v-otg-fs-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpiod 5 0>;
|
||||
regulator-name = "vcc5_host1";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc_3v3: vcc-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "gpio-backlight";
|
||||
gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
panel_rgb: panel-rgb {
|
||||
compatible = "rocktech,rk043fn48h";
|
||||
power-supply = <&vcc_3v3>;
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
port {
|
||||
panel_in_rgb: endpoint {
|
||||
remote-endpoint = <<dc_out_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins_b>;
|
||||
pinctrl-names = "default";
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
pinctrl-0 = <&i2c3_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
touchscreen@38 {
|
||||
compatible = "edt,edt-ft5306";
|
||||
reg = <0x38>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
|
||||
touchscreen-size-x = <480>;
|
||||
touchscreen-size-y = <272>;
|
||||
};
|
||||
};
|
||||
|
||||
<dc {
|
||||
pinctrl-0 = <<dc_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
ltdc_out_rgb: endpoint {
|
||||
remote-endpoint = <&panel_in_rgb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdio1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default", "opendrain";
|
||||
pinctrl-0 = <&sdio_pins_a>;
|
||||
pinctrl-1 = <&sdio_pins_od_a>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&timers5 {
|
||||
/* Override timer5 to act as clockevent */
|
||||
compatible = "st,stm32-timer";
|
||||
interrupts = <50>;
|
||||
status = "okay";
|
||||
/delete-property/#address-cells;
|
||||
/delete-property/#size-cells;
|
||||
/delete-property/clock-names;
|
||||
/delete-node/pwm;
|
||||
/delete-node/timer@4;
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins_b>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_fs {
|
||||
dr_mode = "host";
|
||||
pinctrl-0 = <&usbotg_fs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
dr_mode = "host";
|
||||
phys = <&usbotg_hs_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
pinctrl-0 = <&usbotg_hs_pins_b>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,11 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32f7-pinctrl.dtsi"
|
||||
|
||||
&pinctrl{
|
||||
compatible = "st,stm32f746-pinctrl";
|
||||
};
|
||||
@@ -1,613 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "armv7-m.dtsi"
|
||||
#include <dt-bindings/clock/stm32fx-clock.h>
|
||||
#include <dt-bindings/mfd/stm32f7-rcc.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
clk_i2s_ckin: clk-i2s-ckin {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
timers2: timers@40000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@1 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers3: timers@40000400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@2 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers4: timers@40000800 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@3 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers5: timers@40000c00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000C00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@4 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers6: timers@40001000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
timer@5 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers7: timers@40001400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
timer@6 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <6>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers12: timers@40001800 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@11 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers13: timers@40001c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001C00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers14: timers@40002000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40002000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc@40002800 {
|
||||
compatible = "st,stm32-rtc";
|
||||
reg = <0x40002800 0x400>;
|
||||
clocks = <&rcc 1 CLK_RTC>;
|
||||
assigned-clocks = <&rcc 1 CLK_RTC>;
|
||||
assigned-clock-parents = <&rcc 1 CLK_LSE>;
|
||||
interrupt-parent = <&exti>;
|
||||
interrupts = <17 1>;
|
||||
st,syscfg = <&pwrcfg 0x00 0x100>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can3: can@40003400 {
|
||||
compatible = "st,stm32f4-bxcan";
|
||||
reg = <0x40003400 0x200>;
|
||||
interrupts = <104>, <105>, <106>, <107>;
|
||||
interrupt-names = "tx", "rx0", "rx1", "sce";
|
||||
resets = <&rcc STM32F7_APB1_RESET(CAN3)>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
|
||||
st,gcan = <&gcan3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gcan3: gcan@40003600 {
|
||||
compatible = "st,stm32f4-gcan", "syscon";
|
||||
reg = <0x40003600 0x200>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>;
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32f7-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
interrupts = <38>;
|
||||
clocks = <&rcc 1 CLK_USART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32f7-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
interrupts = <39>;
|
||||
clocks = <&rcc 1 CLK_USART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart4: serial@40004c00 {
|
||||
compatible = "st,stm32f7-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
interrupts = <52>;
|
||||
clocks = <&rcc 1 CLK_UART4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart5: serial@40005000 {
|
||||
compatible = "st,stm32f7-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
interrupts = <53>;
|
||||
clocks = <&rcc 1 CLK_UART5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@40005400 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x40005400 0x400>;
|
||||
interrupts = <31>,
|
||||
<32>;
|
||||
resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
|
||||
clocks = <&rcc 1 CLK_I2C1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x40005800 0x400>;
|
||||
interrupts = <33>,
|
||||
<34>;
|
||||
resets = <&rcc STM32F7_APB1_RESET(I2C2)>;
|
||||
clocks = <&rcc 1 CLK_I2C2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@40005c00 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x40005c00 0x400>;
|
||||
interrupts = <72>,
|
||||
<73>;
|
||||
resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
|
||||
clocks = <&rcc 1 CLK_I2C3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@40006000 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
reg = <0x40006000 0x400>;
|
||||
interrupts = <95>,
|
||||
<96>;
|
||||
resets = <&rcc STM32F7_APB1_RESET(I2C4)>;
|
||||
clocks = <&rcc 1 CLK_I2C4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32f4-bxcan";
|
||||
reg = <0x40006400 0x200>;
|
||||
interrupts = <19>, <20>, <21>, <22>;
|
||||
interrupt-names = "tx", "rx0", "rx1", "sce";
|
||||
resets = <&rcc STM32F7_APB1_RESET(CAN1)>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
|
||||
st,can-primary;
|
||||
st,gcan = <&gcan1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gcan1: gcan@40006600 {
|
||||
compatible = "st,stm32f4-gcan", "syscon";
|
||||
reg = <0x40006600 0x200>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>;
|
||||
};
|
||||
|
||||
can2: can@40006800 {
|
||||
compatible = "st,stm32f4-bxcan";
|
||||
reg = <0x40006800 0x200>;
|
||||
interrupts = <63>, <64>, <65>, <66>;
|
||||
interrupt-names = "tx", "rx0", "rx1", "sce";
|
||||
resets = <&rcc STM32F7_APB1_RESET(CAN2)>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>;
|
||||
st,can-secondary;
|
||||
st,gcan = <&gcan1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cec: cec@40006c00 {
|
||||
compatible = "st,stm32-cec";
|
||||
reg = <0x40006C00 0x400>;
|
||||
interrupts = <94>;
|
||||
clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
|
||||
clock-names = "cec", "hdmi-cec";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart7: serial@40007800 {
|
||||
compatible = "st,stm32f7-uart";
|
||||
reg = <0x40007800 0x400>;
|
||||
interrupts = <82>;
|
||||
clocks = <&rcc 1 CLK_UART7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart8: serial@40007c00 {
|
||||
compatible = "st,stm32f7-uart";
|
||||
reg = <0x40007c00 0x400>;
|
||||
interrupts = <83>;
|
||||
clocks = <&rcc 1 CLK_UART8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timers1: timers@40010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@0 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers8: timers@40010400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@7 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <7>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usart1: serial@40011000 {
|
||||
compatible = "st,stm32f7-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
interrupts = <37>;
|
||||
clocks = <&rcc 1 CLK_USART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart6: serial@40011400 {
|
||||
compatible = "st,stm32f7-uart";
|
||||
reg = <0x40011400 0x400>;
|
||||
interrupts = <71>;
|
||||
clocks = <&rcc 1 CLK_USART6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio2: mmc@40011c00 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00880180>;
|
||||
reg = <0x40011c00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
|
||||
clock-names = "apb_pclk";
|
||||
interrupts = <103>;
|
||||
max-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio1: mmc@40012c00 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00880180>;
|
||||
reg = <0x40012c00 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
|
||||
clock-names = "apb_pclk";
|
||||
interrupts = <49>;
|
||||
max-frequency = <48000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
syscfg: syscon@40013800 {
|
||||
compatible = "st,stm32-syscfg", "syscon";
|
||||
reg = <0x40013800 0x400>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@40013c00 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40013C00 0x400>;
|
||||
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
|
||||
};
|
||||
|
||||
timers9: timers@40014000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer@8 {
|
||||
compatible = "st,stm32-timer-trigger";
|
||||
reg = <8>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers10: timers@40014400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014400 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
timers11: timers@40014800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014800 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
|
||||
clock-names = "int";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ltdc: display-controller@40016800 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x40016800 0x200>;
|
||||
interrupts = <88>, <89>;
|
||||
resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
|
||||
clocks = <&rcc 1 CLK_LCD>;
|
||||
clock-names = "lcd";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwrcfg: power-config@40007000 {
|
||||
compatible = "st,stm32-power-config", "syscon";
|
||||
reg = <0x40007000 0x400>;
|
||||
};
|
||||
|
||||
crc: crc@40023000 {
|
||||
compatible = "st,stm32f7-crc";
|
||||
reg = <0x40023000 0x400>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcc: rcc@40023800 {
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <2>;
|
||||
compatible = "st,stm32f746-rcc", "st,stm32-rcc";
|
||||
reg = <0x40023800 0x400>;
|
||||
clocks = <&clk_hse>, <&clk_i2s_ckin>;
|
||||
st,syscfg = <&pwrcfg>;
|
||||
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
|
||||
assigned-clock-rates = <1000000>;
|
||||
};
|
||||
|
||||
dma1: dma-controller@40026000 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x40026000 0x400>;
|
||||
interrupts = <11>,
|
||||
<12>,
|
||||
<13>,
|
||||
<14>,
|
||||
<15>,
|
||||
<16>,
|
||||
<17>,
|
||||
<47>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
|
||||
#dma-cells = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma2: dma-controller@40026400 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x40026400 0x400>;
|
||||
interrupts = <56>,
|
||||
<57>,
|
||||
<58>,
|
||||
<59>,
|
||||
<60>,
|
||||
<68>,
|
||||
<69>,
|
||||
<70>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
|
||||
#dma-cells = <4>;
|
||||
st,mem2mem;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg_hs: usb@40040000 {
|
||||
compatible = "st,stm32f7-hsotg";
|
||||
reg = <0x40040000 0x40000>;
|
||||
interrupts = <77>;
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
|
||||
clock-names = "otg";
|
||||
g-rx-fifo-size = <256>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg_fs: usb@50000000 {
|
||||
compatible = "st,stm32f4x9-fsotg";
|
||||
reg = <0x50000000 0x40000>;
|
||||
interrupts = <67>;
|
||||
clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
|
||||
clock-names = "otg";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&systick {
|
||||
clocks = <&rcc 1 0>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -23,57 +23,13 @@
|
||||
spi0 = &qspi;
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "orisetech,otm8009a";
|
||||
reset-gpios = <&gpioj 15 1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
dsi: dsi@40016c00 {
|
||||
compatible = "st,stm32-dsi";
|
||||
reg = <0x40016c00 0x800>;
|
||||
resets = <&rcc STM32F7_APB2_RESET(DSI)>;
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
|
||||
<&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
|
||||
<&clk_hse>;
|
||||
clock-names = "pclk", "px_clk", "ref";
|
||||
bootph-all;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
dsi_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
<dc {
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
|
||||
bootph-all;
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
dp_out: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
&dsi {
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
|
||||
<&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
|
||||
<&clk_hse>;
|
||||
clock-names = "pclk", "px_clk", "ref";
|
||||
};
|
||||
|
||||
&fmc {
|
||||
@@ -100,6 +56,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
<dc {
|
||||
bootph-all;
|
||||
|
||||
clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
ethernet_mii: mii@0 {
|
||||
pins {
|
||||
|
||||
@@ -1,133 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2017 - Vikas MANOCHA <vikas.manocha@st.com>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32f746.dtsi"
|
||||
#include "stm32f769-pinctrl.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32F769-DISCO board";
|
||||
compatible = "st,stm32f769-disco", "st,stm32f769";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xC0000000 0x1000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led-green {
|
||||
gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
led-red {
|
||||
gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
button-0 {
|
||||
label = "User";
|
||||
linux,code = <KEY_HOME>;
|
||||
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_phy: usb-phy {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
|
||||
mmc_vcard: mmc_vcard {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "mmc_vcard";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&rcc {
|
||||
compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
|
||||
};
|
||||
|
||||
&cec {
|
||||
pinctrl-0 = <&cec_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins_b>;
|
||||
pinctrl-names = "default";
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
<dc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio2 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&mmc_vcard>;
|
||||
cd-gpios = <&gpioi 15 GPIO_ACTIVE_LOW>;
|
||||
broken-cd;
|
||||
pinctrl-names = "default", "opendrain";
|
||||
pinctrl-0 = <&sdio_pins_b>;
|
||||
pinctrl-1 = <&sdio_pins_od_b>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&timers5 {
|
||||
/* Override timer5 to act as clockevent */
|
||||
compatible = "st,stm32-timer";
|
||||
interrupts = <50>;
|
||||
status = "okay";
|
||||
/delete-property/#address-cells;
|
||||
/delete-property/#size-cells;
|
||||
/delete-property/clock-names;
|
||||
/delete-node/pwm;
|
||||
/delete-node/timer@4;
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
dr_mode = "otg";
|
||||
phys = <&usbotg_hs_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,11 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32f7-pinctrl.dtsi"
|
||||
|
||||
&pinctrl{
|
||||
compatible = "st,stm32f769-pinctrl";
|
||||
};
|
||||
@@ -1,274 +0,0 @@
|
||||
/*
|
||||
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
|
||||
&pinctrl {
|
||||
|
||||
i2c1_pins_a: i2c1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
|
||||
<STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet_rmii: rmii-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('G', 11, AF11)>,
|
||||
<STM32_PINMUX('G', 13, AF11)>,
|
||||
<STM32_PINMUX('G', 12, AF11)>,
|
||||
<STM32_PINMUX('C', 4, AF11)>,
|
||||
<STM32_PINMUX('C', 5, AF11)>,
|
||||
<STM32_PINMUX('A', 7, AF11)>,
|
||||
<STM32_PINMUX('C', 1, AF11)>,
|
||||
<STM32_PINMUX('A', 2, AF11)>,
|
||||
<STM32_PINMUX('A', 1, AF11)>;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
|
||||
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
||||
slew-rate = <3>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
||||
slew-rate = <3>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
pins2{
|
||||
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
||||
slew-rate = <3>;
|
||||
drive-open-drain;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
|
||||
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 6, AF8)>, /* SDMMC1_D0DIR */
|
||||
<STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
|
||||
<STM32_PINMUX('B', 9, AF7)>; /* SDMMC1_CDIR */
|
||||
slew-rate = <3>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins2{
|
||||
pinmux = <STM32_PINMUX('B', 8, AF7)>; /* SDMMC1_CKIN */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC1_D0DIR */
|
||||
<STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
|
||||
<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
|
||||
<STM32_PINMUX('B', 8, ANALOG)>; /* SDMMC1_CKIN */
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('D', 6, AF11)>, /* SDMMC1_CK */
|
||||
<STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
|
||||
slew-rate = <3>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
|
||||
<STM32_PINMUX('B', 15, AF9)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('B', 3, AF9)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('B', 4, AF9)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('D', 6, AF11)>; /* SDMMC1_CK */
|
||||
slew-rate = <3>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
pins2{
|
||||
pinmux = <STM32_PINMUX('D', 7, AF11)>; /* SDMMC1_CMD */
|
||||
slew-rate = <3>;
|
||||
drive-open-drain;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('D', 6, ANALOG)>, /* SDMMC1_CK */
|
||||
<STM32_PINMUX('D', 7, ANALOG)>; /* SDMMC1_CMD */
|
||||
};
|
||||
};
|
||||
|
||||
spi1_pins: spi1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 5, AF5)>,
|
||||
/* SPI1_CLK */
|
||||
<STM32_PINMUX('B', 5, AF5)>;
|
||||
/* SPI1_MOSI */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('G', 9, AF5)>;
|
||||
/* SPI1_MISO */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins: uart4-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 0, AF8)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('I', 9, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins: usart1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_pins: usart2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart3_pins: usart3-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
|
||||
<STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS_DE */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */
|
||||
<STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs_pins_a: usbotg-hs-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
|
||||
<STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
|
||||
<STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
|
||||
<STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
|
||||
<STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
|
||||
<STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
|
||||
<STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
|
||||
<STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
|
||||
<STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
|
||||
<STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
|
||||
<STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
|
||||
<STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -53,7 +53,6 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
|
||||
&fmc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
@@ -1,695 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include "armv7-m.dtsi"
|
||||
#include <dt-bindings/clock/stm32h7-clks.h>
|
||||
#include <dt-bindings/mfd/stm32h7-rcc.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_i2s: i2s_ckin {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
timer5: timer@40000c00 {
|
||||
compatible = "st,stm32-timer";
|
||||
reg = <0x40000c00 0x400>;
|
||||
interrupts = <50>;
|
||||
clocks = <&rcc TIM5_CK>;
|
||||
};
|
||||
|
||||
lptimer1: timer@40002400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x40002400 0x400>;
|
||||
clocks = <&rcc LPTIM1_CK>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trigger@0 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40003800 0x400>;
|
||||
interrupts = <36>;
|
||||
resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
|
||||
clocks = <&rcc SPI2_CK>;
|
||||
status = "disabled";
|
||||
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40003c00 0x400>;
|
||||
interrupts = <51>;
|
||||
resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
|
||||
clocks = <&rcc SPI3_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
interrupts = <38>;
|
||||
status = "disabled";
|
||||
clocks = <&rcc USART2_CK>;
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
interrupts = <39>;
|
||||
status = "disabled";
|
||||
clocks = <&rcc USART3_CK>;
|
||||
};
|
||||
|
||||
uart4: serial@40004c00 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
interrupts = <52>;
|
||||
status = "disabled";
|
||||
clocks = <&rcc UART4_CK>;
|
||||
};
|
||||
|
||||
i2c1: i2c@40005400 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
interrupts = <31>,
|
||||
<32>;
|
||||
resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
|
||||
clocks = <&rcc I2C1_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
interrupts = <33>,
|
||||
<34>;
|
||||
resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
|
||||
clocks = <&rcc I2C2_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@40005c00 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005C00 0x400>;
|
||||
interrupts = <72>,
|
||||
<73>;
|
||||
resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
|
||||
clocks = <&rcc I2C3_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dac: dac@40007400 {
|
||||
compatible = "st,stm32h7-dac-core";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc DAC12_CK>;
|
||||
clock-names = "pclk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
dac1: dac@1 {
|
||||
compatible = "st,stm32-dac";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dac2: dac@2 {
|
||||
compatible = "st,stm32-dac";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usart1: serial@40011000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
interrupts = <37>;
|
||||
status = "disabled";
|
||||
clocks = <&rcc USART1_CK>;
|
||||
};
|
||||
|
||||
spi1: spi@40013000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40013000 0x400>;
|
||||
interrupts = <35>;
|
||||
resets = <&rcc STM32H7_APB2_RESET(SPI1)>;
|
||||
clocks = <&rcc SPI1_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@40013400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40013400 0x400>;
|
||||
interrupts = <84>;
|
||||
resets = <&rcc STM32H7_APB2_RESET(SPI4)>;
|
||||
clocks = <&rcc SPI4_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi5: spi@40015000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x40015000 0x400>;
|
||||
interrupts = <85>;
|
||||
resets = <&rcc STM32H7_APB2_RESET(SPI5)>;
|
||||
clocks = <&rcc SPI5_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma1: dma-controller@40020000 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x40020000 0x400>;
|
||||
interrupts = <11>,
|
||||
<12>,
|
||||
<13>,
|
||||
<14>,
|
||||
<15>,
|
||||
<16>,
|
||||
<17>,
|
||||
<47>;
|
||||
clocks = <&rcc DMA1_CK>;
|
||||
#dma-cells = <4>;
|
||||
st,mem2mem;
|
||||
dma-requests = <8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma2: dma-controller@40020400 {
|
||||
compatible = "st,stm32-dma";
|
||||
reg = <0x40020400 0x400>;
|
||||
interrupts = <56>,
|
||||
<57>,
|
||||
<58>,
|
||||
<59>,
|
||||
<60>,
|
||||
<68>,
|
||||
<69>,
|
||||
<70>;
|
||||
clocks = <&rcc DMA2_CK>;
|
||||
#dma-cells = <4>;
|
||||
st,mem2mem;
|
||||
dma-requests = <8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmamux1: dma-router@40020800 {
|
||||
compatible = "st,stm32h7-dmamux";
|
||||
reg = <0x40020800 0x40>;
|
||||
#dma-cells = <3>;
|
||||
dma-channels = <16>;
|
||||
dma-requests = <128>;
|
||||
dma-masters = <&dma1 &dma2>;
|
||||
clocks = <&rcc DMA1_CK>;
|
||||
};
|
||||
|
||||
adc_12: adc@40022000 {
|
||||
compatible = "st,stm32h7-adc-core";
|
||||
reg = <0x40022000 0x400>;
|
||||
interrupts = <18>;
|
||||
clocks = <&rcc ADC12_CK>;
|
||||
clock-names = "bus";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
adc1: adc@0 {
|
||||
compatible = "st,stm32h7-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x0>;
|
||||
interrupt-parent = <&adc_12>;
|
||||
interrupts = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc2: adc@100 {
|
||||
compatible = "st,stm32h7-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x100>;
|
||||
interrupt-parent = <&adc_12>;
|
||||
interrupts = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs: usb@40040000 {
|
||||
compatible = "st,stm32f7-hsotg";
|
||||
reg = <0x40040000 0x40000>;
|
||||
interrupts = <77>;
|
||||
clocks = <&rcc USB1OTG_CK>;
|
||||
clock-names = "otg";
|
||||
g-rx-fifo-size = <256>;
|
||||
g-np-tx-fifo-size = <32>;
|
||||
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbotg_fs: usb@40080000 {
|
||||
compatible = "st,stm32f4x9-fsotg";
|
||||
reg = <0x40080000 0x40000>;
|
||||
interrupts = <101>;
|
||||
clocks = <&rcc USB2OTG_CK>;
|
||||
clock-names = "otg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ltdc: display-controller@50001000 {
|
||||
compatible = "st,stm32-ltdc";
|
||||
reg = <0x50001000 0x200>;
|
||||
interrupts = <88>, <89>;
|
||||
resets = <&rcc STM32H7_APB3_RESET(LTDC)>;
|
||||
clocks = <&rcc LTDC_CK>;
|
||||
clock-names = "lcd";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdma1: dma-controller@52000000 {
|
||||
compatible = "st,stm32h7-mdma";
|
||||
reg = <0x52000000 0x1000>;
|
||||
interrupts = <122>;
|
||||
clocks = <&rcc MDMA_CK>;
|
||||
#dma-cells = <5>;
|
||||
dma-channels = <16>;
|
||||
dma-requests = <32>;
|
||||
};
|
||||
|
||||
sdmmc1: mmc@52007000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x10153180>;
|
||||
reg = <0x52007000 0x1000>;
|
||||
interrupts = <49>;
|
||||
clocks = <&rcc SDMMC1_CK>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
};
|
||||
|
||||
sdmmc2: mmc@48022400 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x10153180>;
|
||||
reg = <0x48022400 0x400>;
|
||||
interrupts = <124>;
|
||||
clocks = <&rcc SDMMC2_CK>;
|
||||
clock-names = "apb_pclk";
|
||||
resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <120000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
exti: interrupt-controller@58000000 {
|
||||
compatible = "st,stm32h7-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x58000000 0x400>;
|
||||
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
|
||||
};
|
||||
|
||||
syscfg: syscon@58000400 {
|
||||
compatible = "st,stm32-syscfg", "syscon";
|
||||
reg = <0x58000400 0x400>;
|
||||
};
|
||||
|
||||
spi6: spi@58001400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32h7-spi";
|
||||
reg = <0x58001400 0x400>;
|
||||
interrupts = <86>;
|
||||
resets = <&rcc STM32H7_APB4_RESET(SPI6)>;
|
||||
clocks = <&rcc SPI6_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@58001c00 {
|
||||
compatible = "st,stm32f7-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x58001C00 0x400>;
|
||||
interrupts = <95>,
|
||||
<96>;
|
||||
resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
|
||||
clocks = <&rcc I2C4_CK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lptimer2: timer@58002400 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x58002400 0x400>;
|
||||
clocks = <&rcc LPTIM2_CK>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trigger@1 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer3: timer@58002800 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x58002800 0x400>;
|
||||
clocks = <&rcc LPTIM3_CK>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trigger@2 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer4: timer@58002c00 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x58002c00 0x400>;
|
||||
clocks = <&rcc LPTIM4_CK>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer5: timer@58003000 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x58003000 0x400>;
|
||||
clocks = <&rcc LPTIM5_CK>;
|
||||
clock-names = "mux";
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
vrefbuf: regulator@58003c00 {
|
||||
compatible = "st,stm32-vrefbuf";
|
||||
reg = <0x58003C00 0x8>;
|
||||
clocks = <&rcc VREF_CK>;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@58004000 {
|
||||
compatible = "st,stm32h7-rtc";
|
||||
reg = <0x58004000 0x400>;
|
||||
clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
|
||||
clock-names = "pclk", "rtc_ck";
|
||||
assigned-clocks = <&rcc RTC_CK>;
|
||||
assigned-clock-parents = <&rcc LSE_CK>;
|
||||
interrupt-parent = <&exti>;
|
||||
interrupts = <17 IRQ_TYPE_EDGE_RISING>;
|
||||
st,syscfg = <&pwrcfg 0x00 0x100>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcc: reset-clock-controller@58024400 {
|
||||
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
|
||||
reg = <0x58024400 0x400>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
|
||||
st,syscfg = <&pwrcfg>;
|
||||
};
|
||||
|
||||
pwrcfg: power-config@58024800 {
|
||||
compatible = "st,stm32-power-config", "syscon";
|
||||
reg = <0x58024800 0x400>;
|
||||
};
|
||||
|
||||
adc_3: adc@58026000 {
|
||||
compatible = "st,stm32h7-adc-core";
|
||||
reg = <0x58026000 0x400>;
|
||||
interrupts = <127>;
|
||||
clocks = <&rcc ADC3_CK>;
|
||||
clock-names = "bus";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
adc3: adc@0 {
|
||||
compatible = "st,stm32h7-adc";
|
||||
#io-channel-cells = <1>;
|
||||
reg = <0x0>;
|
||||
interrupt-parent = <&adc_3>;
|
||||
interrupts = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
mac: ethernet@40028000 {
|
||||
compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
|
||||
reg = <0x40028000 0x8000>;
|
||||
reg-names = "stmmaceth";
|
||||
interrupts = <61>;
|
||||
interrupt-names = "macirq";
|
||||
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
|
||||
clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>;
|
||||
st,syscon = <&syscfg 0x4>;
|
||||
snps,pbl = <8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@58020000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32h743-pinctrl";
|
||||
ranges = <0 0x58020000 0x3000>;
|
||||
interrupt-parent = <&exti>;
|
||||
st,syscfg = <&syscfg 0x8>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@58020000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&rcc GPIOA_CK>;
|
||||
st,bank-name = "GPIOA";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@58020400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x400 0x400>;
|
||||
clocks = <&rcc GPIOB_CK>;
|
||||
st,bank-name = "GPIOB";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@58020800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x800 0x400>;
|
||||
clocks = <&rcc GPIOC_CK>;
|
||||
st,bank-name = "GPIOC";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@58020c00 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0xc00 0x400>;
|
||||
clocks = <&rcc GPIOD_CK>;
|
||||
st,bank-name = "GPIOD";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@58021000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x1000 0x400>;
|
||||
clocks = <&rcc GPIOE_CK>;
|
||||
st,bank-name = "GPIOE";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@58021400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x1400 0x400>;
|
||||
clocks = <&rcc GPIOF_CK>;
|
||||
st,bank-name = "GPIOF";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@58021800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x1800 0x400>;
|
||||
clocks = <&rcc GPIOG_CK>;
|
||||
st,bank-name = "GPIOG";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@58021c00 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x1c00 0x400>;
|
||||
clocks = <&rcc GPIOH_CK>;
|
||||
st,bank-name = "GPIOH";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@58022000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x2000 0x400>;
|
||||
clocks = <&rcc GPIOI_CK>;
|
||||
st,bank-name = "GPIOI";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@58022400 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x2400 0x400>;
|
||||
clocks = <&rcc GPIOJ_CK>;
|
||||
st,bank-name = "GPIOJ";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@58022800 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x2800 0x400>;
|
||||
clocks = <&rcc GPIOK_CK>;
|
||||
st,bank-name = "GPIOK";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&systick {
|
||||
clock-frequency = <250000000>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,75 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2017 - Patrice Chotard <patrice.chotard@foss.st.com>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32h743.dtsi"
|
||||
#include "stm32h7-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32H743i-Discovery board";
|
||||
compatible = "st,stm32h743i-disco", "st,stm32h743";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@d0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xd0000000 0x2000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &usart2;
|
||||
};
|
||||
|
||||
v3v3: regulator-v3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "disabled";
|
||||
pinctrl-0 = <ðernet_rmii>;
|
||||
pinctrl-names = "default";
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
pinctrl-0 = <&usart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,160 +0,0 @@
|
||||
/*
|
||||
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32h743.dtsi"
|
||||
#include "stm32h7-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32H743i-EVAL board";
|
||||
compatible = "st,stm32h743i-eval", "st,stm32h743";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@d0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xd0000000 0x2000000>;
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &usart1;
|
||||
};
|
||||
|
||||
vdda: regulator-vdda {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
v2v9_sd: regulator-v2v9_sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v2v9_sd";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
usbotg_hs_phy: usb-phy {
|
||||
#phy-cells = <0>;
|
||||
compatible = "usb-nop-xceiv";
|
||||
clocks = <&rcc USB1ULPI_CK>;
|
||||
clock-names = "main_clk";
|
||||
};
|
||||
};
|
||||
|
||||
&adc_12 {
|
||||
vdda-supply = <&vdda>;
|
||||
vref-supply = <&vdda>;
|
||||
status = "okay";
|
||||
adc1: adc@0 {
|
||||
/* potentiometer */
|
||||
st,adc-channels = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "disabled";
|
||||
pinctrl-0 = <ðernet_rmii>;
|
||||
pinctrl-names = "default";
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,sig-dir;
|
||||
st,neg-edge;
|
||||
st,use-ckin;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v2v9_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-0 = <&usart1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
phys = <&usbotg_hs_phy>;
|
||||
phy-names = "usb2-phy";
|
||||
dr_mode = "otg";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,5 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/* Copyright (C) STMicroelectronics 2021 - All Rights Reserved */
|
||||
|
||||
#include "stm32h743.dtsi"
|
||||
|
||||
@@ -1,188 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* Copyright 2021 - Dillon Min <dillon.minfei@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32h750.dtsi"
|
||||
#include "stm32h7-pinctrl.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "RT-Thread STM32H750i-ART-PI board";
|
||||
compatible = "st,stm32h750i-art-pi", "st,stm32h750";
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram";
|
||||
stdout-path = "serial0:2000000n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x2000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
no-map;
|
||||
size = <0x100000>;
|
||||
linux,dma-default;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
serial1 = &usart3;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led-red {
|
||||
gpios = <&gpioi 8 0>;
|
||||
};
|
||||
led-green {
|
||||
gpios = <&gpioc 15 0>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
|
||||
v3v3: regulator-v3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
wlan_pwr: regulator-wlan {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "wl-reg";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&clk_hse {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&dma1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dma2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "disabled";
|
||||
pinctrl-0 = <ðernet_rmii>;
|
||||
pinctrl-names = "default";
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc2_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
non-removable;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&wlan_pwr>;
|
||||
status = "okay";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
brcmf: bcrmf@1 {
|
||||
reg = <1>;
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
|
||||
dmas = <&dmamux1 37 0x400 0x05>,
|
||||
<&dmamux1 38 0x400 0x05>;
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "winbond,w25q128", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <80000000>;
|
||||
|
||||
partition@0 {
|
||||
label = "root filesystem";
|
||||
reg = <0 0x1000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
pinctrl-0 = <&usart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usart3_pins>;
|
||||
dmas = <&dmamux1 45 0x400 0x05>,
|
||||
<&dmamux1 46 0x400 0x05>;
|
||||
dma-names = "rx", "tx";
|
||||
st,hw-flow-ctrl;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
host-wakeup-gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
|
||||
device-wakeup-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>;
|
||||
shutdown-gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
|
||||
max-speed = <115200>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-0 = <&uart4_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,888 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com>
|
||||
*/
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
|
||||
&pinctrl {
|
||||
adc1_pins_a: adc1-pins-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
|
||||
};
|
||||
};
|
||||
|
||||
adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */
|
||||
<STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */
|
||||
};
|
||||
};
|
||||
|
||||
adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */
|
||||
<STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */
|
||||
};
|
||||
};
|
||||
|
||||
eth1_rgmii_pins_a: eth1-rgmii-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
|
||||
<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
|
||||
<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
|
||||
<STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */
|
||||
<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
|
||||
<STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */
|
||||
<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
|
||||
<STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
|
||||
<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
|
||||
<STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
|
||||
<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
|
||||
<STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */
|
||||
<STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
|
||||
<STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
|
||||
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
|
||||
<STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */
|
||||
<STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
|
||||
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */
|
||||
<STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
|
||||
<STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */
|
||||
<STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
|
||||
<STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
|
||||
<STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */
|
||||
<STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */
|
||||
<STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */
|
||||
<STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */
|
||||
};
|
||||
};
|
||||
|
||||
eth2_rgmii_pins_a: eth2-rgmii-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */
|
||||
<STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */
|
||||
<STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */
|
||||
<STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */
|
||||
<STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */
|
||||
<STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */
|
||||
<STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */
|
||||
<STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <2>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */
|
||||
<STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */
|
||||
<STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */
|
||||
<STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */
|
||||
<STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */
|
||||
<STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
|
||||
<STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */
|
||||
<STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD2 */
|
||||
<STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
|
||||
<STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RGMII_TX_CTL */
|
||||
<STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_GTX_CLK */
|
||||
<STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */
|
||||
<STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */
|
||||
<STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
|
||||
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
|
||||
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD2 */
|
||||
<STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD3 */
|
||||
<STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */
|
||||
<STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
|
||||
<STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1_sleep_pins_a: i2c1-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
|
||||
<STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */
|
||||
};
|
||||
};
|
||||
|
||||
i2c5_pins_a: i2c5-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
|
||||
<STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c5_sleep_pins_a: i2c5-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
|
||||
<STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */
|
||||
};
|
||||
};
|
||||
|
||||
i2c5_pins_b: i2c5-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */
|
||||
<STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */
|
||||
bias-disable;
|
||||
drive-open-drain;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c5_sleep_pins_b: i2c5-sleep-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */
|
||||
<STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */
|
||||
};
|
||||
};
|
||||
|
||||
m_can1_pins_a: m-can1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
m_can1_sleep_pins_a: m_can1-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */
|
||||
<STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */
|
||||
};
|
||||
};
|
||||
|
||||
m_can2_pins_a: m-can2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
m_can2_sleep_pins_a: m_can2-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */
|
||||
<STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */
|
||||
};
|
||||
};
|
||||
|
||||
mcp23017_pins_a: mcp23017-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('G', 12, GPIO)>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1_ch3n_pins_a: pwm1-ch3n-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 12, AF1)>; /* TIM1_CH3N */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1_ch3n_sleep_pins_a: pwm1-ch3n-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 12, ANALOG)>; /* TIM1_CH3N */
|
||||
};
|
||||
};
|
||||
|
||||
pwm3_pins_a: pwm3-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3_sleep_pins_a: pwm3-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */
|
||||
};
|
||||
};
|
||||
|
||||
pwm4_pins_a: pwm4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm4_sleep_pins_a: pwm4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */
|
||||
};
|
||||
};
|
||||
|
||||
pwm5_pins_a: pwm5-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm5_sleep_pins_a: pwm5-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */
|
||||
};
|
||||
};
|
||||
|
||||
pwm8_pins_a: pwm8-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm8_sleep_pins_a: pwm8-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */
|
||||
};
|
||||
};
|
||||
|
||||
pwm13_pins_a: pwm13-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm13_sleep_pins_a: pwm13-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */
|
||||
};
|
||||
};
|
||||
|
||||
pwm14_pins_a: pwm14-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */
|
||||
bias-pull-down;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm14_sleep_pins_a: pwm14-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */
|
||||
};
|
||||
};
|
||||
|
||||
qspi_clk_pins_a: qspi-clk-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
|
||||
};
|
||||
};
|
||||
|
||||
qspi_bk1_pins_a: qspi-bk1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
|
||||
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
|
||||
<STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */
|
||||
<STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
|
||||
<STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
|
||||
<STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */
|
||||
<STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */
|
||||
};
|
||||
};
|
||||
|
||||
qspi_cs1_pins_a: qspi-cs1-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */
|
||||
bias-pull-up;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */
|
||||
};
|
||||
};
|
||||
|
||||
sai1a_pins_a: sai1a-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */
|
||||
<STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */
|
||||
<STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */
|
||||
slew-rate = <0>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sai1a_sleep_pins_a: sai1a-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */
|
||||
<STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */
|
||||
<STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */
|
||||
};
|
||||
};
|
||||
|
||||
sai1b_pins_a: sai1b-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sai1b_sleep_pins_a: sai1b-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-open-drain;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
|
||||
<STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
|
||||
<STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
|
||||
<STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
|
||||
<STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
|
||||
<STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
|
||||
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
|
||||
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
|
||||
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */
|
||||
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
|
||||
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */
|
||||
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */
|
||||
<STM32_PINMUX('B', 4, AF10)>; /* SDMMC2_D3 */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
|
||||
slew-rate = <1>;
|
||||
drive-open-drain;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */
|
||||
<STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */
|
||||
<STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */
|
||||
<STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */
|
||||
<STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */
|
||||
<STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_d47_pins_a: sdmmc2-d47-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */
|
||||
<STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */
|
||||
<STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
|
||||
<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
|
||||
slew-rate = <1>;
|
||||
drive-push-pull;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */
|
||||
<STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */
|
||||
<STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */
|
||||
<STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */
|
||||
};
|
||||
};
|
||||
|
||||
spi2_pins_a: spi2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */
|
||||
<STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi2_sleep_pins_a: spi2-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */
|
||||
<STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */
|
||||
<STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */
|
||||
};
|
||||
};
|
||||
|
||||
spi3_pins_a: spi3-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */
|
||||
<STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi3_sleep_pins_a: spi3-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */
|
||||
<STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */
|
||||
<STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */
|
||||
};
|
||||
};
|
||||
|
||||
spi5_pins_a: spi5-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */
|
||||
<STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <1>;
|
||||
};
|
||||
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
spi5_sleep_pins_a: spi5-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */
|
||||
<STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */
|
||||
<STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */
|
||||
};
|
||||
};
|
||||
|
||||
stm32g0_intn_pins_a: stm32g0-intn-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('I', 2, GPIO)>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_a: uart4-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_idle_pins_a: uart4-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_sleep_pins_a: uart4-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */
|
||||
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
|
||||
};
|
||||
};
|
||||
|
||||
uart4_pins_b: uart4-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_idle_pins_b: uart4-idle-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart4_sleep_pins_b: uart4-sleep-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */
|
||||
<STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */
|
||||
};
|
||||
};
|
||||
|
||||
uart7_pins_a: uart7-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */
|
||||
<STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */
|
||||
<STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart7_idle_pins_a: uart7-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
|
||||
<STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins3 {
|
||||
pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
uart7_sleep_pins_a: uart7-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */
|
||||
<STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */
|
||||
<STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */
|
||||
<STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */
|
||||
};
|
||||
};
|
||||
|
||||
uart8_pins_a: uart8-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart8_idle_pins_a: uart8-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
uart8_sleep_pins_a: uart8-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */
|
||||
<STM32_PINMUX('F', 9, ANALOG)>; /* UART8_RX */
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_a: usart1-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
|
||||
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */
|
||||
<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_idle_pins_a: usart1-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
|
||||
<STM32_PINMUX('A', 7, ANALOG)>; /* USART1_CTS_NSS */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins3 {
|
||||
pinmux = <STM32_PINMUX('B', 0, AF4)>; /* USART1_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_sleep_pins_a: usart1-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
|
||||
<STM32_PINMUX('C', 2, ANALOG)>, /* USART1_RTS */
|
||||
<STM32_PINMUX('A', 7, ANALOG)>, /* USART1_CTS_NSS */
|
||||
<STM32_PINMUX('B', 0, ANALOG)>; /* USART1_RX */
|
||||
};
|
||||
};
|
||||
|
||||
usart1_pins_b: usart1-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_idle_pins_b: usart1-idle-1 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
usart1_sleep_pins_b: usart1-sleep-1 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */
|
||||
<STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */
|
||||
};
|
||||
};
|
||||
|
||||
usart2_pins_a: usart2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */
|
||||
<STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
|
||||
<STM32_PINMUX('E', 11, AF2)>; /* USART2_CTS_NSS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_idle_pins_a: usart2-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
|
||||
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 4, AF3)>; /* USART2_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins3 {
|
||||
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_sleep_pins_a: usart2-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */
|
||||
<STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */
|
||||
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
|
||||
<STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */
|
||||
};
|
||||
};
|
||||
|
||||
usart2_pins_b: usart2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */
|
||||
<STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */
|
||||
<STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_idle_pins_b: usart2-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
|
||||
<STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins3 {
|
||||
pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_sleep_pins_b: usart2-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */
|
||||
<STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */
|
||||
<STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */
|
||||
<STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -48,6 +48,10 @@
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&etzpc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpioa {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,98 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp131.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
m_can1: can@4400e000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
m_can2: can@4400f000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc_1: adc@48003000 {
|
||||
compatible = "st,stm32mp13-adc-core";
|
||||
reg = <0x48003000 0x400>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc ADC1>, <&rcc ADC1_K>;
|
||||
clock-names = "bus", "adc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
adc1: adc@0 {
|
||||
compatible = "st,stm32mp13-adc";
|
||||
#io-channel-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>;
|
||||
interrupt-parent = <&adc_1>;
|
||||
interrupts = <0>;
|
||||
dmas = <&dmamux1 9 0x400 0x80000001>;
|
||||
dma-names = "rx";
|
||||
status = "disabled";
|
||||
|
||||
channel@18 {
|
||||
reg = <18>;
|
||||
label = "vrefint";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
eth2: eth2@5800e000 {
|
||||
compatible = "snps,dwmac-4.20a", "st,stm32mp13-dwmac";
|
||||
reg = <0x5800e000 0x2000>;
|
||||
reg-names = "stmmaceth";
|
||||
interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clock-names = "stmmaceth",
|
||||
"mac-clk-tx",
|
||||
"mac-clk-rx",
|
||||
"ethstp",
|
||||
"eth-ck";
|
||||
clocks = <&rcc ETH2MAC>,
|
||||
<&rcc ETH2TX>,
|
||||
<&rcc ETH2RX>,
|
||||
<&rcc ETH2STP>,
|
||||
<&rcc ETH2CK_K>;
|
||||
st,syscon = <&syscfg 0x4 0xff000000>;
|
||||
snps,mixed-burst;
|
||||
snps,pbl = <2>;
|
||||
snps,axi-config = <&stmmac_axi_config_2>;
|
||||
snps,tso;
|
||||
status = "disabled";
|
||||
|
||||
stmmac_axi_config_2: stmmac-axi-config {
|
||||
snps,wr_osr_lmt = <0x7>;
|
||||
snps,rd_osr_lmt = <0x7>;
|
||||
snps,blen = <0 0 0 0 16 8 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,12 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp133.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
};
|
||||
};
|
||||
@@ -1,376 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/regulator/st,stm32mp13-regulator.h>
|
||||
#include "stm32mp135.dtsi"
|
||||
#include "stm32mp13xf.dtsi"
|
||||
#include "stm32mp13-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP135F-DK Discovery Board";
|
||||
compatible = "st,stm32mp135f-dk", "st,stm32mp135";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
serial1 = &usart1;
|
||||
serial2 = &uart8;
|
||||
serial3 = &usart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
optee@dd000000 {
|
||||
reg = <0xdd000000 0x3000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
button-user {
|
||||
label = "User-PA13";
|
||||
linux,code = <BTN_1>;
|
||||
gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-blue {
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&adc_1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&adc1_usb_cc_pins_a>;
|
||||
vdda-supply = <&scmi_vdd_adc>;
|
||||
vref-supply = <&scmi_vdd_adc>;
|
||||
status = "okay";
|
||||
adc1: adc@0 {
|
||||
status = "okay";
|
||||
/*
|
||||
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12.
|
||||
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
|
||||
* 5 * (5.1 + 47kOhms) * 5pF => 1.3us.
|
||||
* Use arbitrary margin here (e.g. 5us).
|
||||
*/
|
||||
channel@6 {
|
||||
reg = <6>;
|
||||
st,min-sample-time-ns = <5000>;
|
||||
};
|
||||
channel@12 {
|
||||
reg = <12>;
|
||||
st,min-sample-time-ns = <5000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
pinctrl-1 = <&i2c1_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <96>;
|
||||
i2c-scl-falling-time-ns = <3>;
|
||||
clock-frequency = <1000000>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
mcp23017: pinctrl@21 {
|
||||
compatible = "microchip,mcp23017";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-parent = <&gpiog>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcp23017_pins_a>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
microchip,irq-mirror;
|
||||
};
|
||||
|
||||
typec@53 {
|
||||
compatible = "st,stm32g0-typec";
|
||||
reg = <0x53>;
|
||||
/* Alert pin on PI2 */
|
||||
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
/* Internal pull-up on PI2 */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&stm32g0_intn_pins_a>;
|
||||
firmware-name = "stm32g0-ucsi.mp135f-dk.fw";
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
|
||||
port {
|
||||
con_usb_c_g0_ep: endpoint {
|
||||
remote-endpoint = <&usbotg_hs_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c5_pins_a>;
|
||||
pinctrl-1 = <&i2c5_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <170>;
|
||||
i2c-scl-falling-time-ns = <5>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&scmi_regu {
|
||||
scmi_vdd_adc: regulator@10 {
|
||||
reg = <VOLTD_SCMI_STPMIC1_LDO1>;
|
||||
regulator-name = "vdd_adc";
|
||||
};
|
||||
scmi_vdd_usb: regulator@13 {
|
||||
reg = <VOLTD_SCMI_STPMIC1_LDO4>;
|
||||
regulator-name = "vdd_usb";
|
||||
};
|
||||
scmi_vdd_sd: regulator@14 {
|
||||
reg = <VOLTD_SCMI_STPMIC1_LDO5>;
|
||||
regulator-name = "vdd_sd";
|
||||
};
|
||||
scmi_v1v8_periph: regulator@15 {
|
||||
reg = <VOLTD_SCMI_STPMIC1_LDO6>;
|
||||
regulator-name = "v1v8_periph";
|
||||
};
|
||||
scmi_v3v3_sw: regulator@19 {
|
||||
reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
|
||||
regulator-name = "v3v3_sw";
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
cd-gpios = <&gpioh 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
disable-wp;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&scmi_vdd_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi5 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&spi5_pins_a>;
|
||||
pinctrl-1 = <&spi5_sleep_pins_a>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timers1 {
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
pwm1: pwm {
|
||||
pinctrl-0 = <&pwm1_ch3n_pins_a>;
|
||||
pinctrl-1 = <&pwm1_ch3n_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers3 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm3_pins_a>;
|
||||
pinctrl-1 = <&pwm3_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@2 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers4 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm4_pins_a>;
|
||||
pinctrl-1 = <&pwm4_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@3 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers8 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm8_pins_a>;
|
||||
pinctrl-1 = <&pwm8_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@7 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers14 {
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm14_pins_a>;
|
||||
pinctrl-1 = <&pwm14_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@13 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
pinctrl-1 = <&uart4_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart4_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart8_pins_a>;
|
||||
pinctrl-1 = <&uart8_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart8_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usart1 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&usart1_pins_a>;
|
||||
pinctrl-1 = <&usart1_sleep_pins_a>;
|
||||
pinctrl-2 = <&usart1_idle_pins_a>;
|
||||
uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Bluetooth */
|
||||
&usart2 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&usart2_pins_a>;
|
||||
pinctrl-1 = <&usart2_sleep_pins_a>;
|
||||
pinctrl-2 = <&usart2_idle_pins_a>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh_ehci {
|
||||
phys = <&usbphyc_port0>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* onboard HUB */
|
||||
hub@1 {
|
||||
compatible = "usb424,2514";
|
||||
reg = <1>;
|
||||
vdd-supply = <&scmi_v3v3_sw>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
usb-role-switch;
|
||||
status = "okay";
|
||||
port {
|
||||
usbotg_hs_ep: endpoint {
|
||||
remote-endpoint = <&con_usb_c_g0_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&scmi_vdd_usb>;
|
||||
st,current-boost-microamp = <1000>;
|
||||
st,decrease-hs-slew-rate;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <11>;
|
||||
st,trim-hs-impedance = <2>;
|
||||
st,tune-squelch-level = <1>;
|
||||
st,enable-hs-rx-gain-eq;
|
||||
st,no-hs-ftime-ctrl;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <&scmi_vdd_usb>;
|
||||
st,current-boost-microamp = <1000>;
|
||||
st,decrease-hs-slew-rate;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <11>;
|
||||
st,trim-hs-impedance = <2>;
|
||||
st,tune-squelch-level = <1>;
|
||||
st,enable-hs-rx-gain-eq;
|
||||
st,no-hs-ftime-ctrl;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
@@ -1,18 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp: crypto@54002000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,18 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2021 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp: crypto@54002000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54002000 0x400>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,88 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
firmware {
|
||||
optee: optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
scmi: scmi {
|
||||
compatible = "linaro,scmi-optee";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
linaro,optee-channel-id = <0>;
|
||||
|
||||
scmi_clk: protocol@14 {
|
||||
reg = <0x14>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_reset: protocol@16 {
|
||||
reg = <0x16>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_voltd: protocol@17 {
|
||||
reg = <0x17>;
|
||||
|
||||
scmi_reguls: regulators {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
scmi_reg11: regulator@0 {
|
||||
reg = <0>;
|
||||
regulator-name = "reg11";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
};
|
||||
|
||||
scmi_reg18: regulator@1 {
|
||||
reg = <1>;
|
||||
regulator-name = "reg18";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
scmi_usb33: regulator@2 {
|
||||
reg = <2>;
|
||||
regulator-name = "usb33";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
®11 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
®18 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb33 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
usb33d-supply = <&scmi_usb33>;
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
vdda1v1-supply = <&scmi_reg11>;
|
||||
vdda1v8-supply = <&scmi_reg18>;
|
||||
};
|
||||
|
||||
/delete-node/ &clk_hse;
|
||||
/delete-node/ &clk_hsi;
|
||||
/delete-node/ &clk_lse;
|
||||
/delete-node/ &clk_lsi;
|
||||
/delete-node/ &clk_csi;
|
||||
@@ -106,6 +106,10 @@
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
|
||||
&etzpc {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
&gpioa {
|
||||
bootph-all;
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,59 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp151.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a7";
|
||||
clock-frequency = <650000000>;
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
|
||||
timer {
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
m_can1: can@4400e000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
m_can2: can@4400f000 {
|
||||
compatible = "bosch,m_can";
|
||||
reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
|
||||
reg-names = "m_can", "message_ram";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "int0", "int1";
|
||||
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
|
||||
clock-names = "hclk", "cclk";
|
||||
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,48 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include "stm32mp153.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
gpu: gpu@59000000 {
|
||||
compatible = "vivante,gc";
|
||||
reg = <0x59000000 0x800>;
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc GPU>, <&rcc GPU_K>;
|
||||
clock-names = "bus" ,"core";
|
||||
resets = <&rcc GPU_R>;
|
||||
};
|
||||
|
||||
dsi: dsi@5a000000 {
|
||||
compatible = "st,stm32-dsi";
|
||||
reg = <0x5a000000 0x800>;
|
||||
clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
|
||||
clock-names = "pclk", "ref", "px_clk";
|
||||
phy-dsi-supply = <®18>;
|
||||
resets = <&rcc DSI_R>;
|
||||
reset-names = "apb";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,82 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157a-dk1.dts"
|
||||
#include "stm32mp15-scmi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
|
||||
compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
|
||||
|
||||
reserved-memory {
|
||||
optee@de000000 {
|
||||
reg = <0xde000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&dsi {
|
||||
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
|
||||
};
|
||||
|
||||
&gpioz {
|
||||
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&mdma1 {
|
||||
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||
};
|
||||
|
||||
&m4_rproc {
|
||||
/delete-property/ st,syscfg-holdboot;
|
||||
resets = <&scmi_reset RST_SCMI_MCU>,
|
||||
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
|
||||
reset-names = "mcu_rst", "hold_boot";
|
||||
};
|
||||
|
||||
&rcc {
|
||||
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||
<&scmi_clk CK_SCMI_HSI>,
|
||||
<&scmi_clk CK_SCMI_CSI>,
|
||||
<&scmi_clk CK_SCMI_LSE>,
|
||||
<&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||
};
|
||||
@@ -1,25 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxac-pinctrl.dtsi"
|
||||
#include "stm32mp15xx-dkx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
|
||||
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
@@ -1,49 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutons(India)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp157a-icore-stm32mp1.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxaa-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Engicam i.Core STM32MP1 C.TOUCH 2.0";
|
||||
compatible = "engicam,icore-stm32mp1-ctouch2",
|
||||
"engicam,icore-stm32mp1", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
st,neg-edge;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
pinctrl-1 = <&uart4_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart4_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,161 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutons(India)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp157a-microgea-stm32mp1.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxaa-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 7\" Open Frame";
|
||||
compatible = "engicam,microgea-stm32mp1-microdev2.0-of7",
|
||||
"engicam,microgea-stm32mp1", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
serial1 = &uart8;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "gpio-backlight";
|
||||
gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
|
||||
default-on;
|
||||
};
|
||||
|
||||
lcd_3v3: regulator-lcd-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lcd_3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpiof 10 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
power-supply = <&panel_pwr>;
|
||||
};
|
||||
|
||||
panel_pwr: regulator-panel-pwr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "panel_pwr";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpiob 10 GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "auo,b101aw03";
|
||||
backlight = <&backlight>;
|
||||
enable-gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <&lcd_3v3>;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <<dc_ep0_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c2_pins_a>;
|
||||
pinctrl-1 = <&i2c2_sleep_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
<dc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <<dc_pins>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ltdc_ep0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
ltdc_pins: ltdc-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */
|
||||
<STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */
|
||||
<STM32_PINMUX('H', 11, AF14)>, /* LTDC_R5 */
|
||||
<STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */
|
||||
<STM32_PINMUX('D', 9, AF14)>, /* LTDC_B0 */
|
||||
<STM32_PINMUX('E', 5, AF14)>, /* LTDC_G0 */
|
||||
<STM32_PINMUX('E', 6, AF14)>, /* LTDC_G1 */
|
||||
<STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */
|
||||
<STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */
|
||||
<STM32_PINMUX('G', 7, AF14)>, /* LTDC_CLK */
|
||||
<STM32_PINMUX('G', 12, AF14)>, /* LTDC_B1 */
|
||||
<STM32_PINMUX('H', 2, AF14)>, /* LTDC_R0 */
|
||||
<STM32_PINMUX('H', 3, AF14)>, /* LTDC_R1 */
|
||||
<STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */
|
||||
<STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */
|
||||
<STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */
|
||||
<STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */
|
||||
<STM32_PINMUX('H', 14, AF14)>, /* LTDC_G3 */
|
||||
<STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */
|
||||
<STM32_PINMUX('I', 0, AF14)>, /* LTDC_G5 */
|
||||
<STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */
|
||||
<STM32_PINMUX('I', 2, AF14)>, /* LTDC_G7 */
|
||||
<STM32_PINMUX('I', 4, AF14)>, /* LTDC_B4 */
|
||||
<STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */
|
||||
<STM32_PINMUX('B', 8, AF14)>, /* LTDC_B6 */
|
||||
<STM32_PINMUX('I', 7, AF14)>, /* LTDC_B7 */
|
||||
<STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */
|
||||
<STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
st,neg-edge;
|
||||
vmmc-supply = <&vdd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
pinctrl-1 = <&uart4_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart4_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* J31: RS323 */
|
||||
&uart8 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,59 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutons(India)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp157a-microgea-stm32mp1.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxaa-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Engicam MicroGEA STM32MP1 MicroDev 2.0 Carrier Board";
|
||||
compatible = "engicam,microgea-stm32mp1-microdev2.0",
|
||||
"engicam,microgea-stm32mp1", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
serial1 = &uart8;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
st,neg-edge;
|
||||
vmmc-supply = <&vdd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
pinctrl-1 = <&uart4_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart4_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* J31: RS323 */
|
||||
&uart8 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,148 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (c) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutons(India)
|
||||
*/
|
||||
|
||||
/ {
|
||||
compatible = "engicam,microgea-stm32mp1", "st,stm32mp157";
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x10000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mcuram2: mcuram2@10000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring0: vdev0vring0@10040000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10040000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring1: vdev0vring1@10041000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10041000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0buffer: vdev0buffer@10042000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10042000 0x4000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcuram: mcuram@30000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x30000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
retram: retram@38000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x38000000 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
vin: regulator-vin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vin";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddcore: regulator-vddcore {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vin>;
|
||||
};
|
||||
|
||||
vdd: regulator-vdd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vin>;
|
||||
};
|
||||
|
||||
vddq_ddr: regulator-vddq-ddr {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vddq_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <&vin>;
|
||||
};
|
||||
};
|
||||
|
||||
&dts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fmc {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&fmc_pins_a>;
|
||||
pinctrl-1 = <&fmc_sleep_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
nand-controller@4,0 {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-on-flash-bbt;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iwdg2{
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&m4_rproc{
|
||||
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
||||
<&vdev0vring1>, <&vdev0buffer>;
|
||||
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>;
|
||||
mbox-names = "vq0", "vq1", "shutdown";
|
||||
interrupt-parent = <&exti>;
|
||||
interrupts = <68 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vrefbuf {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
vdda-supply = <&vdd>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,88 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c-dk2.dts"
|
||||
#include "stm32mp15-scmi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
|
||||
compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
|
||||
|
||||
reserved-memory {
|
||||
optee@de000000 {
|
||||
reg = <0xde000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cryp1 {
|
||||
clocks = <&scmi_clk CK_SCMI_CRYP1>;
|
||||
resets = <&scmi_reset RST_SCMI_CRYP1>;
|
||||
};
|
||||
|
||||
&dsi {
|
||||
phy-dsi-supply = <&scmi_reg18>;
|
||||
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
|
||||
};
|
||||
|
||||
&gpioz {
|
||||
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&mdma1 {
|
||||
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||
};
|
||||
|
||||
&m4_rproc {
|
||||
/delete-property/ st,syscfg-holdboot;
|
||||
resets = <&scmi_reset RST_SCMI_MCU>,
|
||||
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
|
||||
reset-names = "mcu_rst", "hold_boot";
|
||||
};
|
||||
|
||||
&rcc {
|
||||
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||
<&scmi_clk CK_SCMI_HSI>,
|
||||
<&scmi_clk CK_SCMI_CSI>,
|
||||
<&scmi_clk CK_SCMI_LSE>,
|
||||
<&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||
};
|
||||
@@ -1,94 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15xc.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxac-pinctrl.dtsi"
|
||||
#include "stm32mp15xx-dkx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
|
||||
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
ethernet0 = ðernet0;
|
||||
serial3 = &usart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&cryp1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
panel@0 {
|
||||
compatible = "orisetech,otm8009a";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
|
||||
power-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_in {
|
||||
remote-endpoint = <<dc_ep1_out>;
|
||||
};
|
||||
|
||||
&dsi_out {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
touchscreen@38 {
|
||||
compatible = "focaltech,ft6236";
|
||||
reg = <0x38>;
|
||||
interrupts = <2 2>;
|
||||
interrupt-parent = <&gpiof>;
|
||||
interrupt-controller;
|
||||
touchscreen-size-x = <480>;
|
||||
touchscreen-size-y = <800>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
<dc {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ltdc_ep1_out: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&usart2_pins_c>;
|
||||
pinctrl-1 = <&usart2_sleep_pins_c>;
|
||||
pinctrl-2 = <&usart2_idle_pins_c>;
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -1,87 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c-ed1.dts"
|
||||
#include "stm32mp15-scmi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
|
||||
compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
reserved-memory {
|
||||
optee@fe000000 {
|
||||
reg = <0xfe000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cryp1 {
|
||||
clocks = <&scmi_clk CK_SCMI_CRYP1>;
|
||||
resets = <&scmi_reset RST_SCMI_CRYP1>;
|
||||
};
|
||||
|
||||
&dsi {
|
||||
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
|
||||
};
|
||||
|
||||
&gpioz {
|
||||
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&mdma1 {
|
||||
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||
};
|
||||
|
||||
&m4_rproc {
|
||||
/delete-property/ st,syscfg-holdboot;
|
||||
resets = <&scmi_reset RST_SCMI_MCU>,
|
||||
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
|
||||
reset-names = "mcu_rst", "hold_boot";
|
||||
};
|
||||
|
||||
&rcc {
|
||||
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||
<&scmi_clk CK_SCMI_HSI>,
|
||||
<&scmi_clk CK_SCMI_CSI>,
|
||||
<&scmi_clk CK_SCMI_LSE>,
|
||||
<&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||
};
|
||||
@@ -1,403 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157.dtsi"
|
||||
#include "stm32mp15xc.dtsi"
|
||||
#include "stm32mp15-pinctrl.dtsi"
|
||||
#include "stm32mp15xxaa-pinctrl.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mfd/st,stpmic1.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C eval daughter";
|
||||
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xC0000000 0x40000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mcuram2: mcuram2@10000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring0: vdev0vring0@10040000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10040000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring1: vdev0vring1@10041000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10041000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0buffer: vdev0buffer@10042000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10042000 0x4000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcuram: mcuram@30000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x30000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
retram: retram@38000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x38000000 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
sd_switch: regulator-sd_switch {
|
||||
compatible = "regulator-gpio";
|
||||
regulator-name = "sd_switch";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-type = "voltage";
|
||||
regulator-always-on;
|
||||
|
||||
gpios = <&gpiof 14 GPIO_ACTIVE_HIGH>;
|
||||
gpios-states = <0>;
|
||||
states = <1800000 0x1>,
|
||||
<2900000 0x0>;
|
||||
};
|
||||
|
||||
vin: vin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vin";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
/* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */
|
||||
pinctrl-0 = <&adc1_in6_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
vdd-supply = <&vdd>;
|
||||
vdda-supply = <&vdda>;
|
||||
vref-supply = <&vdda>;
|
||||
status = "disabled";
|
||||
adc1: adc@0 {
|
||||
status = "okay";
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
/* 16.5 ck_cycles sampling time */
|
||||
st,min-sample-time-ns = <400>;
|
||||
};
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
st,min-sample-time-ns = <400>;
|
||||
};
|
||||
channel@6 {
|
||||
reg = <6>;
|
||||
st,min-sample-time-ns = <400>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&crc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryp1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dac_ch1_pins_a &dac_ch2_pins_a>;
|
||||
vref-supply = <&vdda>;
|
||||
status = "disabled";
|
||||
dac1: dac@1 {
|
||||
status = "okay";
|
||||
};
|
||||
dac2: dac@2 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&dts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
pinctrl-1 = <&i2c4_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
pmic: stpmic@33 {
|
||||
compatible = "st,stpmic1";
|
||||
reg = <0x33>;
|
||||
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmic1-regulators";
|
||||
buck1-supply = <&vin>;
|
||||
buck2-supply = <&vin>;
|
||||
buck3-supply = <&vin>;
|
||||
buck4-supply = <&vin>;
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo2-supply = <&v3v3>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo4-supply = <&vin>;
|
||||
ldo5-supply = <&v3v3>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
vref_ddr-supply = <&vin>;
|
||||
boost-supply = <&vin>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore: buck1 {
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_ddr: buck2 {
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd: buck3 {
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
v3v3: buck4 {
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
};
|
||||
|
||||
vdda: ldo1 {
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
interrupts = <IT_CURLIM_LDO1 0>;
|
||||
};
|
||||
|
||||
v2v8: ldo2 {
|
||||
regulator-name = "v2v8";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
interrupts = <IT_CURLIM_LDO2 0>;
|
||||
};
|
||||
|
||||
vtt_ddr: ldo3 {
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_usb: ldo4 {
|
||||
regulator-name = "vdd_usb";
|
||||
interrupts = <IT_CURLIM_LDO4 0>;
|
||||
};
|
||||
|
||||
vdd_sd: ldo5 {
|
||||
regulator-name = "vdd_sd";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
interrupts = <IT_CURLIM_LDO5 0>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v1v8: ldo6 {
|
||||
regulator-name = "v1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
interrupts = <IT_CURLIM_LDO6 0>;
|
||||
};
|
||||
|
||||
vref_ddr: vref_ddr {
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
bst_out: boost {
|
||||
regulator-name = "bst_out";
|
||||
interrupts = <IT_OCP_BOOST 0>;
|
||||
};
|
||||
|
||||
vbus_otg: pwr_sw1 {
|
||||
regulator-name = "vbus_otg";
|
||||
interrupts = <IT_OCP_OTG 0>;
|
||||
};
|
||||
|
||||
vbus_sw: pwr_sw2 {
|
||||
regulator-name = "vbus_sw";
|
||||
interrupts = <IT_OCP_SWOUT 0>;
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
onkey {
|
||||
compatible = "st,stpmic1-onkey";
|
||||
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
||||
interrupt-names = "onkey-falling", "onkey-rising";
|
||||
power-off-time-sec = <10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "st,stpmic1-wdt";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&m4_rproc {
|
||||
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
||||
<&vdev0vring1>, <&vdev0buffer>;
|
||||
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
|
||||
mbox-names = "vq0", "vq1", "shutdown", "detach";
|
||||
interrupt-parent = <&exti>;
|
||||
interrupts = <68 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwr_regulators {
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>;
|
||||
cd-gpios = <&gpiog 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
disable-wp;
|
||||
st,sig-dir;
|
||||
st,neg-edge;
|
||||
st,use-ckin;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&vdd_sd>;
|
||||
vqmmc-supply = <&sd_switch>;
|
||||
sd-uhs-sdr12;
|
||||
sd-uhs-sdr25;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-ddr50;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
|
||||
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
|
||||
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
st,neg-edge;
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
vqmmc-supply = <&vdd>;
|
||||
mmc-ddr-3_3v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&timers6 {
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
timer@5 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
pinctrl-1 = <&uart4_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart4_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
vbus-supply = <&vbus_otg>;
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
@@ -1,93 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c-ev1.dts"
|
||||
#include "stm32mp15-scmi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
|
||||
compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
|
||||
"st,stm32mp157";
|
||||
|
||||
reserved-memory {
|
||||
optee@fe000000 {
|
||||
reg = <0xfe000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cryp1 {
|
||||
clocks = <&scmi_clk CK_SCMI_CRYP1>;
|
||||
resets = <&scmi_reset RST_SCMI_CRYP1>;
|
||||
};
|
||||
|
||||
&dsi {
|
||||
phy-dsi-supply = <&scmi_reg18>;
|
||||
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
|
||||
};
|
||||
|
||||
&gpioz {
|
||||
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&m_can1 {
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
|
||||
};
|
||||
|
||||
&mdma1 {
|
||||
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||
};
|
||||
|
||||
&m4_rproc {
|
||||
/delete-property/ st,syscfg-holdboot;
|
||||
resets = <&scmi_reset RST_SCMI_MCU>,
|
||||
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
|
||||
reset-names = "mcu_rst", "hold_boot";
|
||||
};
|
||||
|
||||
&rcc {
|
||||
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||
<&scmi_clk CK_SCMI_HSI>,
|
||||
<&scmi_clk CK_SCMI_CSI>,
|
||||
<&scmi_clk CK_SCMI_LSE>,
|
||||
<&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||
};
|
||||
@@ -1,414 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
|
||||
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c-ed1.dts"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/media/video-interfaces.h>
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
|
||||
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
aliases {
|
||||
serial1 = &usart3;
|
||||
ethernet0 = ðernet0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_ext_camera: clk-ext-camera {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
||||
joystick {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&joystick_pins>;
|
||||
pinctrl-names = "default";
|
||||
button-0 {
|
||||
label = "JoySel";
|
||||
linux,code = <KEY_ENTER>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
button-1 {
|
||||
label = "JoyDown";
|
||||
linux,code = <KEY_DOWN>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
button-2 {
|
||||
label = "JoyLeft";
|
||||
linux,code = <KEY_LEFT>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <2 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
button-3 {
|
||||
label = "JoyRight";
|
||||
linux,code = <KEY_RIGHT>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <3 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
button-4 {
|
||||
label = "JoyUp";
|
||||
linux,code = <KEY_UP>;
|
||||
interrupt-parent = <&stmfx_pinctrl>;
|
||||
interrupts = <4 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
panel_backlight: panel-backlight {
|
||||
compatible = "gpio-backlight";
|
||||
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
|
||||
default-on;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&cec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cec_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcmi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&dcmi_pins_a>;
|
||||
pinctrl-1 = <&dcmi_sleep_pins_a>;
|
||||
|
||||
port {
|
||||
dcmi_0: endpoint {
|
||||
remote-endpoint = <&ov5640_0>;
|
||||
bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
panel@0 {
|
||||
compatible = "raydium,rm68200";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpiof 15 GPIO_ACTIVE_LOW>;
|
||||
backlight = <&panel_backlight>;
|
||||
power-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
dsi_panel_in: endpoint {
|
||||
remote-endpoint = <&dsi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_in {
|
||||
remote-endpoint = <<dc_ep0_out>;
|
||||
};
|
||||
|
||||
&dsi_out {
|
||||
remote-endpoint = <&dsi_panel_in>;
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
||||
pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
phy-mode = "rgmii-id";
|
||||
max-speed = <1000>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fmc {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&fmc_pins_a>;
|
||||
pinctrl-1 = <&fmc_sleep_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
nand-controller@4,0 {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
reg = <0>;
|
||||
nand-on-flash-bbt;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c2_pins_a>;
|
||||
pinctrl-1 = <&i2c2_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
|
||||
ov5640: camera@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
clocks = <&clk_ext_camera>;
|
||||
clock-names = "xclk";
|
||||
AVDD-supply = <&v2v8>;
|
||||
DOVDD-supply = <&v2v8>;
|
||||
DVDD-supply = <&v2v8>;
|
||||
powerdown-gpios = <&stmfx_pinctrl 18 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL)>;
|
||||
reset-gpios = <&stmfx_pinctrl 19 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>;
|
||||
rotation = <180>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
ov5640_0: endpoint {
|
||||
remote-endpoint = <&dcmi_0>;
|
||||
bus-width = <8>;
|
||||
data-shift = <2>; /* lines 9:2 are used */
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
pclk-sample = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
stmfx: stmfx@42 {
|
||||
compatible = "st,stmfx-0300";
|
||||
reg = <0x42>;
|
||||
interrupts = <8 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
vdd-supply = <&v3v3>;
|
||||
|
||||
stmfx_pinctrl: pinctrl {
|
||||
compatible = "st,stmfx-0300-pinctrl";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&stmfx_pinctrl 0 0 24>;
|
||||
|
||||
joystick_pins: joystick-pins {
|
||||
pins = "gpio0", "gpio1", "gpio2", "gpio3", "gpio4";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c5_pins_a>;
|
||||
pinctrl-1 = <&i2c5_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
<dc {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
ltdc_ep0_out: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&m_can1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&m_can1_pins_a>;
|
||||
pinctrl-1 = <&m_can1_sleep_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qspi_clk_pins_a
|
||||
&qspi_bk1_pins_a
|
||||
&qspi_cs1_pins_a
|
||||
&qspi_bk2_pins_a
|
||||
&qspi_cs2_pins_a>;
|
||||
pinctrl-1 = <&qspi_clk_sleep_pins_a
|
||||
&qspi_bk1_sleep_pins_a
|
||||
&qspi_cs1_sleep_pins_a
|
||||
&qspi_bk2_sleep_pins_a
|
||||
&qspi_cs2_sleep_pins_a>;
|
||||
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash0: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
flash1: flash@1 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc3 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins_a>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timers2 {
|
||||
/* spare dmas for other usage (un-delete to enable pwm capture) */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm2_pins_a>;
|
||||
pinctrl-1 = <&pwm2_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@1 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers8 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm8_pins_a>;
|
||||
pinctrl-1 = <&pwm8_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@7 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers12 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm12_pins_a>;
|
||||
pinctrl-1 = <&pwm12_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@11 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&usart3 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&usart3_pins_b>;
|
||||
pinctrl-1 = <&usart3_sleep_pins_b>;
|
||||
pinctrl-2 = <&usart3_idle_pins_b>;
|
||||
/*
|
||||
* HW flow control USART3_RTS is optional, and isn't default wired to
|
||||
* the connector. SB23 needs to be soldered in order to use it, and R77
|
||||
* (ETH_CLK) should be removed.
|
||||
*/
|
||||
uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbh_ehci {
|
||||
phys = <&usbphyc_port0>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* onboard HUB */
|
||||
hub@1 {
|
||||
compatible = "usb424,2514";
|
||||
reg = <1>;
|
||||
vdd-supply = <&v3v3>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
pinctrl-0 = <&usbotg_hs_pins_a>;
|
||||
pinctrl-names = "default";
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-fs-rftime-tuning;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <15>;
|
||||
st,trim-hs-impedance = <1>;
|
||||
st,tune-squelch-level = <3>;
|
||||
st,tune-hs-rx-offset = <2>;
|
||||
st,no-lsfs-sc;
|
||||
|
||||
connector {
|
||||
compatible = "usb-a-connector";
|
||||
vbus-supply = <&vbus_sw>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-fs-rftime-tuning;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <15>;
|
||||
st,trim-hs-impedance = <1>;
|
||||
st,tune-squelch-level = <3>;
|
||||
st,tune-hs-rx-offset = <2>;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
@@ -1,18 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp1: cryp@54001000 {
|
||||
compatible = "st,stm32mp1-cryp";
|
||||
reg = <0x54001000 0x400>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc CRYP1>;
|
||||
resets = <&rcc CRYP1_R>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,741 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mfd/st,stpmic1.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart4;
|
||||
serial1 = &usart3;
|
||||
serial2 = &uart7;
|
||||
};
|
||||
|
||||
memory@c0000000 {
|
||||
device_type = "memory";
|
||||
reg = <0xc0000000 0x20000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
mcuram2: mcuram2@10000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring0: vdev0vring0@10040000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10040000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0vring1: vdev0vring1@10041000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10041000 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
vdev0buffer: vdev0buffer@10042000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x10042000 0x4000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcuram: mcuram@30000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x30000000 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
retram: retram@38000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x38000000 0x10000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
led {
|
||||
compatible = "gpio-leds";
|
||||
led-blue {
|
||||
label = "heartbeat";
|
||||
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "STM32MP15-DK";
|
||||
routing =
|
||||
"Playback" , "MCLK",
|
||||
"Capture" , "MCLK",
|
||||
"MICL" , "Mic Bias";
|
||||
dais = <&sai2a_port &sai2b_port &i2s2_port>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
vin: vin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vin";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&adc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&adc12_usb_cc_pins_a>;
|
||||
vdd-supply = <&vdd>;
|
||||
vdda-supply = <&vdd>;
|
||||
vref-supply = <&vrefbuf>;
|
||||
status = "okay";
|
||||
adc1: adc@0 {
|
||||
status = "okay";
|
||||
/*
|
||||
* Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
|
||||
* Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
|
||||
* 5 * (56 + 47kOhms) * 5pF => 2.5us.
|
||||
* Use arbitrary margin here (e.g. 5us).
|
||||
*/
|
||||
channel@18 {
|
||||
reg = <18>;
|
||||
st,min-sample-time-ns = <5000>;
|
||||
};
|
||||
channel@19 {
|
||||
reg = <19>;
|
||||
st,min-sample-time-ns = <5000>;
|
||||
};
|
||||
};
|
||||
adc2: adc@100 {
|
||||
status = "okay";
|
||||
/* USB Type-C CC1 & CC2 */
|
||||
channel@18 {
|
||||
reg = <18>;
|
||||
st,min-sample-time-ns = <5000>;
|
||||
};
|
||||
channel@19 {
|
||||
reg = <19>;
|
||||
st,min-sample-time-ns = <5000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cec {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cec_pins_b>;
|
||||
pinctrl-1 = <&cec_sleep_pins_b>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&crc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dts {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ðernet0 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <ðernet0_rgmii_pins_a>;
|
||||
pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
phy-mode = "rgmii-id";
|
||||
max-speed = <1000>;
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,dwmac-mdio";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c1_pins_a>;
|
||||
pinctrl-1 = <&i2c1_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <100>;
|
||||
i2c-scl-falling-time-ns = <7>;
|
||||
status = "okay";
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
hdmi-transmitter@39 {
|
||||
compatible = "sil,sii9022";
|
||||
reg = <0x39>;
|
||||
iovcc-supply = <&v3v3_hdmi>;
|
||||
cvcc12-supply = <&v1v2_hdmi>;
|
||||
reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-parent = <&gpiog>;
|
||||
#sound-dai-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
sii9022_in: endpoint {
|
||||
remote-endpoint = <<dc_ep0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
sii9022_tx_endpoint: endpoint {
|
||||
remote-endpoint = <&i2s2_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cs42l51: cs42l51@4a {
|
||||
compatible = "cirrus,cs42l51";
|
||||
reg = <0x4a>;
|
||||
#sound-dai-cells = <0>;
|
||||
VL-supply = <&v3v3>;
|
||||
VD-supply = <&v1v8_audio>;
|
||||
VA-supply = <&v1v8_audio>;
|
||||
VAHP-supply = <&v1v8_audio>;
|
||||
reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&sai2a>;
|
||||
clock-names = "MCLK";
|
||||
status = "okay";
|
||||
|
||||
cs42l51_port: port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cs42l51_tx_endpoint: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&sai2a_endpoint>;
|
||||
frame-master = <&cs42l51_tx_endpoint>;
|
||||
bitclock-master = <&cs42l51_tx_endpoint>;
|
||||
};
|
||||
|
||||
cs42l51_rx_endpoint: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&sai2b_endpoint>;
|
||||
frame-master = <&cs42l51_rx_endpoint>;
|
||||
bitclock-master = <&cs42l51_rx_endpoint>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c4_pins_a>;
|
||||
pinctrl-1 = <&i2c4_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
|
||||
stusb1600@28 {
|
||||
compatible = "st,stusb1600";
|
||||
reg = <0x28>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-parent = <&gpioi>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&stusb1600_pins_a>;
|
||||
status = "okay";
|
||||
vdd-supply = <&vin>;
|
||||
|
||||
connector {
|
||||
compatible = "usb-c-connector";
|
||||
label = "USB-C";
|
||||
power-role = "dual";
|
||||
typec-power-opmode = "default";
|
||||
|
||||
port {
|
||||
con_usbotg_hs_ep: endpoint {
|
||||
remote-endpoint = <&usbotg_hs_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmic: stpmic@33 {
|
||||
compatible = "st,stpmic1";
|
||||
reg = <0x33>;
|
||||
interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
|
||||
regulators {
|
||||
compatible = "st,stpmic1-regulators";
|
||||
buck1-supply = <&vin>;
|
||||
buck2-supply = <&vin>;
|
||||
buck3-supply = <&vin>;
|
||||
buck4-supply = <&vin>;
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo2-supply = <&vin>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo4-supply = <&vin>;
|
||||
ldo5-supply = <&vin>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
vref_ddr-supply = <&vin>;
|
||||
boost-supply = <&vin>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore: buck1 {
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_ddr: buck2 {
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd: buck3 {
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
v3v3: buck4 {
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
};
|
||||
|
||||
v1v8_audio: ldo1 {
|
||||
regulator-name = "v1v8_audio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO1 0>;
|
||||
};
|
||||
|
||||
v3v3_hdmi: ldo2 {
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO2 0>;
|
||||
};
|
||||
|
||||
vtt_ddr: ldo3 {
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
};
|
||||
|
||||
vdd_usb: ldo4 {
|
||||
regulator-name = "vdd_usb";
|
||||
interrupts = <IT_CURLIM_LDO4 0>;
|
||||
};
|
||||
|
||||
vdda: ldo5 {
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
interrupts = <IT_CURLIM_LDO5 0>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v1v2_hdmi: ldo6 {
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
interrupts = <IT_CURLIM_LDO6 0>;
|
||||
};
|
||||
|
||||
vref_ddr: vref_ddr {
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
bst_out: boost {
|
||||
regulator-name = "bst_out";
|
||||
interrupts = <IT_OCP_BOOST 0>;
|
||||
};
|
||||
|
||||
vbus_otg: pwr_sw1 {
|
||||
regulator-name = "vbus_otg";
|
||||
interrupts = <IT_OCP_OTG 0>;
|
||||
};
|
||||
|
||||
vbus_sw: pwr_sw2 {
|
||||
regulator-name = "vbus_sw";
|
||||
interrupts = <IT_OCP_SWOUT 0>;
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
onkey {
|
||||
compatible = "st,stpmic1-onkey";
|
||||
interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>;
|
||||
interrupt-names = "onkey-falling", "onkey-rising";
|
||||
power-off-time-sec = <10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog {
|
||||
compatible = "st,stpmic1-wdt";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c5_pins_a>;
|
||||
pinctrl-1 = <&i2c5_sleep_pins_a>;
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
clock-frequency = <400000>;
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
||||
clock-names = "pclk", "i2sclk", "x8k", "x11k";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2s2_pins_a>;
|
||||
pinctrl-1 = <&i2s2_sleep_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
i2s2_port: port {
|
||||
i2s2_endpoint: endpoint {
|
||||
remote-endpoint = <&sii9022_tx_endpoint>;
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ipcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
<dc {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <<dc_pins_a>;
|
||||
pinctrl-1 = <<dc_sleep_pins_a>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
ltdc_ep0_out: endpoint {
|
||||
remote-endpoint = <&sii9022_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&m4_rproc {
|
||||
memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
|
||||
<&vdev0vring1>, <&vdev0buffer>;
|
||||
mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
|
||||
mbox-names = "vq0", "vq1", "shutdown", "detach";
|
||||
interrupt-parent = <&exti>;
|
||||
interrupts = <68 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwr_regulators {
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
|
||||
clock-names = "pclk", "x8k", "x11k";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&sai2a_pins_a>, <&sai2b_pins_b>;
|
||||
pinctrl-1 = <&sai2a_sleep_pins_a>, <&sai2b_sleep_pins_b>;
|
||||
status = "okay";
|
||||
|
||||
sai2a: audio-controller@4400b004 {
|
||||
#clock-cells = <0>;
|
||||
dma-names = "tx";
|
||||
status = "okay";
|
||||
|
||||
sai2a_port: port {
|
||||
sai2a_endpoint: endpoint {
|
||||
remote-endpoint = <&cs42l51_tx_endpoint>;
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
dai-tdm-slot-num = <2>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sai2b: audio-controller@4400b024 {
|
||||
dma-names = "rx";
|
||||
st,sync = <&sai2a 2>;
|
||||
clocks = <&rcc SAI2_K>, <&sai2a>;
|
||||
clock-names = "sai_ck", "MCLK";
|
||||
status = "okay";
|
||||
|
||||
sai2b_port: port {
|
||||
sai2b_endpoint: endpoint {
|
||||
remote-endpoint = <&cs42l51_rx_endpoint>;
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
dai-tdm-slot-num = <2>;
|
||||
dai-tdm-slot-width = <32>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc1_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
|
||||
cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
||||
disable-wp;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc3 {
|
||||
pinctrl-names = "default", "opendrain", "sleep";
|
||||
pinctrl-0 = <&sdmmc3_b4_pins_a>;
|
||||
pinctrl-1 = <&sdmmc3_b4_od_pins_a>;
|
||||
pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>;
|
||||
broken-cd;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&timers1 {
|
||||
/* spare dmas for other usage */
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm1_pins_a>;
|
||||
pinctrl-1 = <&pwm1_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers3 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm3_pins_a>;
|
||||
pinctrl-1 = <&pwm3_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@2 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers4 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm4_pins_a &pwm4_pins_b>;
|
||||
pinctrl-1 = <&pwm4_sleep_pins_a &pwm4_sleep_pins_b>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@3 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers5 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm5_pins_a>;
|
||||
pinctrl-1 = <&pwm5_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@4 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers6 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
timer@5 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&timers12 {
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
pwm {
|
||||
pinctrl-0 = <&pwm12_pins_a>;
|
||||
pinctrl-1 = <&pwm12_sleep_pins_a>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
status = "okay";
|
||||
};
|
||||
timer@11 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart4_pins_a>;
|
||||
pinctrl-1 = <&uart4_sleep_pins_a>;
|
||||
pinctrl-2 = <&uart4_idle_pins_a>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&uart7_pins_c>;
|
||||
pinctrl-1 = <&uart7_sleep_pins_c>;
|
||||
pinctrl-2 = <&uart7_idle_pins_c>;
|
||||
/delete-property/dmas;
|
||||
/delete-property/dma-names;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usart3 {
|
||||
pinctrl-names = "default", "sleep", "idle";
|
||||
pinctrl-0 = <&usart3_pins_c>;
|
||||
pinctrl-1 = <&usart3_sleep_pins_c>;
|
||||
pinctrl-2 = <&usart3_idle_pins_c>;
|
||||
uart-has-rtscts;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbh_ehci {
|
||||
phys = <&usbphyc_port0>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* onboard HUB */
|
||||
hub@1 {
|
||||
compatible = "usb424,2514";
|
||||
reg = <1>;
|
||||
vdd-supply = <&v3v3>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbotg_hs {
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
usb-role-switch;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
usbotg_hs_ep: endpoint {
|
||||
remote-endpoint = <&con_usbotg_hs_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usbphyc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-fs-rftime-tuning;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <15>;
|
||||
st,trim-hs-impedance = <1>;
|
||||
st,tune-squelch-level = <3>;
|
||||
st,tune-hs-rx-offset = <2>;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
|
||||
&usbphyc_port1 {
|
||||
phy-supply = <&vdd_usb>;
|
||||
st,tune-hs-dc-level = <2>;
|
||||
st,enable-fs-rftime-tuning;
|
||||
st,enable-hs-rftime-reduction;
|
||||
st,trim-hs-current = <15>;
|
||||
st,trim-hs-impedance = <1>;
|
||||
st,tune-squelch-level = <3>;
|
||||
st,tune-hs-rx-offset = <2>;
|
||||
st,no-lsfs-sc;
|
||||
};
|
||||
|
||||
&vrefbuf {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
vdda-supply = <&vdd>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,85 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AA>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@5000b000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@5000c000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
st,package = <STM32MP_PKG_AA>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
@@ -1,57 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AB>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <6>;
|
||||
gpio-ranges = <&pinctrl 6 86 6>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl 6 102 10>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <2>;
|
||||
gpio-ranges = <&pinctrl 0 112 2>;
|
||||
};
|
||||
};
|
||||
@@ -1,73 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AC>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
st,package = <STM32MP_PKG_AC>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
@@ -1,57 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2019 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AD>;
|
||||
|
||||
gpioa: gpio@50002000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@50003000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <6>;
|
||||
gpio-ranges = <&pinctrl 6 86 6>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl 6 102 10>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <2>;
|
||||
gpio-ranges = <&pinctrl 0 112 2>;
|
||||
};
|
||||
};
|
||||
@@ -1,38 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
|
||||
&pinctrl {
|
||||
usart2_pins_a: usart2-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
|
||||
bias-disable;
|
||||
drive-push-pull;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_idle_pins_a: usart2-idle-0 {
|
||||
pins1 {
|
||||
pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */
|
||||
};
|
||||
pins2 {
|
||||
pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
usart2_sleep_pins_a: usart2-sleep-0 {
|
||||
pins {
|
||||
pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */
|
||||
<STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,301 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a35";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a35-pmu";
|
||||
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>;
|
||||
interrupt-parent = <&intc>;
|
||||
};
|
||||
|
||||
arm_wdt: watchdog {
|
||||
compatible = "arm,smc-wdt";
|
||||
arm,smc-id = <0xb200005a>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
ck_flexgen_08: ck-flexgen-08 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
ck_flexgen_51: ck-flexgen-51 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
ck_icn_ls_mcu: ck-icn-ls-mcu {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
scmi {
|
||||
compatible = "linaro,scmi-optee";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
linaro,optee-channel-id = <0>;
|
||||
|
||||
scmi_clk: protocol@14 {
|
||||
reg = <0x14>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
scmi_reset: protocol@16 {
|
||||
reg = <0x16>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
intc: interrupt-controller@4ac00000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x4ac10000 0x0 0x1000>,
|
||||
<0x0 0x4ac20000 0x0 0x2000>,
|
||||
<0x0 0x4ac40000 0x0 0x2000>,
|
||||
<0x0 0x4ac60000 0x0 0x2000>;
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
always-on;
|
||||
};
|
||||
|
||||
soc@0 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
ranges = <0x0 0x0 0x0 0x80000000>;
|
||||
|
||||
rifsc: rifsc-bus@42080000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0x42080000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
usart2: serial@400e0000 {
|
||||
compatible = "st,stm32h7-uart";
|
||||
reg = <0x400e0000 0x400>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ck_flexgen_08>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
bsec: efuse@44000000 {
|
||||
compatible = "st,stm32mp25-bsec";
|
||||
reg = <0x44000000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
part_number_otp@24 {
|
||||
reg = <0x24 0x4>;
|
||||
};
|
||||
|
||||
package_otp@1e8 {
|
||||
reg = <0x1e8 0x1>;
|
||||
bits = <0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
syscfg: syscon@44230000 {
|
||||
compatible = "st,stm32mp25-syscfg", "syscon";
|
||||
reg = <0x44230000 0x10000>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@44240000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp257-pinctrl";
|
||||
ranges = <0 0x44240000 0xa0400>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x0 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOA";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x10000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOB";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x20000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOC";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x30000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOD";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x40000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOE";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x50000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOF";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x60000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x70000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOH";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x80000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOI";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpioj: gpio@442d0000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x90000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOJ";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiok: gpio@442e0000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0xa0000 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOK";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pinctrl@46200000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,stm32mp257-z-pinctrl";
|
||||
ranges = <0 0x46200000 0x400>;
|
||||
pins-are-numbered;
|
||||
|
||||
gpioz: gpio@46200000 {
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0 0x400>;
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
st,bank-name = "GPIOZ";
|
||||
st,bank-ioport = <11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,23 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include "stm32mp251.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a35";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>;
|
||||
};
|
||||
};
|
||||
@@ -1,9 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include "stm32mp253.dtsi"
|
||||
|
||||
/ {
|
||||
};
|
||||
@@ -1,9 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
#include "stm32mp255.dtsi"
|
||||
|
||||
/ {
|
||||
};
|
||||
@@ -5,8 +5,89 @@
|
||||
|
||||
#include "stm32mp25-u-boot.dtsi"
|
||||
|
||||
/ {
|
||||
config {
|
||||
u-boot,boot-led = "led-blue";
|
||||
u-boot,mmc-env-partition = "u-boot-env";
|
||||
};
|
||||
|
||||
clocks {
|
||||
ck_flexgen_08: ck-flexgen-08 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <64000000>;
|
||||
};
|
||||
|
||||
ck_flexgen_51: ck-flexgen-51 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
ck_icn_ls_mcu: ck-icn-ls-mcu {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpioa {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpiob {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpioc {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpiod {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpioe {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpiof {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpiog {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpioh {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpioi {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpioj {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpiok {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&gpioz {
|
||||
clocks = <&ck_icn_ls_mcu>;
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
clocks = <&ck_flexgen_51>;
|
||||
/delete-property/resets;
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
bootph-all;
|
||||
clocks = <&ck_flexgen_08>;
|
||||
};
|
||||
|
||||
&usart2_pins_a {
|
||||
|
||||
@@ -1,55 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp257.dtsi"
|
||||
#include "stm32mp25xf.dtsi"
|
||||
#include "stm32mp25-pinctrl.dtsi"
|
||||
#include "stm32mp25xxai-pinctrl.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board";
|
||||
compatible = "st,stm32mp257f-ev1", "st,stm32mp257";
|
||||
|
||||
aliases {
|
||||
serial0 = &usart2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x1 0x0>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
fw@80000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x0 0x80000000 0x0 0x4000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&arm_wdt {
|
||||
timeout-sec = <32>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usart2 {
|
||||
pinctrl-names = "default", "idle", "sleep";
|
||||
pinctrl-0 = <&usart2_pins_a>;
|
||||
pinctrl-1 = <&usart2_idle_pins_a>;
|
||||
pinctrl-2 = <&usart2_sleep_pins_a>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,8 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
};
|
||||
@@ -1,8 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/ {
|
||||
};
|
||||
@@ -1,83 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AI>;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
status = "okay";
|
||||
ngpios = <14>;
|
||||
gpio-ranges = <&pinctrl 0 32 14>;
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 2 114 12>;
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 128 16>;
|
||||
};
|
||||
|
||||
gpioj: gpio@442d0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 144 16>;
|
||||
};
|
||||
|
||||
gpiok: gpio@442e0000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl 0 160 8>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
gpioz: gpio@46200000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 10>;
|
||||
};
|
||||
};
|
||||
@@ -1,71 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AK>;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
status = "okay";
|
||||
ngpios = <14>;
|
||||
gpio-ranges = <&pinctrl 0 32 14>;
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 2 114 12>;
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
gpioz: gpio@46200000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 10>;
|
||||
};
|
||||
};
|
||||
@@ -1,71 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2023 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
&pinctrl {
|
||||
st,package = <STM32MP_PKG_AL>;
|
||||
|
||||
gpioa: gpio@44240000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 0 16>;
|
||||
};
|
||||
|
||||
gpiob: gpio@44250000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@44260000 {
|
||||
status = "okay";
|
||||
ngpios = <14>;
|
||||
gpio-ranges = <&pinctrl 0 32 14>;
|
||||
};
|
||||
|
||||
gpiod: gpio@44270000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@44280000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@44290000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@442a0000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@442b0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 2 114 12>;
|
||||
};
|
||||
|
||||
gpioi: gpio@442c0000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl_z {
|
||||
gpioz: gpio@46200000 {
|
||||
status = "okay";
|
||||
ngpios = <10>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 10>;
|
||||
};
|
||||
};
|
||||
@@ -15,6 +15,7 @@ config STM32F4
|
||||
select STM32_SERIAL
|
||||
select STM32_TIMER
|
||||
select TIMER
|
||||
imply OF_UPSTREAM
|
||||
|
||||
config STM32F7
|
||||
bool "stm32f7 family"
|
||||
@@ -32,6 +33,7 @@ config STM32F7
|
||||
select STM32_TIMER
|
||||
select SUPPORT_SPL
|
||||
select TIMER
|
||||
imply OF_UPSTREAM
|
||||
imply SPL_OS_BOOT
|
||||
|
||||
config STM32H7
|
||||
@@ -51,6 +53,7 @@ config STM32H7
|
||||
select STM32_TIMER
|
||||
select SYSCON
|
||||
select TIMER
|
||||
imply OF_UPSTREAM
|
||||
|
||||
source "arch/arm/mach-stm32/stm32f4/Kconfig"
|
||||
source "arch/arm/mach-stm32/stm32f7/Kconfig"
|
||||
|
||||
@@ -52,6 +52,7 @@ config STM32MP13X
|
||||
select STM32_SERIAL
|
||||
select SYS_ARCH_TIMER
|
||||
imply CMD_NVEDIT_INFO
|
||||
imply OF_UPSTREAM
|
||||
help
|
||||
support of STMicroelectronics SOC STM32MP13x family
|
||||
STMicroelectronics MPU with core ARMv7
|
||||
@@ -73,6 +74,7 @@ config STM32MP15X
|
||||
select SUPPORT_SPL
|
||||
select SYS_ARCH_TIMER
|
||||
imply CMD_NVEDIT_INFO
|
||||
imply OF_UPSTREAM
|
||||
help
|
||||
support of STMicroelectronics SOC STM32MP15x family
|
||||
STM32MP157, STM32MP153 or STM32MP151
|
||||
@@ -94,6 +96,7 @@ config STM32MP25X
|
||||
imply CMD_NVEDIT_INFO
|
||||
imply DM_REGULATOR
|
||||
imply DM_REGULATOR_SCMI
|
||||
imply OF_UPSTREAM
|
||||
imply OPTEE
|
||||
imply RESET_SCMI
|
||||
imply SYSRESET_PSCI
|
||||
@@ -127,14 +130,6 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
|
||||
Partition on the second MMC to load U-Boot from when the MMC is being
|
||||
used in raw mode
|
||||
|
||||
config STM32_ETZPC
|
||||
bool "STM32 Extended TrustZone Protection"
|
||||
depends on STM32MP15X || STM32MP13X
|
||||
default y
|
||||
imply BOOTP_SERVERIP
|
||||
help
|
||||
Say y to enable STM32 Extended TrustZone Protection
|
||||
|
||||
config STM32_ECDSA_VERIFY
|
||||
bool "STM32 ECDSA verification via the ROM API"
|
||||
depends on SPL_ECDSA_VERIFY
|
||||
|
||||
@@ -14,12 +14,23 @@
|
||||
|
||||
/*
|
||||
* Closed device: OTP0
|
||||
* STM32MP15x: bit 6 of OPT0
|
||||
* STM32MP15x: bit 6 of OTP0
|
||||
* STM32MP13x: 0b111111 = 0x3F for OTP_SECURED closed device
|
||||
* STM32MP25x: bit 0 of OTP18
|
||||
*/
|
||||
#define STM32_OTP_CLOSE_ID 0
|
||||
#define STM32_OTP_STM32MP13X_CLOSE_MASK 0x3F
|
||||
#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6)
|
||||
#define STM32MP1_OTP_CLOSE_ID 0
|
||||
#define STM32_OTP_STM32MP13X_CLOSE_MASK GENMASK(5, 0)
|
||||
#define STM32_OTP_STM32MP15X_CLOSE_MASK BIT(6)
|
||||
#define STM32MP25_OTP_WORD8 8
|
||||
#define STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK GENMASK(7, 0)
|
||||
#define STM32MP25_OTP_CLOSE_ID 18
|
||||
#define STM32_OTP_STM32MP25X_CLOSE_MASK GENMASK(3, 0)
|
||||
#define STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK GENMASK(7, 4)
|
||||
#define STM32MP25_OTP_HWCONFIG 124
|
||||
#define STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK BIT(20)
|
||||
|
||||
#define STM32MP25_OTP_BOOTROM_CONF8 17
|
||||
#define STM32_OTP_STM32MP25X_OEM_KEY2_EN BIT(8)
|
||||
|
||||
/* PKH is the first element of the key list */
|
||||
#define STM32KEY_PKH 0
|
||||
@@ -27,8 +38,9 @@
|
||||
struct stm32key {
|
||||
char *name;
|
||||
char *desc;
|
||||
u8 start;
|
||||
u16 start;
|
||||
u8 size;
|
||||
int (*post_process)(struct udevice *dev);
|
||||
};
|
||||
|
||||
const struct stm32key stm32mp13_list[] = {
|
||||
@@ -55,6 +67,99 @@ const struct stm32key stm32mp15_list[] = {
|
||||
}
|
||||
};
|
||||
|
||||
static int post_process_oem_key2(struct udevice *dev);
|
||||
|
||||
const struct stm32key stm32mp25_list[] = {
|
||||
[STM32KEY_PKH] = {
|
||||
.name = "OEM-KEY1",
|
||||
.desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLA or M",
|
||||
.start = 144,
|
||||
.size = 8,
|
||||
},
|
||||
{
|
||||
.name = "OEM-KEY2",
|
||||
.desc = "Hash of the 8 ECC Public Keys Hashes Table (ECDSA is the authentication algorithm) for FSBLM",
|
||||
.start = 152,
|
||||
.size = 8,
|
||||
.post_process = post_process_oem_key2,
|
||||
},
|
||||
{
|
||||
.name = "FIP-EDMK",
|
||||
.desc = "Encryption/Decryption Master Key for FIP",
|
||||
.start = 260,
|
||||
.size = 8,
|
||||
},
|
||||
{
|
||||
.name = "EDMK1",
|
||||
.desc = "Encryption/Decryption Master Key for FSBLA or M",
|
||||
.start = 364,
|
||||
.size = 4,
|
||||
},
|
||||
{
|
||||
.name = "EDMK2",
|
||||
.desc = "Encryption/Decryption Master Key for FSBLM",
|
||||
.start = 360,
|
||||
.size = 4,
|
||||
}
|
||||
};
|
||||
|
||||
struct otp_close {
|
||||
u32 word;
|
||||
u32 mask_wr;
|
||||
u32 mask_rd;
|
||||
bool (*close_status_ops)(u32 value, u32 mask);
|
||||
};
|
||||
|
||||
static bool compare_mask_exact(u32 value, u32 mask)
|
||||
{
|
||||
return ((value & mask) == mask);
|
||||
}
|
||||
|
||||
static bool compare_any_bits(u32 value, u32 mask)
|
||||
{
|
||||
return ((value & mask) != 0);
|
||||
}
|
||||
|
||||
const struct otp_close stm32mp13_close_state_otp[] = {
|
||||
{
|
||||
.word = STM32MP1_OTP_CLOSE_ID,
|
||||
.mask_wr = STM32_OTP_STM32MP13X_CLOSE_MASK,
|
||||
.mask_rd = STM32_OTP_STM32MP13X_CLOSE_MASK,
|
||||
.close_status_ops = compare_mask_exact,
|
||||
}
|
||||
};
|
||||
|
||||
const struct otp_close stm32mp15_close_state_otp[] = {
|
||||
{
|
||||
.word = STM32MP1_OTP_CLOSE_ID,
|
||||
.mask_wr = STM32_OTP_STM32MP15X_CLOSE_MASK,
|
||||
.mask_rd = STM32_OTP_STM32MP15X_CLOSE_MASK,
|
||||
.close_status_ops = compare_mask_exact,
|
||||
}
|
||||
};
|
||||
|
||||
const struct otp_close stm32mp25_close_state_otp[] = {
|
||||
{
|
||||
.word = STM32MP25_OTP_WORD8,
|
||||
.mask_wr = STM32_OTP_STM32MP25X_BOOTROM_CLOSE_MASK,
|
||||
.mask_rd = 0,
|
||||
.close_status_ops = NULL
|
||||
},
|
||||
{
|
||||
.word = STM32MP25_OTP_CLOSE_ID,
|
||||
.mask_wr = STM32_OTP_STM32MP25X_CLOSE_MASK |
|
||||
STM32_OTP_STM32MP25X_PROVISIONING_DONE_MASK,
|
||||
.mask_rd = STM32_OTP_STM32MP25X_CLOSE_MASK,
|
||||
.close_status_ops = compare_any_bits
|
||||
},
|
||||
{
|
||||
.word = STM32MP25_OTP_HWCONFIG,
|
||||
.mask_wr = STM32_OTP_STM32MP25X_DISABLE_SCAN_MASK,
|
||||
.mask_rd = 0,
|
||||
.close_status_ops = NULL
|
||||
},
|
||||
};
|
||||
|
||||
/* index of current selected key in stm32key list, 0 = PKH by default */
|
||||
static u8 stm32key_index;
|
||||
|
||||
@@ -65,6 +170,9 @@ static u8 get_key_nb(void)
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP15X))
|
||||
return ARRAY_SIZE(stm32mp15_list);
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP25X))
|
||||
return ARRAY_SIZE(stm32mp25_list);
|
||||
}
|
||||
|
||||
static const struct stm32key *get_key(u8 index)
|
||||
@@ -74,15 +182,33 @@ static const struct stm32key *get_key(u8 index)
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP15X))
|
||||
return &stm32mp15_list[index];
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP25X))
|
||||
return &stm32mp25_list[index];
|
||||
}
|
||||
|
||||
static u32 get_otp_close_mask(void)
|
||||
static u8 get_otp_close_state_nb(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_STM32MP13X))
|
||||
return STM32_OTP_STM32MP13X_CLOSE_MASK;
|
||||
return ARRAY_SIZE(stm32mp13_close_state_otp);
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP15X))
|
||||
return STM32_OTP_STM32MP15X_CLOSE_MASK;
|
||||
return ARRAY_SIZE(stm32mp15_close_state_otp);
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP25X))
|
||||
return ARRAY_SIZE(stm32mp25_close_state_otp);
|
||||
}
|
||||
|
||||
static const struct otp_close *get_otp_close_state(u8 index)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_STM32MP13X))
|
||||
return &stm32mp13_close_state_otp[index];
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP15X))
|
||||
return &stm32mp15_close_state_otp[index];
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP25X))
|
||||
return &stm32mp25_close_state_otp[index];
|
||||
}
|
||||
|
||||
static int get_misc_dev(struct udevice **dev)
|
||||
@@ -96,13 +222,13 @@ static int get_misc_dev(struct udevice **dev)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void read_key_value(const struct stm32key *key, u32 addr)
|
||||
static void read_key_value(const struct stm32key *key, unsigned long addr)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < key->size; i++) {
|
||||
printf("%s OTP %i: [%08x] %08x\n", key->name, key->start + i,
|
||||
addr, __be32_to_cpu(*(u32 *)addr));
|
||||
(u32)addr, __be32_to_cpu(*(u32 *)addr));
|
||||
addr += 4;
|
||||
}
|
||||
}
|
||||
@@ -157,26 +283,42 @@ static int read_key_otp(struct udevice *dev, const struct stm32key *key, bool pr
|
||||
|
||||
static int read_close_status(struct udevice *dev, bool print, bool *closed)
|
||||
{
|
||||
int word, ret, result;
|
||||
u32 val, lock, mask;
|
||||
bool status;
|
||||
int ret, result, i;
|
||||
const struct otp_close *otp_close = NULL;
|
||||
u32 otp_close_nb = get_otp_close_state_nb();
|
||||
u32 val, lock, mask, word = 0;
|
||||
bool status = true;
|
||||
bool tested_once = false;
|
||||
|
||||
result = 0;
|
||||
word = STM32_OTP_CLOSE_ID;
|
||||
ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
|
||||
if (ret < 0)
|
||||
result = ret;
|
||||
if (ret != 4)
|
||||
val = 0x0;
|
||||
for (i = 0; status && (i < otp_close_nb); i++) {
|
||||
otp_close = get_otp_close_state(i);
|
||||
|
||||
ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
|
||||
if (ret < 0)
|
||||
result = ret;
|
||||
if (ret != 4)
|
||||
lock = BSEC_LOCK_ERROR;
|
||||
if (!otp_close->close_status_ops)
|
||||
continue;
|
||||
|
||||
mask = otp_close->mask_rd;
|
||||
word = otp_close->word;
|
||||
|
||||
ret = misc_read(dev, STM32_BSEC_OTP(word), &val, 4);
|
||||
if (ret < 0)
|
||||
result = ret;
|
||||
if (ret != 4)
|
||||
val = 0x0;
|
||||
|
||||
ret = misc_read(dev, STM32_BSEC_LOCK(word), &lock, 4);
|
||||
if (ret < 0)
|
||||
result = ret;
|
||||
if (ret != 4)
|
||||
lock = BSEC_LOCK_ERROR;
|
||||
|
||||
status = otp_close->close_status_ops(val, mask);
|
||||
tested_once = true;
|
||||
}
|
||||
|
||||
if (!tested_once)
|
||||
status = false;
|
||||
|
||||
mask = get_otp_close_mask();
|
||||
status = (val & mask) == mask;
|
||||
if (closed)
|
||||
*closed = status;
|
||||
if (print)
|
||||
@@ -185,7 +327,49 @@ static int read_close_status(struct udevice *dev, bool print, bool *closed)
|
||||
return result;
|
||||
}
|
||||
|
||||
static int fuse_key_value(struct udevice *dev, const struct stm32key *key, u32 addr, bool print)
|
||||
static int write_close_status(struct udevice *dev)
|
||||
{
|
||||
int i;
|
||||
u32 val, word, ret;
|
||||
const struct otp_close *otp_close = NULL;
|
||||
u32 otp_num = get_otp_close_state_nb();
|
||||
|
||||
for (i = 0; i < otp_num; i++) {
|
||||
otp_close = get_otp_close_state(i);
|
||||
val = otp_close->mask_wr;
|
||||
word = otp_close->word;
|
||||
ret = misc_write(dev, STM32_BSEC_OTP(word), &val, 4);
|
||||
if (ret != 4) {
|
||||
log_err("Error: can't update OTP %d\n", word);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int post_process_oem_key2(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
ret = misc_read(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4);
|
||||
if (ret != 4) {
|
||||
log_err("Error %d failed to read STM32MP25_OTP_BOOTROM_CONF8\n", ret);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
val |= STM32_OTP_STM32MP25X_OEM_KEY2_EN;
|
||||
ret = misc_write(dev, STM32_BSEC_OTP(STM32MP25_OTP_BOOTROM_CONF8), &val, 4);
|
||||
if (ret != 4) {
|
||||
log_err("Error %d failed to write OEM_KEY2_ENABLE\n", ret);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fuse_key_value(struct udevice *dev, const struct stm32key *key, unsigned long addr,
|
||||
bool print)
|
||||
{
|
||||
u32 word, val;
|
||||
int i, ret;
|
||||
@@ -229,7 +413,7 @@ static int confirm_prog(void)
|
||||
static void display_key_info(const struct stm32key *key)
|
||||
{
|
||||
printf("%s : %s\n", key->name, key->desc);
|
||||
printf("\tOTP%d..%d\n", key->start, key->start + key->size);
|
||||
printf("\tOTP%d..%d\n", key->start, key->start + key->size - 1);
|
||||
}
|
||||
|
||||
static int do_stm32key_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
@@ -272,7 +456,7 @@ static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *con
|
||||
{
|
||||
const struct stm32key *key;
|
||||
struct udevice *dev;
|
||||
u32 addr;
|
||||
unsigned long addr;
|
||||
int ret, i;
|
||||
int result;
|
||||
|
||||
@@ -310,7 +494,7 @@ static int do_stm32key_read(struct cmd_tbl *cmdtp, int flag, int argc, char *con
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
key = get_key(stm32key_index);
|
||||
printf("Read %s at 0x%08x\n", key->name, addr);
|
||||
printf("Read %s at 0x%08x\n", key->name, (u32)addr);
|
||||
read_key_value(key, addr);
|
||||
|
||||
return CMD_RET_SUCCESS;
|
||||
@@ -320,7 +504,7 @@ static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *con
|
||||
{
|
||||
const struct stm32key *key = get_key(stm32key_index);
|
||||
struct udevice *dev;
|
||||
u32 addr;
|
||||
unsigned long addr;
|
||||
int ret;
|
||||
bool yes = false, lock;
|
||||
|
||||
@@ -361,6 +545,13 @@ static int do_stm32key_fuse(struct cmd_tbl *cmdtp, int flag, int argc, char *con
|
||||
if (fuse_key_value(dev, key, addr, !yes))
|
||||
return CMD_RET_FAILURE;
|
||||
|
||||
if (key->post_process) {
|
||||
if (key->post_process(dev)) {
|
||||
printf("Error: %s for post process\n", key->name);
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
printf("%s updated !\n", key->name);
|
||||
|
||||
return CMD_RET_SUCCESS;
|
||||
@@ -371,7 +562,6 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co
|
||||
const struct stm32key *key;
|
||||
bool yes, lock, closed;
|
||||
struct udevice *dev;
|
||||
u32 val;
|
||||
int ret;
|
||||
|
||||
yes = false;
|
||||
@@ -407,12 +597,8 @@ static int do_stm32key_close(struct cmd_tbl *cmdtp, int flag, int argc, char *co
|
||||
if (!yes && !confirm_prog())
|
||||
return CMD_RET_FAILURE;
|
||||
|
||||
val = get_otp_close_mask();
|
||||
ret = misc_write(dev, STM32_BSEC_OTP(STM32_OTP_CLOSE_ID), &val, 4);
|
||||
if (ret != 4) {
|
||||
printf("Error: can't update OTP %d\n", STM32_OTP_CLOSE_ID);
|
||||
if (write_close_status(dev))
|
||||
return CMD_RET_FAILURE;
|
||||
}
|
||||
|
||||
printf("Device is closed !\n");
|
||||
|
||||
@@ -432,3 +618,25 @@ U_BOOT_CMD_WITH_SUBCMDS(stm32key, "Manage key on STM32", stm32key_help_text,
|
||||
U_BOOT_SUBCMD_MKENT(read, 2, 0, do_stm32key_read),
|
||||
U_BOOT_SUBCMD_MKENT(fuse, 3, 0, do_stm32key_fuse),
|
||||
U_BOOT_SUBCMD_MKENT(close, 2, 0, do_stm32key_close));
|
||||
|
||||
/*
|
||||
* Check the "closed" state in product life cycle, when product secrets have
|
||||
* been provisioned into the device, by SSP tools for example.
|
||||
* On closed devices, authentication is mandatory.
|
||||
*/
|
||||
bool stm32mp_is_closed(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
bool closed;
|
||||
int ret;
|
||||
|
||||
ret = get_misc_dev(&dev);
|
||||
if (ret)
|
||||
return false;
|
||||
|
||||
ret = read_close_status(dev, false, &closed);
|
||||
if (ret)
|
||||
return false;
|
||||
|
||||
return closed;
|
||||
}
|
||||
|
||||
@@ -27,6 +27,8 @@ config CMD_STM32PROG_USB
|
||||
config CMD_STM32PROG_SERIAL
|
||||
bool "support stm32prog over UART"
|
||||
depends on CMD_STM32PROG
|
||||
imply DISABLE_CONSOLE
|
||||
imply SILENT_CONSOLE
|
||||
default y
|
||||
help
|
||||
activate the command "stm32prog serial" for STM32MP soc family
|
||||
|
||||
@@ -13,6 +13,7 @@
|
||||
#include <part.h>
|
||||
#include <tee.h>
|
||||
#include <asm/arch/stm32mp1_smc.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <dm/uclass.h>
|
||||
@@ -1156,7 +1157,8 @@ static int create_gpt_partitions(struct stm32prog_data *data)
|
||||
|
||||
/* partition UUID */
|
||||
uuid_bin = NULL;
|
||||
if (!rootfs_found && !strcmp(part->name, "rootfs")) {
|
||||
if (!rootfs_found && (!strcmp(part->name, "rootfs") ||
|
||||
!strcmp(part->name, "rootfs-a"))) {
|
||||
mmc_id = part->dev_id;
|
||||
rootfs_found = true;
|
||||
if (mmc_id < ARRAY_SIZE(uuid_mmc))
|
||||
@@ -1357,7 +1359,7 @@ static int dfu_init_entities(struct stm32prog_data *data)
|
||||
|
||||
alt_nb = 1; /* number of virtual = CMD*/
|
||||
|
||||
if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP)) {
|
||||
if (IS_ENABLED(CONFIG_CMD_STM32PROG_OTP) && !stm32mp_is_closed()) {
|
||||
/* OTP_SIZE_SMC = 0 if SMC is not supported */
|
||||
otp_size = OTP_SIZE_SMC;
|
||||
/* check if PTA BSEC is supported */
|
||||
|
||||
32
arch/arm/mach-stm32mp/include/mach/etzpc.h
Normal file
32
arch/arm/mach-stm32mp/include/mach/etzpc.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#ifndef MACH_ETZPC_H
|
||||
#define MACH_ETZPC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/**
|
||||
* stm32_etzpc_check_access - Check ETZPC accesses for given device node
|
||||
*
|
||||
* @device_node Node of the device for which the accesses are checked
|
||||
*
|
||||
* @returns 0 on success (if access is granted), -EINVAL if access is denied.
|
||||
* Else, returns an appropriate negative ERRNO value
|
||||
*/
|
||||
int stm32_etzpc_check_access(ofnode device_node);
|
||||
|
||||
/**
|
||||
* stm32_etzpc_check_access_by_id - Check ETZPC accesses for given id
|
||||
*
|
||||
* @device_node Node of the device to get a reference on ETZPC
|
||||
* @id ID of the resource to check
|
||||
*
|
||||
* @returns 0 on success (if access is granted), -EINVAL if access is denied.
|
||||
* Else, returns an appropriate negative ERRNO value
|
||||
*/
|
||||
int stm32_etzpc_check_access_by_id(ofnode device_node, u32 id);
|
||||
|
||||
#endif /* MACH_ETZPC_H*/
|
||||
26
arch/arm/mach-stm32mp/include/mach/rif.h
Normal file
26
arch/arm/mach-stm32mp/include/mach/rif.h
Normal file
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#ifndef MACH_RIF_H
|
||||
#define MACH_RIF_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/**
|
||||
* stm32_rifsc_check_access - Check RIF accesses for given device node
|
||||
*
|
||||
* @device_node Node of the device for which the accesses are checked
|
||||
*/
|
||||
int stm32_rifsc_check_access(ofnode device_node);
|
||||
|
||||
/**
|
||||
* stm32_rifsc_check_access - Check RIF accesses for given id
|
||||
*
|
||||
* @device_node Node of the device to get a reference on RIFSC
|
||||
* @id ID of the resource to check
|
||||
*/
|
||||
int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id);
|
||||
|
||||
#endif /* MACH_RIF_H*/
|
||||
@@ -42,6 +42,9 @@ enum boot_device {
|
||||
|
||||
BOOT_FLASH_SPINAND = 0x70,
|
||||
BOOT_FLASH_SPINAND_1 = 0x71,
|
||||
|
||||
BOOT_FLASH_HYPERFLASH = 0x80,
|
||||
BOOT_FLASH_HYPERFLASH_1 = 0x81
|
||||
};
|
||||
|
||||
#define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
|
||||
@@ -158,8 +161,20 @@ enum forced_boot_mode {
|
||||
#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
|
||||
|
||||
#ifdef CONFIG_STM32MP25X
|
||||
#define STM32_USART2_BASE 0x400E0000
|
||||
#define STM32_USART3_BASE 0x400F0000
|
||||
#define STM32_UART4_BASE 0x40100000
|
||||
#define STM32_UART5_BASE 0x40110000
|
||||
#define STM32_USART6_BASE 0x40220000
|
||||
#define STM32_UART9_BASE 0x402C0000
|
||||
#define STM32_USART1_BASE 0x40330000
|
||||
#define STM32_UART7_BASE 0x40370000
|
||||
#define STM32_UART8_BASE 0x40380000
|
||||
#define STM32_RCC_BASE 0x44200000
|
||||
#define STM32_TAMP_BASE 0x46010000
|
||||
#define STM32_SDMMC1_BASE 0x48220000
|
||||
#define STM32_SDMMC2_BASE 0x48230000
|
||||
#define STM32_SDMMC3_BASE 0x48240000
|
||||
|
||||
#define STM32_DDR_BASE 0x80000000
|
||||
|
||||
@@ -197,6 +212,7 @@ enum forced_boot_mode {
|
||||
#ifdef CONFIG_STM32MP25X
|
||||
#define BSEC_OTP_SERIAL 5
|
||||
#define BSEC_OTP_RPN 9
|
||||
#define BSEC_OTP_REVID 102
|
||||
#define BSEC_OTP_PKG 122
|
||||
#define BSEC_OTP_BOARD 246
|
||||
#define BSEC_OTP_MAC 247
|
||||
|
||||
@@ -58,6 +58,7 @@ u32 get_cpu_type(void);
|
||||
/* return CPU_DEV constants */
|
||||
u32 get_cpu_dev(void);
|
||||
|
||||
/* Silicon revision = REV_ID[15:0] of Device Version */
|
||||
#define CPU_REV1 0x1000
|
||||
#define CPU_REV1_1 0x1001
|
||||
#define CPU_REV1_2 0x1003
|
||||
@@ -65,7 +66,15 @@ u32 get_cpu_dev(void);
|
||||
#define CPU_REV2_1 0x2001
|
||||
#define CPU_REV2_2 0x2003
|
||||
|
||||
/* return Silicon revision = REV_ID[15:0] of Device Version */
|
||||
/* OTP revision ID = 6 bits : 3 for Major / 3 for Minor */
|
||||
#define OTP_REVID_1 0b001000
|
||||
#define OTP_REVID_1_1 0b001001
|
||||
#define OTP_REVID_1_2 0b001010
|
||||
#define OTP_REVID_2 0b010000
|
||||
#define OTP_REVID_2_1 0b010001
|
||||
#define OTP_REVID_2_2 0b010010
|
||||
|
||||
/* return SoC revision = Silicon revision (STM32MP1) or OTP revision ID (STM32MP2)*/
|
||||
u32 get_cpu_rev(void);
|
||||
|
||||
/* Get Package options from OTP */
|
||||
@@ -80,9 +89,9 @@ u32 get_cpu_package(void);
|
||||
|
||||
/* package used for STM32MP25x */
|
||||
#define STM32MP25_PKG_CUSTOM 0
|
||||
#define STM32MP25_PKG_AL_TBGA361 3
|
||||
#define STM32MP25_PKG_AK_TBGA424 4
|
||||
#define STM32MP25_PKG_AI_TBGA436 5
|
||||
#define STM32MP25_PKG_AL_VFBGA361 1
|
||||
#define STM32MP25_PKG_AK_VFBGA424 3
|
||||
#define STM32MP25_PKG_AI_TFBGA436 5
|
||||
#define STM32MP25_PKG_UNKNOWN 7
|
||||
|
||||
/* Get SOC name */
|
||||
@@ -111,3 +120,10 @@ u32 get_otp(int index, int shift, int mask);
|
||||
|
||||
uintptr_t get_stm32mp_rom_api_table(void);
|
||||
uintptr_t get_stm32mp_bl2_dtb(void);
|
||||
|
||||
/* helper function: check "closed" state in product "Life Cycle" */
|
||||
#ifdef CONFIG_CMD_STM32KEY
|
||||
bool stm32mp_is_closed(void);
|
||||
#else
|
||||
static inline bool stm32mp_is_closed(void) { return false; }
|
||||
#endif
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
#
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += etzpc.o
|
||||
|
||||
obj-$(CONFIG_STM32MP13X) += stm32mp13x.o
|
||||
obj-$(CONFIG_STM32MP15X) += stm32mp15x.o
|
||||
|
||||
194
arch/arm/mach-stm32mp/stm32mp1/etzpc.c
Normal file
194
arch/arm/mach-stm32mp/stm32mp1/etzpc.c
Normal file
@@ -0,0 +1,194 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY UCLASS_NOP
|
||||
|
||||
#include <dm.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <dm/lists.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <mach/etzpc.h>
|
||||
|
||||
/* ETZPC peripheral as firewall bus */
|
||||
/* ETZPC registers */
|
||||
#define ETZPC_DECPROT 0x10
|
||||
#define ETZPC_HWCFGR 0x3F0
|
||||
|
||||
/* ETZPC miscellaneous */
|
||||
#define ETZPC_PROT_MASK GENMASK(1, 0)
|
||||
#define ETZPC_PROT_A7NS 0x3
|
||||
#define ETZPC_DECPROT_SHIFT 1
|
||||
|
||||
#define IDS_PER_DECPROT_REGS 16
|
||||
|
||||
#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8)
|
||||
#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16)
|
||||
|
||||
/*
|
||||
* struct stm32_etzpc_plat: Information about ETZPC device
|
||||
*
|
||||
* @base: Base address of ETZPC
|
||||
* @max_entries: Number of securable peripherals in ETZPC
|
||||
*/
|
||||
struct stm32_etzpc_plat {
|
||||
void *base;
|
||||
unsigned int max_entries;
|
||||
};
|
||||
|
||||
static int etzpc_parse_feature_domain(ofnode node, struct ofnode_phandle_args *args)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ofnode_parse_phandle_with_args(node, "access-controllers",
|
||||
"#access-controller-cells", 0,
|
||||
0, args);
|
||||
if (ret) {
|
||||
log_debug("failed to parse access-controller (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (args->args_count != 1) {
|
||||
log_debug("invalid domain args_count: %d\n", args->args_count);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int etzpc_check_access(void *base, u32 id)
|
||||
{
|
||||
u32 reg_offset, offset, sec_val;
|
||||
|
||||
/* Check access configuration, 16 peripherals per register */
|
||||
reg_offset = ETZPC_DECPROT + 0x4 * (id / IDS_PER_DECPROT_REGS);
|
||||
offset = (id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT;
|
||||
|
||||
/* Verify peripheral is non-secure and attributed to cortex A7 */
|
||||
sec_val = (readl(base + reg_offset) >> offset) & ETZPC_PROT_MASK;
|
||||
if (sec_val != ETZPC_PROT_A7NS) {
|
||||
log_debug("Invalid bus configuration: reg_offset %#x, value %d\n",
|
||||
reg_offset, sec_val);
|
||||
return -EACCES;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int stm32_etzpc_check_access_by_id(ofnode device_node, u32 id)
|
||||
{
|
||||
struct stm32_etzpc_plat *plat;
|
||||
struct ofnode_phandle_args args;
|
||||
struct udevice *dev;
|
||||
int err;
|
||||
|
||||
err = etzpc_parse_feature_domain(device_node, &args);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (id == -1U)
|
||||
id = args.args[0];
|
||||
|
||||
err = uclass_get_device_by_ofnode(UCLASS_NOP, args.node, &dev);
|
||||
if (err || dev->driver != DM_DRIVER_GET(stm32_etzpc)) {
|
||||
log_err("No device found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
plat = dev_get_plat(dev);
|
||||
|
||||
if (id >= plat->max_entries) {
|
||||
dev_err(dev, "Invalid sys bus ID for %s\n", ofnode_get_name(device_node));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return etzpc_check_access(plat->base, id);
|
||||
}
|
||||
|
||||
int stm32_etzpc_check_access(ofnode device_node)
|
||||
{
|
||||
return stm32_etzpc_check_access_by_id(device_node, -1U);
|
||||
}
|
||||
|
||||
static int stm32_etzpc_bind(struct udevice *dev)
|
||||
{
|
||||
struct stm32_etzpc_plat *plat = dev_get_plat(dev);
|
||||
struct ofnode_phandle_args args;
|
||||
u32 nb_per, nb_master;
|
||||
int ret = 0, err = 0;
|
||||
ofnode node, parent;
|
||||
|
||||
plat->base = dev_read_addr_ptr(dev);
|
||||
if (!plat->base) {
|
||||
dev_err(dev, "can't get registers base address\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
/* Get number of etzpc entries*/
|
||||
nb_per = FIELD_GET(ETZPC_HWCFGR_NUM_PER_SEC,
|
||||
readl(plat->base + ETZPC_HWCFGR));
|
||||
nb_master = FIELD_GET(ETZPC_HWCFGR_NUM_AHB_SEC,
|
||||
readl(plat->base + ETZPC_HWCFGR));
|
||||
plat->max_entries = nb_per + nb_master;
|
||||
|
||||
parent = dev_ofnode(dev);
|
||||
for (node = ofnode_first_subnode(parent);
|
||||
ofnode_valid(node);
|
||||
node = ofnode_next_subnode(node)) {
|
||||
const char *node_name = ofnode_get_name(node);
|
||||
|
||||
if (!ofnode_is_enabled(node))
|
||||
continue;
|
||||
|
||||
err = etzpc_parse_feature_domain(node, &args);
|
||||
if (err) {
|
||||
dev_err(dev, "%s failed to parse child on bus (%d)\n", node_name, err);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!ofnode_equal(args.node, parent)) {
|
||||
dev_err(dev, "%s phandle to %s\n",
|
||||
node_name, ofnode_get_name(args.node));
|
||||
continue;
|
||||
}
|
||||
|
||||
if (args.args[0] >= plat->max_entries) {
|
||||
dev_err(dev, "Invalid sys bus ID for %s\n", node_name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
err = etzpc_check_access(plat->base, args.args[0]);
|
||||
if (err) {
|
||||
dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err);
|
||||
continue;
|
||||
}
|
||||
|
||||
err = lists_bind_fdt(dev, node, NULL, NULL,
|
||||
gd->flags & GD_FLG_RELOC ? false : true);
|
||||
if (err) {
|
||||
ret = err;
|
||||
dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret);
|
||||
}
|
||||
}
|
||||
|
||||
if (ret)
|
||||
dev_err(dev, "Some child failed to bind (%d)\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct udevice_id stm32_etzpc_ids[] = {
|
||||
{ .compatible = "st,stm32-etzpc" },
|
||||
{},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stm32_etzpc) = {
|
||||
.name = "stm32_etzpc",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = stm32_etzpc_ids,
|
||||
.bind = stm32_etzpc_bind,
|
||||
.plat_auto = sizeof(struct stm32_etzpc_plat),
|
||||
};
|
||||
@@ -14,20 +14,6 @@
|
||||
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n))
|
||||
#define ETZPC_DECPROT_NB 6
|
||||
|
||||
#define DECPROT_MASK 0x03
|
||||
#define NB_PROT_PER_REG 0x10
|
||||
#define DECPROT_NB_BITS 2
|
||||
|
||||
#define DECPROT_SECURED 0x00
|
||||
#define DECPROT_WRITE_SECURE 0x01
|
||||
#define DECPROT_MCU_ISOLATION 0x02
|
||||
#define DECPROT_NON_SECURED 0x03
|
||||
|
||||
#define ETZPC_RESERVED 0xffffffff
|
||||
|
||||
#define STM32MP13_FDCAN_BASE 0x4400F000
|
||||
#define STM32MP13_ADC1_BASE 0x48003000
|
||||
#define STM32MP13_TSC_BASE 0x5000B000
|
||||
@@ -42,204 +28,6 @@
|
||||
#define STM32MP15_GPU_BASE 0x59000000
|
||||
#define STM32MP15_DSI_BASE 0x5a000000
|
||||
|
||||
static const u32 stm32mp13_ip_addr[] = {
|
||||
0x50025000, /* 0 VREFBUF APB3 */
|
||||
0x50021000, /* 1 LPTIM2 APB3 */
|
||||
0x50022000, /* 2 LPTIM3 APB3 */
|
||||
STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */
|
||||
STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */
|
||||
0x5A006000, /* 5 USBPHYCTRL APB4 */
|
||||
0x5A003000, /* 6 DDRCTRLPHY APB4 */
|
||||
ETZPC_RESERVED, /* 7 Reserved*/
|
||||
ETZPC_RESERVED, /* 8 Reserved*/
|
||||
ETZPC_RESERVED, /* 9 Reserved*/
|
||||
0x5C006000, /* 10 TZC APB5 */
|
||||
0x58001000, /* 11 MCE APB5 */
|
||||
0x5C000000, /* 12 IWDG1 APB5 */
|
||||
0x5C008000, /* 13 STGENC APB5 */
|
||||
ETZPC_RESERVED, /* 14 Reserved*/
|
||||
ETZPC_RESERVED, /* 15 Reserved*/
|
||||
0x4C000000, /* 16 USART1 APB6 */
|
||||
0x4C001000, /* 17 USART2 APB6 */
|
||||
0x4C002000, /* 18 SPI4 APB6 */
|
||||
0x4C003000, /* 19 SPI5 APB6 */
|
||||
0x4C004000, /* 20 I2C3 APB6 */
|
||||
0x4C005000, /* 21 I2C4 APB6 */
|
||||
0x4C006000, /* 22 I2C5 APB6 */
|
||||
0x4C007000, /* 23 TIM12 APB6 */
|
||||
0x4C008000, /* 24 TIM13 APB6 */
|
||||
0x4C009000, /* 25 TIM14 APB6 */
|
||||
0x4C00A000, /* 26 TIM15 APB6 */
|
||||
0x4C00B000, /* 27 TIM16 APB6 */
|
||||
0x4C00C000, /* 28 TIM17 APB6 */
|
||||
ETZPC_RESERVED, /* 29 Reserved*/
|
||||
ETZPC_RESERVED, /* 30 Reserved*/
|
||||
ETZPC_RESERVED, /* 31 Reserved*/
|
||||
STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */
|
||||
0x48004000, /* 33 ADC2 AHB2 */
|
||||
0x49000000, /* 34 OTG AHB2 */
|
||||
ETZPC_RESERVED, /* 35 Reserved*/
|
||||
ETZPC_RESERVED, /* 36 Reserved*/
|
||||
STM32MP13_TSC_BASE, /* 37 TSC AHB4 */
|
||||
ETZPC_RESERVED, /* 38 Reserved*/
|
||||
ETZPC_RESERVED, /* 39 Reserved*/
|
||||
0x54004000, /* 40 RNG AHB5 */
|
||||
0x54003000, /* 41 HASH AHB5 */
|
||||
STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */
|
||||
0x54005000, /* 43 SAES AHB5 */
|
||||
0x54006000, /* 44 PKA AHB5 */
|
||||
0x54000000, /* 45 BKPSRAM AHB5 */
|
||||
ETZPC_RESERVED, /* 46 Reserved*/
|
||||
ETZPC_RESERVED, /* 47 Reserved*/
|
||||
0x5800A000, /* 48 ETH1 AHB6 */
|
||||
STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */
|
||||
0x58005000, /* 50 SDMMC1 AHB6 */
|
||||
0x58007000, /* 51 SDMMC2 AHB6 */
|
||||
ETZPC_RESERVED, /* 52 Reserved*/
|
||||
ETZPC_RESERVED, /* 53 Reserved*/
|
||||
0x58002000, /* 54 FMC AHB6 */
|
||||
0x58003000, /* 55 QSPI AHB6 */
|
||||
ETZPC_RESERVED, /* 56 Reserved*/
|
||||
ETZPC_RESERVED, /* 57 Reserved*/
|
||||
ETZPC_RESERVED, /* 58 Reserved*/
|
||||
ETZPC_RESERVED, /* 59 Reserved*/
|
||||
0x30000000, /* 60 SRAM1 MLAHB */
|
||||
0x30004000, /* 61 SRAM2 MLAHB */
|
||||
0x30006000, /* 62 SRAM3 MLAHB */
|
||||
ETZPC_RESERVED, /* 63 Reserved*/
|
||||
ETZPC_RESERVED, /* 64 Reserved*/
|
||||
ETZPC_RESERVED, /* 65 Reserved*/
|
||||
ETZPC_RESERVED, /* 66 Reserved*/
|
||||
ETZPC_RESERVED, /* 67 Reserved*/
|
||||
ETZPC_RESERVED, /* 68 Reserved*/
|
||||
ETZPC_RESERVED, /* 69 Reserved*/
|
||||
ETZPC_RESERVED, /* 70 Reserved*/
|
||||
ETZPC_RESERVED, /* 71 Reserved*/
|
||||
ETZPC_RESERVED, /* 72 Reserved*/
|
||||
ETZPC_RESERVED, /* 73 Reserved*/
|
||||
ETZPC_RESERVED, /* 74 Reserved*/
|
||||
ETZPC_RESERVED, /* 75 Reserved*/
|
||||
ETZPC_RESERVED, /* 76 Reserved*/
|
||||
ETZPC_RESERVED, /* 77 Reserved*/
|
||||
ETZPC_RESERVED, /* 78 Reserved*/
|
||||
ETZPC_RESERVED, /* 79 Reserved*/
|
||||
ETZPC_RESERVED, /* 80 Reserved*/
|
||||
ETZPC_RESERVED, /* 81 Reserved*/
|
||||
ETZPC_RESERVED, /* 82 Reserved*/
|
||||
ETZPC_RESERVED, /* 83 Reserved*/
|
||||
ETZPC_RESERVED, /* 84 Reserved*/
|
||||
ETZPC_RESERVED, /* 85 Reserved*/
|
||||
ETZPC_RESERVED, /* 86 Reserved*/
|
||||
ETZPC_RESERVED, /* 87 Reserved*/
|
||||
ETZPC_RESERVED, /* 88 Reserved*/
|
||||
ETZPC_RESERVED, /* 89 Reserved*/
|
||||
ETZPC_RESERVED, /* 90 Reserved*/
|
||||
ETZPC_RESERVED, /* 91 Reserved*/
|
||||
ETZPC_RESERVED, /* 92 Reserved*/
|
||||
ETZPC_RESERVED, /* 93 Reserved*/
|
||||
ETZPC_RESERVED, /* 94 Reserved*/
|
||||
ETZPC_RESERVED, /* 95 Reserved*/
|
||||
};
|
||||
|
||||
static const u32 stm32mp15_ip_addr[] = {
|
||||
0x5c008000, /* 00 stgenc */
|
||||
0x54000000, /* 01 bkpsram */
|
||||
0x5c003000, /* 02 iwdg1 */
|
||||
0x5c000000, /* 03 usart1 */
|
||||
0x5c001000, /* 04 spi6 */
|
||||
0x5c002000, /* 05 i2c4 */
|
||||
ETZPC_RESERVED, /* 06 reserved */
|
||||
0x54003000, /* 07 rng1 */
|
||||
0x54002000, /* 08 hash1 */
|
||||
STM32MP15_CRYP1_BASE, /* 09 cryp1 */
|
||||
0x5a003000, /* 0A ddrctrl */
|
||||
0x5a004000, /* 0B ddrphyc */
|
||||
0x5c009000, /* 0C i2c6 */
|
||||
ETZPC_RESERVED, /* 0D reserved */
|
||||
ETZPC_RESERVED, /* 0E reserved */
|
||||
ETZPC_RESERVED, /* 0F reserved */
|
||||
0x40000000, /* 10 tim2 */
|
||||
0x40001000, /* 11 tim3 */
|
||||
0x40002000, /* 12 tim4 */
|
||||
0x40003000, /* 13 tim5 */
|
||||
0x40004000, /* 14 tim6 */
|
||||
0x40005000, /* 15 tim7 */
|
||||
0x40006000, /* 16 tim12 */
|
||||
0x40007000, /* 17 tim13 */
|
||||
0x40008000, /* 18 tim14 */
|
||||
0x40009000, /* 19 lptim1 */
|
||||
0x4000a000, /* 1A wwdg1 */
|
||||
0x4000b000, /* 1B spi2 */
|
||||
0x4000c000, /* 1C spi3 */
|
||||
0x4000d000, /* 1D spdifrx */
|
||||
0x4000e000, /* 1E usart2 */
|
||||
0x4000f000, /* 1F usart3 */
|
||||
0x40010000, /* 20 uart4 */
|
||||
0x40011000, /* 21 uart5 */
|
||||
0x40012000, /* 22 i2c1 */
|
||||
0x40013000, /* 23 i2c2 */
|
||||
0x40014000, /* 24 i2c3 */
|
||||
0x40015000, /* 25 i2c5 */
|
||||
0x40016000, /* 26 cec */
|
||||
0x40017000, /* 27 dac */
|
||||
0x40018000, /* 28 uart7 */
|
||||
0x40019000, /* 29 uart8 */
|
||||
ETZPC_RESERVED, /* 2A reserved */
|
||||
ETZPC_RESERVED, /* 2B reserved */
|
||||
0x4001c000, /* 2C mdios */
|
||||
ETZPC_RESERVED, /* 2D reserved */
|
||||
ETZPC_RESERVED, /* 2E reserved */
|
||||
ETZPC_RESERVED, /* 2F reserved */
|
||||
0x44000000, /* 30 tim1 */
|
||||
0x44001000, /* 31 tim8 */
|
||||
ETZPC_RESERVED, /* 32 reserved */
|
||||
0x44003000, /* 33 usart6 */
|
||||
0x44004000, /* 34 spi1 */
|
||||
0x44005000, /* 35 spi4 */
|
||||
0x44006000, /* 36 tim15 */
|
||||
0x44007000, /* 37 tim16 */
|
||||
0x44008000, /* 38 tim17 */
|
||||
0x44009000, /* 39 spi5 */
|
||||
0x4400a000, /* 3A sai1 */
|
||||
0x4400b000, /* 3B sai2 */
|
||||
0x4400c000, /* 3C sai3 */
|
||||
0x4400d000, /* 3D dfsdm */
|
||||
STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */
|
||||
ETZPC_RESERVED, /* 3F reserved */
|
||||
0x50021000, /* 40 lptim2 */
|
||||
0x50022000, /* 41 lptim3 */
|
||||
0x50023000, /* 42 lptim4 */
|
||||
0x50024000, /* 43 lptim5 */
|
||||
0x50027000, /* 44 sai4 */
|
||||
0x50025000, /* 45 vrefbuf */
|
||||
0x4c006000, /* 46 dcmi */
|
||||
0x4c004000, /* 47 crc2 */
|
||||
0x48003000, /* 48 adc */
|
||||
0x4c002000, /* 49 hash2 */
|
||||
0x4c003000, /* 4A rng2 */
|
||||
STM32MP15_CRYP2_BASE, /* 4B cryp2 */
|
||||
ETZPC_RESERVED, /* 4C reserved */
|
||||
ETZPC_RESERVED, /* 4D reserved */
|
||||
ETZPC_RESERVED, /* 4E reserved */
|
||||
ETZPC_RESERVED, /* 4F reserved */
|
||||
ETZPC_RESERVED, /* 50 sram1 */
|
||||
ETZPC_RESERVED, /* 51 sram2 */
|
||||
ETZPC_RESERVED, /* 52 sram3 */
|
||||
ETZPC_RESERVED, /* 53 sram4 */
|
||||
ETZPC_RESERVED, /* 54 retram */
|
||||
0x49000000, /* 55 otg */
|
||||
0x48004000, /* 56 sdmmc3 */
|
||||
0x48005000, /* 57 dlybsd3 */
|
||||
0x48000000, /* 58 dma1 */
|
||||
0x48001000, /* 59 dma2 */
|
||||
0x48002000, /* 5A dmamux */
|
||||
0x58002000, /* 5B fmc */
|
||||
0x58003000, /* 5C qspi */
|
||||
0x58004000, /* 5D dlybq */
|
||||
0x5800a000, /* 5E eth */
|
||||
ETZPC_RESERVED, /* 5F reserved */
|
||||
};
|
||||
|
||||
/* fdt helper */
|
||||
static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
|
||||
{
|
||||
@@ -263,46 +51,6 @@ static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr)
|
||||
return false;
|
||||
}
|
||||
|
||||
static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node)
|
||||
{
|
||||
const u32 *array;
|
||||
int array_size, i;
|
||||
int offset, shift;
|
||||
u32 addr, status, decprot[ETZPC_DECPROT_NB];
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP13X)) {
|
||||
array = stm32mp13_ip_addr;
|
||||
array_size = ARRAY_SIZE(stm32mp13_ip_addr);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_STM32MP15X)) {
|
||||
array = stm32mp15_ip_addr;
|
||||
array_size = ARRAY_SIZE(stm32mp15_ip_addr);
|
||||
}
|
||||
|
||||
for (i = 0; i < ETZPC_DECPROT_NB; i++)
|
||||
decprot[i] = readl(ETZPC_DECPROT(i));
|
||||
|
||||
for (i = 0; i < array_size; i++) {
|
||||
offset = i / NB_PROT_PER_REG;
|
||||
shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS;
|
||||
status = (decprot[offset] >> shift) & DECPROT_MASK;
|
||||
addr = array[i];
|
||||
|
||||
log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status);
|
||||
|
||||
if (addr == ETZPC_RESERVED ||
|
||||
status == DECPROT_NON_SECURED)
|
||||
continue;
|
||||
|
||||
if (fdt_disable_subnode_by_address(fdt, soc_node, addr))
|
||||
log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n",
|
||||
addr, i, status);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* deactivate all the cpu except core 0 */
|
||||
static void stm32_fdt_fixup_cpu(void *blob, char *name)
|
||||
{
|
||||
@@ -481,12 +229,6 @@ int ft_system_setup(void *blob, struct bd_info *bd)
|
||||
if (soc < 0)
|
||||
return soc;
|
||||
|
||||
if (CONFIG_IS_ENABLED(STM32_ETZPC)) {
|
||||
ret = stm32_fdt_fixup_etzpc(blob, soc);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* MPUs Part Numbers and name*/
|
||||
cpu = get_cpu_type();
|
||||
get_soc_name(name);
|
||||
|
||||
@@ -5,5 +5,6 @@
|
||||
|
||||
obj-y += cpu.o
|
||||
obj-y += arm64-mmu.o
|
||||
obj-y += rifsc.o
|
||||
obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o
|
||||
obj-$(CONFIG_STM32MP25X) += stm32mp25x.o
|
||||
|
||||
@@ -24,7 +24,7 @@
|
||||
* early TLB into the .data section so that it not get cleared
|
||||
* with 16kB alignment
|
||||
*/
|
||||
#define EARLY_TLB_SIZE 0xA000
|
||||
#define EARLY_TLB_SIZE 0x10000
|
||||
u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000);
|
||||
|
||||
/*
|
||||
@@ -55,6 +55,19 @@ int arch_cpu_init(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mach_cpu_init(void)
|
||||
{
|
||||
u32 boot_mode;
|
||||
|
||||
boot_mode = get_bootmode();
|
||||
|
||||
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
|
||||
(boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
|
||||
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void enable_caches(void)
|
||||
{
|
||||
/* deactivate the data cache, early enabled in arch_cpu_init() */
|
||||
@@ -67,14 +80,6 @@ void enable_caches(void)
|
||||
dcache_enable();
|
||||
}
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
setup_serial_number();
|
||||
setup_mac_address();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Force data-section, as .bss will not be valid
|
||||
* when save_boot_params is invoked.
|
||||
@@ -97,3 +102,150 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
|
||||
|
||||
save_boot_params_ret();
|
||||
}
|
||||
|
||||
u32 get_bootmode(void)
|
||||
{
|
||||
/* read bootmode from TAMP backup register */
|
||||
return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
|
||||
TAMP_BOOT_MODE_SHIFT;
|
||||
}
|
||||
|
||||
static void setup_boot_mode(void)
|
||||
{
|
||||
const u32 serial_addr[] = {
|
||||
STM32_USART1_BASE,
|
||||
STM32_USART2_BASE,
|
||||
STM32_USART3_BASE,
|
||||
STM32_UART4_BASE,
|
||||
STM32_UART5_BASE,
|
||||
STM32_USART6_BASE,
|
||||
STM32_UART7_BASE,
|
||||
STM32_UART8_BASE,
|
||||
STM32_UART9_BASE
|
||||
};
|
||||
const u32 sdmmc_addr[] = {
|
||||
STM32_SDMMC1_BASE,
|
||||
STM32_SDMMC2_BASE,
|
||||
STM32_SDMMC3_BASE
|
||||
};
|
||||
char cmd[60];
|
||||
u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
|
||||
u32 boot_mode =
|
||||
(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
|
||||
unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
|
||||
u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
|
||||
struct udevice *dev;
|
||||
|
||||
log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
|
||||
__func__, boot_ctx, boot_mode, instance, forced_mode);
|
||||
switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
|
||||
case BOOT_SERIAL_UART:
|
||||
if (instance > ARRAY_SIZE(serial_addr))
|
||||
break;
|
||||
/* serial : search associated node in devicetree */
|
||||
sprintf(cmd, "serial@%x", serial_addr[instance]);
|
||||
if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
|
||||
/* restore console on error */
|
||||
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
|
||||
gd->flags &= ~(GD_FLG_SILENT |
|
||||
GD_FLG_DISABLE_CONSOLE);
|
||||
log_err("uart%d = %s not found in device tree!\n",
|
||||
instance + 1, cmd);
|
||||
break;
|
||||
}
|
||||
sprintf(cmd, "%d", dev_seq(dev));
|
||||
env_set("boot_device", "serial");
|
||||
env_set("boot_instance", cmd);
|
||||
|
||||
/* restore console on uart when not used */
|
||||
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
|
||||
gd->flags &= ~(GD_FLG_SILENT |
|
||||
GD_FLG_DISABLE_CONSOLE);
|
||||
log_info("serial boot with console enabled!\n");
|
||||
}
|
||||
break;
|
||||
case BOOT_SERIAL_USB:
|
||||
env_set("boot_device", "usb");
|
||||
env_set("boot_instance", "0");
|
||||
break;
|
||||
case BOOT_FLASH_SD:
|
||||
case BOOT_FLASH_EMMC:
|
||||
if (instance > ARRAY_SIZE(sdmmc_addr))
|
||||
break;
|
||||
/* search associated sdmmc node in devicetree */
|
||||
sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
|
||||
if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
|
||||
printf("mmc%d = %s not found in device tree!\n",
|
||||
instance, cmd);
|
||||
break;
|
||||
}
|
||||
sprintf(cmd, "%d", dev_seq(dev));
|
||||
env_set("boot_device", "mmc");
|
||||
env_set("boot_instance", cmd);
|
||||
break;
|
||||
case BOOT_FLASH_NAND:
|
||||
env_set("boot_device", "nand");
|
||||
env_set("boot_instance", "0");
|
||||
break;
|
||||
case BOOT_FLASH_SPINAND:
|
||||
env_set("boot_device", "spi-nand");
|
||||
env_set("boot_instance", "0");
|
||||
break;
|
||||
case BOOT_FLASH_NOR:
|
||||
env_set("boot_device", "nor");
|
||||
if (IS_ENABLED(CONFIG_SYS_MAX_FLASH_BANKS))
|
||||
sprintf(cmd, "%d", CONFIG_SYS_MAX_FLASH_BANKS);
|
||||
else
|
||||
sprintf(cmd, "%d", 0);
|
||||
env_set("boot_instance", cmd);
|
||||
break;
|
||||
case BOOT_FLASH_HYPERFLASH:
|
||||
env_set("boot_device", "nor");
|
||||
env_set("boot_instance", "0");
|
||||
break;
|
||||
default:
|
||||
env_set("boot_device", "invalid");
|
||||
env_set("boot_instance", "");
|
||||
log_err("unexpected boot mode = %x\n", boot_mode);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (forced_mode) {
|
||||
case BOOT_FASTBOOT:
|
||||
log_info("Enter fastboot!\n");
|
||||
env_set("preboot", "env set preboot; fastboot 0");
|
||||
break;
|
||||
case BOOT_STM32PROG:
|
||||
env_set("boot_device", "usb");
|
||||
env_set("boot_instance", "0");
|
||||
break;
|
||||
case BOOT_UMS_MMC0:
|
||||
case BOOT_UMS_MMC1:
|
||||
case BOOT_UMS_MMC2:
|
||||
log_info("Enter UMS!\n");
|
||||
instance = forced_mode - BOOT_UMS_MMC0;
|
||||
sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
|
||||
env_set("preboot", cmd);
|
||||
break;
|
||||
case BOOT_RECOVERY:
|
||||
env_set("preboot", "env set preboot; run altbootcmd");
|
||||
break;
|
||||
case BOOT_NORMAL:
|
||||
break;
|
||||
default:
|
||||
log_debug("unexpected forced boot mode = %x\n", forced_mode);
|
||||
break;
|
||||
}
|
||||
|
||||
/* clear TAMP for next reboot */
|
||||
clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
|
||||
}
|
||||
|
||||
int arch_misc_init(void)
|
||||
{
|
||||
setup_boot_mode();
|
||||
setup_serial_number();
|
||||
setup_mac_address();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
364
arch/arm/mach-stm32mp/stm32mp2/rifsc.c
Normal file
364
arch/arm/mach-stm32mp/stm32mp2/rifsc.c
Normal file
@@ -0,0 +1,364 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
|
||||
/*
|
||||
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY UCLASS_NOP
|
||||
|
||||
#include <dm.h>
|
||||
#include <asm/io.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/device_compat.h>
|
||||
#include <dm/lists.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <mach/rif.h>
|
||||
|
||||
/* RIFSC offset register */
|
||||
#define RIFSC_RISC_SECCFGR0(id) (0x10 + 0x4 * (id))
|
||||
#define RIFSC_RISC_PER0_CIDCFGR(id) (0x100 + 0x8 * (id))
|
||||
#define RIFSC_RISC_PER0_SEMCR(id) (0x104 + 0x8 * (id))
|
||||
|
||||
/*
|
||||
* SEMCR register
|
||||
*/
|
||||
#define SEMCR_MUTEX BIT(0)
|
||||
|
||||
/* RIFSC miscellaneous */
|
||||
#define RIFSC_RISC_SCID_MASK GENMASK(6, 4)
|
||||
#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16)
|
||||
|
||||
#define IDS_PER_RISC_SEC_PRIV_REGS 32
|
||||
|
||||
/*
|
||||
* CIDCFGR register fields
|
||||
*/
|
||||
#define CIDCFGR_CFEN BIT(0)
|
||||
#define CIDCFGR_SEMEN BIT(1)
|
||||
|
||||
#define SEMWL_SHIFT 16
|
||||
|
||||
#define STM32MP25_RIFSC_ENTRIES 178
|
||||
|
||||
/* Compartiment IDs */
|
||||
#define RIF_CID0 0x0
|
||||
#define RIF_CID1 0x1
|
||||
|
||||
/*
|
||||
* struct stm32_rifsc_plat: Information about RIFSC device
|
||||
*
|
||||
* @base: Base address of RIFSC
|
||||
*/
|
||||
struct stm32_rifsc_plat {
|
||||
void *base;
|
||||
};
|
||||
|
||||
/*
|
||||
* struct stm32_rifsc_child_plat: Information about each child
|
||||
*
|
||||
* @domain_id: Domain id
|
||||
*/
|
||||
struct stm32_rifsc_child_plat {
|
||||
u32 domain_id;
|
||||
};
|
||||
|
||||
static bool stm32_rif_is_semaphore_available(void *base, u32 id)
|
||||
{
|
||||
void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
|
||||
|
||||
return !(readl(addr) & SEMCR_MUTEX);
|
||||
}
|
||||
|
||||
static int stm32_rif_acquire_semaphore(void *base, u32 id)
|
||||
{
|
||||
void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
|
||||
|
||||
/* Check that the semaphore is available */
|
||||
if (!stm32_rif_is_semaphore_available(base, id))
|
||||
return -EACCES;
|
||||
|
||||
setbits_le32(addr, SEMCR_MUTEX);
|
||||
|
||||
/* Check that CID1 has the semaphore */
|
||||
if (stm32_rif_is_semaphore_available(base, id) ||
|
||||
FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1))
|
||||
return -EACCES;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_rif_release_semaphore(void *base, u32 id)
|
||||
{
|
||||
void *addr = base + RIFSC_RISC_PER0_SEMCR(id);
|
||||
|
||||
if (stm32_rif_is_semaphore_available(base, id))
|
||||
return 0;
|
||||
|
||||
clrbits_le32(addr, SEMCR_MUTEX);
|
||||
|
||||
/* Ok if another compartment takes the semaphore before the check */
|
||||
if (!stm32_rif_is_semaphore_available(base, id) &&
|
||||
FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) == RIF_CID1))
|
||||
return -EACCES;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rifsc_parse_access_controller(ofnode node, struct ofnode_phandle_args *args)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ofnode_parse_phandle_with_args(node, "access-controllers",
|
||||
"#access-controller-cells", 0,
|
||||
0, args);
|
||||
if (ret) {
|
||||
log_debug("failed to parse access-controller (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (args->args_count != 1) {
|
||||
log_debug("invalid domain args_count: %d\n", args->args_count);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (args->args[0] >= STM32MP25_RIFSC_ENTRIES) {
|
||||
log_err("Invalid sys bus ID for %s\n", ofnode_get_name(node));
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rifsc_check_access(void *base, u32 id)
|
||||
{
|
||||
u32 reg_offset, reg_id, sec_reg_value, cid_reg_value, sem_reg_value;
|
||||
|
||||
/*
|
||||
* RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for
|
||||
* 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register
|
||||
* per peripheral
|
||||
*/
|
||||
reg_id = id / IDS_PER_RISC_SEC_PRIV_REGS;
|
||||
reg_offset = id % IDS_PER_RISC_SEC_PRIV_REGS;
|
||||
sec_reg_value = readl(base + RIFSC_RISC_SECCFGR0(reg_id));
|
||||
cid_reg_value = readl(base + RIFSC_RISC_PER0_CIDCFGR(id));
|
||||
sem_reg_value = readl(base + RIFSC_RISC_PER0_SEMCR(id));
|
||||
|
||||
/*
|
||||
* First check conditions for semaphore mode, which doesn't take into
|
||||
* account static CID.
|
||||
*/
|
||||
if (cid_reg_value & CIDCFGR_SEMEN)
|
||||
goto skip_cid_check;
|
||||
|
||||
/*
|
||||
* Skip cid check if CID filtering isn't enabled or filtering is enabled on CID0, which
|
||||
* corresponds to whatever CID.
|
||||
*/
|
||||
if (!(cid_reg_value & CIDCFGR_CFEN) ||
|
||||
FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0)
|
||||
goto skip_cid_check;
|
||||
|
||||
/* Coherency check with the CID configuration */
|
||||
if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) {
|
||||
log_debug("Invalid CID configuration for peripheral %d\n", id);
|
||||
return -EACCES;
|
||||
}
|
||||
|
||||
/* Check semaphore accesses */
|
||||
if (cid_reg_value & CIDCFGR_SEMEN) {
|
||||
if (!(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
|
||||
log_debug("Not in semaphore whitelist for peripheral %d\n", id);
|
||||
return -EACCES;
|
||||
}
|
||||
if (!stm32_rif_is_semaphore_available(base, id) &&
|
||||
!(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & BIT(RIF_CID1))) {
|
||||
log_debug("Semaphore unavailable for peripheral %d\n", id);
|
||||
return -EACCES;
|
||||
}
|
||||
}
|
||||
|
||||
skip_cid_check:
|
||||
/* Check security configuration */
|
||||
if (sec_reg_value & BIT(reg_offset)) {
|
||||
log_debug("Invalid security configuration for peripheral %d\n", id);
|
||||
return -EACCES;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id)
|
||||
{
|
||||
struct ofnode_phandle_args args;
|
||||
int err;
|
||||
|
||||
if (id >= STM32MP25_RIFSC_ENTRIES)
|
||||
return -EINVAL;
|
||||
|
||||
err = rifsc_parse_access_controller(device_node, &args);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return rifsc_check_access((void *)ofnode_get_addr(args.node), id);
|
||||
}
|
||||
|
||||
int stm32_rifsc_check_access(ofnode device_node)
|
||||
{
|
||||
struct ofnode_phandle_args args;
|
||||
int err;
|
||||
|
||||
err = rifsc_parse_access_controller(device_node, &args);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return rifsc_check_access((void *)ofnode_get_addr(args.node), args.args[0]);
|
||||
}
|
||||
|
||||
static int stm32_rifsc_child_pre_probe(struct udevice *dev)
|
||||
{
|
||||
struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent);
|
||||
struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
|
||||
u32 cid_reg_value;
|
||||
int err;
|
||||
u32 id = child_plat->domain_id;
|
||||
|
||||
cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id));
|
||||
|
||||
/*
|
||||
* If the peripheral is in semaphore mode, take the semaphore so that
|
||||
* the CID1 has the ownership.
|
||||
*/
|
||||
if (cid_reg_value & CIDCFGR_SEMEN &&
|
||||
(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
|
||||
err = stm32_rif_acquire_semaphore(plat->base, id);
|
||||
if (err) {
|
||||
dev_err(dev, "Couldn't acquire RIF semaphore for peripheral %d (%d)\n",
|
||||
id, err);
|
||||
return err;
|
||||
}
|
||||
dev_dbg(dev, "Acquiring semaphore for peripheral %d\n", id);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_rifsc_child_post_remove(struct udevice *dev)
|
||||
{
|
||||
struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent);
|
||||
struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
|
||||
u32 cid_reg_value;
|
||||
int err;
|
||||
u32 id = child_plat->domain_id;
|
||||
|
||||
cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id));
|
||||
|
||||
/*
|
||||
* If the peripheral is in semaphore mode, release the semaphore so that
|
||||
* there's no ownership.
|
||||
*/
|
||||
if (cid_reg_value & CIDCFGR_SEMEN &&
|
||||
(FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) {
|
||||
err = stm32_rif_release_semaphore(plat->base, id);
|
||||
if (err)
|
||||
dev_err(dev, "Couldn't release rif semaphore for peripheral %d (%d)\n",
|
||||
id, err);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_rifsc_child_post_bind(struct udevice *dev)
|
||||
{
|
||||
struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev);
|
||||
struct ofnode_phandle_args args;
|
||||
int ret;
|
||||
|
||||
if (!dev_has_ofnode(dev))
|
||||
return -EPERM;
|
||||
|
||||
ret = rifsc_parse_access_controller(dev_ofnode(dev), &args);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
child_plat->domain_id = args.args[0];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_rifsc_bind(struct udevice *dev)
|
||||
{
|
||||
struct stm32_rifsc_plat *plat = dev_get_plat(dev);
|
||||
struct ofnode_phandle_args args;
|
||||
int ret = 0, err = 0;
|
||||
ofnode node;
|
||||
|
||||
plat->base = dev_read_addr_ptr(dev);
|
||||
if (!plat->base) {
|
||||
dev_err(dev, "can't get registers base address\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
for (node = ofnode_first_subnode(dev_ofnode(dev));
|
||||
ofnode_valid(node);
|
||||
node = ofnode_next_subnode(node)) {
|
||||
const char *node_name = ofnode_get_name(node);
|
||||
|
||||
if (!ofnode_is_enabled(node))
|
||||
continue;
|
||||
|
||||
err = rifsc_parse_access_controller(node, &args);
|
||||
if (err) {
|
||||
dev_dbg(dev, "%s failed to parse child on bus (%d)\n", node_name, err);
|
||||
continue;
|
||||
}
|
||||
|
||||
err = rifsc_check_access(plat->base, args.args[0]);
|
||||
if (err) {
|
||||
dev_info(dev, "%s not allowed on bus (%d)\n", node_name, err);
|
||||
continue;
|
||||
}
|
||||
|
||||
err = lists_bind_fdt(dev, node, NULL, NULL,
|
||||
gd->flags & GD_FLG_RELOC ? false : true);
|
||||
if (err && !ret) {
|
||||
ret = err;
|
||||
dev_err(dev, "%s failed to bind on bus (%d)\n", node_name, ret);
|
||||
}
|
||||
}
|
||||
|
||||
if (ret)
|
||||
dev_err(dev, "Some child failed to bind (%d)\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_rifsc_remove(struct udevice *bus)
|
||||
{
|
||||
struct udevice *dev;
|
||||
|
||||
/* Deactivate all child devices not yet removed */
|
||||
for (device_find_first_child(bus, &dev); dev; device_find_next_child(&dev))
|
||||
if (device_active(dev))
|
||||
stm32_rifsc_child_post_remove(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id stm32_rifsc_ids[] = {
|
||||
{ .compatible = "st,stm32mp25-rifsc" },
|
||||
{},
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stm32_rifsc) = {
|
||||
.name = "stm32_rifsc",
|
||||
.id = UCLASS_NOP,
|
||||
.of_match = stm32_rifsc_ids,
|
||||
.bind = stm32_rifsc_bind,
|
||||
.remove = stm32_rifsc_remove,
|
||||
.child_post_bind = stm32_rifsc_child_post_bind,
|
||||
.child_pre_probe = stm32_rifsc_child_pre_probe,
|
||||
.child_post_remove = stm32_rifsc_child_post_remove,
|
||||
.plat_auto = sizeof(struct stm32_rifsc_plat),
|
||||
.per_child_plat_auto = sizeof(struct stm32_rifsc_child_plat),
|
||||
.flags = DM_FLAG_OS_PREPARE,
|
||||
};
|
||||
@@ -15,8 +15,10 @@
|
||||
#define SYSCFG_DEVICEID_OFFSET 0x6400
|
||||
#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0)
|
||||
#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0
|
||||
#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16)
|
||||
#define SYSCFG_DEVICEID_REV_ID_SHIFT 16
|
||||
|
||||
/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/
|
||||
#define REVID_SHIFT 0
|
||||
#define REVID_MASK GENMASK(5, 0)
|
||||
|
||||
/* Device Part Number (RPN) = OTP9 */
|
||||
#define RPN_SHIFT 0
|
||||
@@ -24,8 +26,8 @@
|
||||
|
||||
/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines
|
||||
* - 000: Custom package
|
||||
* - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm
|
||||
* - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm
|
||||
* - 001: VFBGA361 => AL = 10x10, 361 balls pith 0.5mm
|
||||
* - 011: VFBGA424 => AK = 14x14, 424 balls pith 0.5mm
|
||||
* - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm
|
||||
* - others: Reserved
|
||||
*/
|
||||
@@ -46,7 +48,7 @@ u32 get_cpu_dev(void)
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT;
|
||||
return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK);
|
||||
}
|
||||
|
||||
/* Get Device Part Number (RPN) from OTP */
|
||||
@@ -164,12 +166,21 @@ void get_soc_name(char name[SOC_NAME_SIZE])
|
||||
}
|
||||
/* REVISION */
|
||||
switch (get_cpu_rev()) {
|
||||
case CPU_REV1:
|
||||
case OTP_REVID_1:
|
||||
cpu_r = "A";
|
||||
break;
|
||||
case CPU_REV2:
|
||||
case OTP_REVID_1_1:
|
||||
cpu_r = "Z";
|
||||
break;
|
||||
case OTP_REVID_2:
|
||||
cpu_r = "B";
|
||||
break;
|
||||
case OTP_REVID_2_1:
|
||||
cpu_r = "Y";
|
||||
break;
|
||||
case OTP_REVID_2_2:
|
||||
cpu_r = "X";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@@ -178,13 +189,13 @@ void get_soc_name(char name[SOC_NAME_SIZE])
|
||||
case STM32MP25_PKG_CUSTOM:
|
||||
package = "XX";
|
||||
break;
|
||||
case STM32MP25_PKG_AL_TBGA361:
|
||||
case STM32MP25_PKG_AL_VFBGA361:
|
||||
package = "AL";
|
||||
break;
|
||||
case STM32MP25_PKG_AK_TBGA424:
|
||||
case STM32MP25_PKG_AK_VFBGA424:
|
||||
package = "AK";
|
||||
break;
|
||||
case STM32MP25_PKG_AI_TBGA436:
|
||||
case STM32MP25_PKG_AI_TFBGA436:
|
||||
package = "AI";
|
||||
break;
|
||||
default:
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
STM32MP1 BOARD
|
||||
M: Patrick Delaunay <patrick.delaunay@foss.st.com>
|
||||
M: Patrice Chotard <patrice.chotard@foss.st.com>
|
||||
L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
|
||||
T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git
|
||||
S: Maintained
|
||||
@@ -10,6 +11,7 @@ F: configs/stm32mp13_defconfig
|
||||
F: configs/stm32mp15_defconfig
|
||||
F: configs/stm32mp15_basic_defconfig
|
||||
F: configs/stm32mp15_trusted_defconfig
|
||||
F: configs/stm32mp15-odyssey_defconfig
|
||||
F: include/configs/stm32mp13_common.h
|
||||
F: include/configs/stm32mp13_st_common.h
|
||||
F: include/configs/stm32mp15_common.h
|
||||
|
||||
@@ -7,7 +7,7 @@ config SYS_VENDOR
|
||||
default "st"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "stm32mp25_common"
|
||||
default "stm32mp25_st_common"
|
||||
|
||||
source "board/st/common/Kconfig"
|
||||
endif
|
||||
|
||||
@@ -7,3 +7,4 @@ F: arch/arm/dts/stm32mp25*
|
||||
F: board/st/stm32mp2/
|
||||
F: configs/stm32mp25_defconfig
|
||||
F: include/configs/stm32mp25_common.h
|
||||
F: include/configs/stm32mp25_st_common.h
|
||||
|
||||
@@ -5,16 +5,21 @@
|
||||
|
||||
#define LOG_CATEGORY LOGC_BOARD
|
||||
|
||||
#include <button.h>
|
||||
#include <config.h>
|
||||
#include <env.h>
|
||||
#include <env_internal.h>
|
||||
#include <fdt_support.h>
|
||||
#include <led.h>
|
||||
#include <log.h>
|
||||
#include <misc.h>
|
||||
#include <mmc.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/ofnode.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
/*
|
||||
* Get a global data pointer
|
||||
@@ -53,12 +58,140 @@ int checkboard(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int get_led(struct udevice **dev, char *led_string)
|
||||
{
|
||||
const char *led_name;
|
||||
int ret;
|
||||
|
||||
led_name = ofnode_conf_read_str(led_string);
|
||||
if (!led_name) {
|
||||
log_debug("could not find %s config string\n", led_string);
|
||||
return -ENOENT;
|
||||
}
|
||||
ret = led_get_by_label(led_name, dev);
|
||||
if (ret) {
|
||||
log_debug("get=%d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_led(enum led_state_t cmd)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
|
||||
if (!CONFIG_IS_ENABLED(LED))
|
||||
return 0;
|
||||
|
||||
ret = get_led(&dev, "u-boot,boot-led");
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = led_set_state(dev, cmd);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void check_user_button(void)
|
||||
{
|
||||
struct udevice *button;
|
||||
int i;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_CMD_STM32PROG) || !IS_ENABLED(CONFIG_BUTTON))
|
||||
return;
|
||||
|
||||
if (button_get_by_label("User-2", &button))
|
||||
return;
|
||||
|
||||
for (i = 0; i < 21; ++i) {
|
||||
if (button_get_state(button) != BUTTON_ON)
|
||||
return;
|
||||
if (i < 20)
|
||||
mdelay(50);
|
||||
}
|
||||
|
||||
log_notice("entering download mode...\n");
|
||||
clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_STM32PROG);
|
||||
}
|
||||
|
||||
/* board dependent setup after realloc */
|
||||
int board_init(void)
|
||||
{
|
||||
setup_led(LEDST_ON);
|
||||
check_user_button();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
enum env_location env_get_location(enum env_operation op, int prio)
|
||||
{
|
||||
u32 bootmode = get_bootmode();
|
||||
|
||||
if (prio)
|
||||
return ENVL_UNKNOWN;
|
||||
|
||||
switch (bootmode & TAMP_BOOT_DEVICE_MASK) {
|
||||
case BOOT_FLASH_SD:
|
||||
case BOOT_FLASH_EMMC:
|
||||
if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC))
|
||||
return ENVL_MMC;
|
||||
else
|
||||
return ENVL_NOWHERE;
|
||||
|
||||
case BOOT_FLASH_NAND:
|
||||
case BOOT_FLASH_SPINAND:
|
||||
if (CONFIG_IS_ENABLED(ENV_IS_IN_UBI))
|
||||
return ENVL_UBI;
|
||||
else
|
||||
return ENVL_NOWHERE;
|
||||
|
||||
case BOOT_FLASH_NOR:
|
||||
if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH))
|
||||
return ENVL_SPI_FLASH;
|
||||
else
|
||||
return ENVL_NOWHERE;
|
||||
default:
|
||||
return ENVL_NOWHERE;
|
||||
}
|
||||
}
|
||||
|
||||
int mmc_get_boot(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
u32 boot_mode = get_bootmode();
|
||||
unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
|
||||
char cmd[20];
|
||||
const u32 sdmmc_addr[] = {
|
||||
STM32_SDMMC1_BASE,
|
||||
STM32_SDMMC2_BASE,
|
||||
STM32_SDMMC3_BASE
|
||||
};
|
||||
|
||||
if (instance > ARRAY_SIZE(sdmmc_addr))
|
||||
return 0;
|
||||
|
||||
/* search associated sdmmc node in devicetree */
|
||||
snprintf(cmd, sizeof(cmd), "mmc@%x", sdmmc_addr[instance]);
|
||||
if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
|
||||
log_err("mmc%d = %s not found in device tree!\n", instance, cmd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return dev_seq(dev);
|
||||
};
|
||||
|
||||
int mmc_get_env_dev(void)
|
||||
{
|
||||
const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1));
|
||||
|
||||
if (mmc_env_dev >= 0)
|
||||
return mmc_env_dev;
|
||||
|
||||
/* use boot instance to select the correct mmc device identifier */
|
||||
return mmc_get_boot();
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
const void *fdt_compat;
|
||||
@@ -86,3 +219,8 @@ int board_late_init(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_quiesce_devices(void)
|
||||
{
|
||||
setup_led(LEDST_OFF);
|
||||
}
|
||||
|
||||
@@ -8,7 +8,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7bdfff10
|
||||
CONFIG_ENV_SIZE=0x4000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="stih410-b2260"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="st/stih410-b2260"
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SYS_BOOTM_LEN=0x1000000
|
||||
CONFIG_SYS_LOAD_ADDR=0x40000000
|
||||
@@ -31,6 +31,7 @@ CONFIG_CMD_TIMER=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
# CONFIG_ISO_PARTITION is not set
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_UPSTREAM=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_USE_BOOTFILE=y
|
||||
CONFIG_BOOTFILE="uImage"
|
||||
|
||||
@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="stm32746g-eval"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="st/stm32746g-eval"
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SYS_MONITOR_LEN=524288
|
||||
CONFIG_SYS_LOAD_ADDR=0x8008000
|
||||
@@ -20,6 +20,7 @@ CONFIG_AUTOBOOT_STOP_STR=" "
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
|
||||
CONFIG_SYS_PBSIZE=1050
|
||||
CONFIG_DEFAULT_FDT_FILE="stm32746g-eval"
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
CONFIG_SYS_PROMPT="U-Boot > "
|
||||
CONFIG_CMD_GPT=y
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user