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CLK: ARC: HSDK: use appropriate config data types

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* constify clocks config data where is possible
* use more appropriate data types for clocks config

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Eugeniy Paltsev
2020-05-07 17:52:11 +03:00
committed by Alexey Brodkin
parent 5a2706524c
commit 731f12f382
1 changed files with 21 additions and 20 deletions
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41
drivers/clk/clk-hsdk-cgu.c
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@@ -129,8 +129,8 @@
#define MAX_FREQ_VARIATIONS 6 #define MAX_FREQ_VARIATIONS 6
struct hsdk_idiv_cfg { struct hsdk_idiv_cfg {
u32 oft; const u32 oft;
u8 val[MAX_FREQ_VARIATIONS]; const u8 val[MAX_FREQ_VARIATIONS];
}; };
struct hsdk_div_full_cfg { struct hsdk_div_full_cfg {
@@ -174,11 +174,11 @@ static const struct hsdk_div_full_cfg axi_clk_cfg = {
}; };
struct hsdk_pll_cfg { struct hsdk_pll_cfg {
u32 rate; const u32 rate;
u32 idiv; const u8 idiv;
u32 fbdiv; const u8 fbdiv;
u32 odiv; const u8 odiv;
u32 band; const u8 band;
}; };
static const struct hsdk_pll_cfg asdt_pll_cfg[] = { static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
@@ -233,9 +233,10 @@ struct hsdk_cgu_clk {
struct hsdk_pll_devdata { struct hsdk_pll_devdata {
const u32 parent_rate; const u32 parent_rate;
const struct hsdk_pll_cfg *pll_cfg; const struct hsdk_pll_cfg *const pll_cfg;
int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate, const int (*const update_rate)(struct hsdk_cgu_clk *clk,
const struct hsdk_pll_cfg *cfg); unsigned long rate,
const struct hsdk_pll_cfg *cfg);
}; };
static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long, static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
@@ -271,12 +272,12 @@ static ulong pll_set(struct clk *, ulong);
static ulong pll_get(struct clk *); static ulong pll_get(struct clk *);
struct hsdk_cgu_clock_map { struct hsdk_cgu_clock_map {
u32 cgu_pll_oft; const u32 cgu_pll_oft;
u32 cgu_div_oft; const u32 cgu_div_oft;
const struct hsdk_pll_devdata *pll_devdata; const struct hsdk_pll_devdata *const pll_devdata;
ulong (*get_rate)(struct clk *clk); const ulong (*const get_rate)(struct clk *clk);
ulong (*set_rate)(struct clk *clk, ulong rate); const ulong (*const set_rate)(struct clk *clk, ulong rate);
int (*disable)(struct clk *clk); const int (*const disable)(struct clk *clk);
}; };
static const struct hsdk_cgu_clock_map clock_map[] = { static const struct hsdk_cgu_clock_map clock_map[] = {
@@ -345,10 +346,10 @@ static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
u32 val = 0; u32 val = 0;
/* Powerdown and Bypass bits should be cleared */ /* Powerdown and Bypass bits should be cleared */
val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT; val |= (u32)cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT; val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT; val |= (u32)cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT; val |= (u32)cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
pr_debug("write configurarion: %#x\n", val); pr_debug("write configurarion: %#x\n", val);