colin/u-boot
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

novena: Move the DCD settings to spl code

Browse Source 
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.

Move the configuration to the spl code.

CCM_CCOSR setting is no longer required to get audio functionality in the
kernel, so remove such setting.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Fabio Estevam
2014-11-14 09:37:01 -02:00
committed by Stefano Babic
parent e25fbe3fe5
commit 7d29acd9b7
2 changed files with 28 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
board/kosagi/novena/novena_spl.c
View File

@@ -17,6 +17,7 @@
#include <asm/imx-common/boot_mode.h> #include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/mxc_i2c.h>
#include <asm/arch/crm_regs.h>
#include <i2c.h> #include <i2c.h>
#include <mmc.h> #include <mmc.h>
#include <fsl_esdhc.h> #include <fsl_esdhc.h>
@@ -533,6 +534,30 @@ static struct mx6_ddr3_cfg elpida_4gib_1600 = {
.trasmin = 3590, .trasmin = 3590,
}; };
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0xFFFFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/* /*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main) * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM * - we have a stack and a place to store GD, both in SRAM
@@ -543,6 +568,9 @@ void board_init_f(ulong dummy)
/* setup AIPS and disable watchdog */ /* setup AIPS and disable watchdog */
arch_cpu_init(); arch_cpu_init();
ccgr_init();
gpr_init();
/* setup GP timer */ /* setup GP timer */
timer_init(); timer_init();

31
board/kosagi/novena/setup.cfg
View File

@@ -14,34 +14,3 @@ IMAGE_VERSION 2
/* Boot Device : sd */ /* Boot Device : sd */
BOOT_FROM sd BOOT_FROM sd
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4, CCM_CCOSR, 0x000000fb