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imx8ulp: clock: Fix lcd clock algo

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The div loop uses reassign and reuse parent_rate, which causes
the parent rate reference to be wrong after the first loop, the
resulting clock becomes incorrect for div != 1.

Fixes: 829e06bf41 ("imx8ulp: clock: Add MIPI DSI clock and DCNano clock")
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Loic Poulain
2022-03-31 12:39:37 +02:00
committed by Stefano Babic
parent 22bfaa1f67
commit 85d0580e68
1 changed files with 2 additions and 3 deletions
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3
arch/arm/mach-imx/imx8ulp/clock.c
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@@ -440,10 +440,9 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz)
debug("PLL4 rate %ukhz\n", pll4_rate); debug("PLL4 rate %ukhz\n", pll4_rate);
for (pfd = 12; pfd <= 35; pfd++) { for (pfd = 12; pfd <= 35; pfd++) {
for (div = 1; div <= 64; div++) {
parent_rate = pll4_rate; parent_rate = pll4_rate;
parent_rate = parent_rate * 18 / pfd; parent_rate = parent_rate * 18 / pfd;
for (div = 1; div <= 64; div++) {
parent_rate = parent_rate / div; parent_rate = parent_rate / div;
for (pcd = 0; pcd < 8; pcd++) { for (pcd = 0; pcd < 8; pcd++) {