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Merge commit 'remotes/wd/master'

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This commit is contained in:
Jon Loeliger
2007-11-20 14:34:57 -06:00
parent 1d8a49eca1 9a337ddc15
commit 890e9413c0
102 changed files with 2439 additions and 435 deletions
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2
include/asm-arm/arch-at91rm9200/hardware.h
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@@ -24,8 +24,6 @@
#ifndef __ASSEMBLY__
#include "AT91RM9200.h"
#else
#include "AT91RM9200_inc.h"
#endif
/* Virtual and Physical base address for system peripherals */

29
include/asm-m68k/immap_5329.h
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@@ -57,7 +57,8 @@
#define MMAP_PWM 0xFC090000
#define MMAP_EPORT 0xFC094000
#define MMAP_WDOG 0xFC098000
#define MMAP_CCM 0xFC0A0000
#define MMAP_RCM 0xFC0A0000
#define MMAP_CCM 0xFC0A0004
#define MMAP_GPIO 0xFC0A4000
#define MMAP_RTC 0xFC0A8000
#define MMAP_LCDC 0xFC0AC000
@@ -479,20 +480,22 @@ typedef struct wdog_ctrl {
/*Chip configuration module registers */
typedef struct ccm_ctrl {
u8 rstctrl; /* 0x00 Reset Controller register */
u8 rststat; /* 0x01 Reset Status register */
u16 res1; /* 0x02 - 0x03 */
u16 ccr; /* 0x04 Chip configuration register */
u16 res2; /* 0x06 */
u16 rcon; /* 0x08 Rreset configuration register */
u16 cir; /* 0x0A Chip identification register */
u32 res3; /* 0x0C */
u16 misccr; /* 0x10 Miscellaneous control register */
u16 cdr; /* 0x12 Clock divider register */
u16 uhcsr; /* 0x14 USB Host controller status register */
u16 uocsr; /* 0x16 USB On-the-Go Controller Status Register */
u16 ccr; /* 0x00 Chip configuration register */
u16 res2; /* 0x02 */
u16 rcon; /* 0x04 Rreset configuration register */
u16 cir; /* 0x06 Chip identification register */
u32 res3; /* 0x08 */
u16 misccr; /* 0x0A Miscellaneous control register */
u16 cdr; /* 0x0C Clock divider register */
u16 uhcsr; /* 0x10 USB Host controller status register */
u16 uocsr; /* 0x12 USB On-the-Go Controller Status Reg */
} ccm_t;
typedef struct rcm {
u8 rcr;
u8 rsr;
} rcm_t;
/* GPIO port registers */
typedef struct gpio_ctrl {
/* Port Output Data Registers */

15
include/asm-m68k/m5329.h
View File

@@ -245,6 +245,21 @@
#define CSCR_BSTR (0x00000010)
#define CSCR_BSTW (0x00000008)
/*********************************************************************
* Reset Controller Module (RCM)
*********************************************************************/
/* Bit definitions and macros for RCR */
#define RCM_RCR_FRCRSTOUT (0x40)
#define RCM_RCR_SOFTRST (0x80)
/* Bit definitions and macros for RSR */
#define RCM_RSR_LOL (0x01)
#define RCM_RSR_WDR_CORE (0x02)
#define RCM_RSR_EXT (0x04)
#define RCM_RSR_POR (0x08)
#define RCM_RSR_SOFT (0x20)
/*********************************************************************
* FlexCAN Module (CAN)
*********************************************************************/

4
include/asm-m68k/m5445x.h
View File

@@ -792,8 +792,8 @@
#define GPIO_PAR_FEC_FEC0_MASK (0xF8)
#define GPIO_PAR_FEC_FEC0_MII (0x07)
#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
#define GPIO_PAR_FEC_FEC0_RMII_ATA (0x02)
#define GPIO_PAR_FEC_FEC0_ATA (0x01)
#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
#define GPIO_PAR_FEC_FEC0_ULPI (0x01)
#define GPIO_PAR_FEC_FEC0_GPIO (0x00)
/* Bit definitions and macros for PAR_DMA */

16
include/asm-mips/io.h
View File

@@ -71,7 +71,21 @@
* instruction, so the lower 16 bits must be zero. Should be true on
* on any sane architecture; generic code does not use this assumption.
*/
extern unsigned long mips_io_port_base;
extern const unsigned long mips_io_port_base;
/*
* Gcc will generate code to load the value of mips_io_port_base after each
* function call which may be fairly wasteful in some cases. So we don't
* play quite by the book. We tell gcc mips_io_port_base is a long variable
* which solves the code generation issue. Now we need to violate the
* aliasing rules a little to make initialization possible and finally we
* will need the barrier() to fight side effects of the aliasing chat.
* This trickery will eventually collapse under gcc's optimizer. Oh well.
*/
static inline void set_io_port_base(unsigned long base)
{
* (unsigned long *) &mips_io_port_base = base;
}
/*
* Thanks to James van Artsdalen for a better timing-fix than

8
include/common.h
View File

@@ -63,19 +63,13 @@ typedef volatile unsigned char vu_char;
#endif
#elif defined(CONFIG_5xx)
#include <asm/5xx_immap.h>
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC5xxx)
#include <mpc5xxx.h>
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC512X)
#include <mpc512x.h>
#include <asm/immap_512x.h>
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_MPC8220)
#include <asm/immap_8220.h>
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_824X)
#define CONFIG_RELOC_FIXUP_WORKS
#elif defined(CONFIG_8260)
#if defined(CONFIG_MPC8247) \
|| defined(CONFIG_MPC8248) \
@@ -87,7 +81,6 @@ typedef volatile unsigned char vu_char;
#define CONFIG_MPC8260 1
#endif
#include <asm/immap_8260.h>
#define CONFIG_RELOC_FIXUP_WORKS
#endif
#ifdef CONFIG_MPC86xx
#include <mpc86xx.h>
@@ -100,7 +93,6 @@ typedef volatile unsigned char vu_char;
#ifdef CONFIG_MPC83XX
#include <mpc83xx.h>
#include <asm/immap_83xx.h>
#define CONFIG_RELOC_FIXUP_WORKS
#endif
#ifdef CONFIG_4xx
#include <ppc4xx.h>

10
include/configs/MPC8568MDS.h
View File

@@ -334,11 +334,6 @@ extern unsigned long get_clock_freq(void);
#define CFG_SRIO_MEM_BASE 0xc0000000
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#ifdef CONFIG_QE
/*
* QE UEC ethernet configuration
@@ -377,6 +372,11 @@ extern unsigned long get_clock_freq(void);
#endif
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

4
include/configs/lwmon5.h
View File

@@ -432,7 +432,7 @@
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
@@ -473,7 +473,7 @@
{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \

4
include/configs/rsdproto.h
View File

@@ -92,8 +92,8 @@
/* enable I2C */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x30
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */

2
include/configs/uc101.h
View File

@@ -297,7 +297,7 @@
/* 8Mbit SRAM @0x80100000 */
#define CFG_CS1_START CFG_SRAM_BASE
#define CFG_CS1_SIZE 0x00100000
#define CFG_CS1_SIZE 0x00200000
#define CFG_CS1_CFG 0x21D00
/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */

110
include/miiphy.h
View File

@@ -26,56 +26,49 @@
|
| Author: Mark Wisner
|
| Change Activity-
|
| Date Description of Change BY
| --------- --------------------- ---
| 04-May-99 Created MKW
| 07-Jul-99 Added full duplex support MKW
| 08-Sep-01 Tweaks gvb
|
+----------------------------------------------------------------------------*/
#ifndef _miiphy_h_
#define _miiphy_h_
#include <net.h>
int miiphy_read(char *devname, unsigned char addr, unsigned char reg,
unsigned short *value);
int miiphy_write(char *devname, unsigned char addr, unsigned char reg,
unsigned short value);
int miiphy_info(char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev);
int miiphy_reset(char *devname, unsigned char addr);
int miiphy_speed(char *devname, unsigned char addr);
int miiphy_duplex(char *devname, unsigned char addr);
int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
unsigned short *value);
int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
unsigned short value);
int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
unsigned char *model, unsigned char *rev);
int miiphy_reset (char *devname, unsigned char addr);
int miiphy_speed (char *devname, unsigned char addr);
int miiphy_duplex (char *devname, unsigned char addr);
int miiphy_is_1000base_x (char *devname, unsigned char addr);
#ifdef CFG_FAULT_ECHO_LINK_DOWN
int miiphy_link(char *devname, unsigned char addr);
int miiphy_link (char *devname, unsigned char addr);
#endif
void miiphy_init(void);
void miiphy_init (void);
void miiphy_register(char *devname,
int (* read)(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (* write)(char *devname, unsigned char addr,
unsigned char reg, unsigned short value));
void miiphy_register (char *devname,
int (*read) (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value),
int (*write) (char *devname, unsigned char addr,
unsigned char reg, unsigned short value));
int miiphy_set_current_dev(char *devname);
char *miiphy_get_current_dev(void);
int miiphy_set_current_dev (char *devname);
char *miiphy_get_current_dev (void);
void miiphy_listdev(void);
void miiphy_listdev (void);
#define BB_MII_DEVNAME "bbmii"
int bb_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
unsigned char reg, unsigned short *value);
int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
unsigned char reg, unsigned short value);
/* phy seed setup */
#define AUTO 99
#define _1000BASET 1000
#define _1000BASET 1000
#define _100BASET 100
#define _10BASET 10
#define HALF 22
@@ -90,9 +83,10 @@ int bb_miiphy_write (char *devname, unsigned char addr,
#define PHY_ANLPAR 0x05
#define PHY_ANER 0x06
#define PHY_ANNPTR 0x07
#define PHY_ANLPNP 0x08
#define PHY_1000BTCR 0x09
#define PHY_1000BTSR 0x0A
#define PHY_ANLPNP 0x08
#define PHY_1000BTCR 0x09
#define PHY_1000BTSR 0x0A
#define PHY_EXSR 0x0F
#define PHY_PHYSTS 0x10
#define PHY_MIPSCR 0x11
#define PHY_MIPGSR 0x12
@@ -115,10 +109,10 @@ int bb_miiphy_write (char *devname, unsigned char addr,
#define PHY_BMCR_DPLX 0x0100
#define PHY_BMCR_COL_TST 0x0080
#define PHY_BMCR_SPEED_MASK 0x2040
#define PHY_BMCR_1000_MBPS 0x0040
#define PHY_BMCR_100_MBPS 0x2000
#define PHY_BMCR_10_MBPS 0x0000
#define PHY_BMCR_SPEED_MASK 0x2040
#define PHY_BMCR_1000_MBPS 0x0040
#define PHY_BMCR_100_MBPS 0x2000
#define PHY_BMCR_10_MBPS 0x0000
/* phy BMSR */
#define PHY_BMSR_100T4 0x8000
@@ -126,6 +120,7 @@ int bb_miiphy_write (char *devname, unsigned char addr,
#define PHY_BMSR_100TXH 0x2000
#define PHY_BMSR_10TF 0x1000
#define PHY_BMSR_10TH 0x0800
#define PHY_BMSR_EXT_STAT 0x0100
#define PHY_BMSR_PRE_SUP 0x0040
#define PHY_BMSR_AUTN_COMP 0x0020
#define PHY_BMSR_RF 0x0010
@@ -138,23 +133,42 @@ int bb_miiphy_write (char *devname, unsigned char addr,
#define PHY_ANLPAR_NP 0x8000
#define PHY_ANLPAR_ACK 0x4000
#define PHY_ANLPAR_RF 0x2000
#define PHY_ANLPAR_ASYMP 0x0800
#define PHY_ANLPAR_PAUSE 0x0400
#define PHY_ANLPAR_T4 0x0200
#define PHY_ANLPAR_TXFD 0x0100
#define PHY_ANLPAR_TX 0x0080
#define PHY_ANLPAR_10FD 0x0040
#define PHY_ANLPAR_10 0x0020
#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
#define PHY_ANLPAR_100 0x0380 /* we can run at 100 */
/* phy ANLPAR 1000BASE-X */
#define PHY_X_ANLPAR_NP 0x8000
#define PHY_X_ANLPAR_ACK 0x4000
#define PHY_X_ANLPAR_RF_MASK 0x3000
#define PHY_X_ANLPAR_PAUSE_MASK 0x0180
#define PHY_X_ANLPAR_HD 0x0040
#define PHY_X_ANLPAR_FD 0x0020
#define PHY_ANLPAR_PSB_MASK 0x001f
#define PHY_ANLPAR_PSB_802_3 0x0001
#define PHY_ANLPAR_PSB_802_9 0x0002
#define PHY_ANLPAR_PSB_MASK 0x001f
#define PHY_ANLPAR_PSB_802_3 0x0001
#define PHY_ANLPAR_PSB_802_9 0x0002
/* PHY_1000BTSR */
#define PHY_1000BTSR_MSCF 0x8000
#define PHY_1000BTSR_MSCR 0x4000
#define PHY_1000BTSR_LRS 0x2000
#define PHY_1000BTSR_RRS 0x1000
#define PHY_1000BTSR_1000FD 0x0800
#define PHY_1000BTSR_1000HD 0x0400
/* phy 1000BTCR */
#define PHY_1000BTCR_1000FD 0x0200
#define PHY_1000BTCR_1000HD 0x0100
/* phy 1000BTSR */
#define PHY_1000BTSR_MSCF 0x8000
#define PHY_1000BTSR_MSCR 0x4000
#define PHY_1000BTSR_LRS 0x2000
#define PHY_1000BTSR_RRS 0x1000
#define PHY_1000BTSR_1000FD 0x0800
#define PHY_1000BTSR_1000HD 0x0400
/* phy EXSR */
#define PHY_EXSR_1000XF 0x8000
#define PHY_EXSR_1000XH 0x4000
#define PHY_EXSR_1000TF 0x2000
#define PHY_EXSR_1000TH 0x1000
#endif