From b416df33c9701955752a8ba22c1cf46ee6465ef6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 22 Apr 2022 13:50:06 +0530 Subject: [PATCH 01/56] configs: Layerscape: Remove the 'fdt_addr' env On Layerscape platforms, the DTB is loaded from boot filesystem, per the fdt_addr description in doc/README.distro, it must be removed. Signed-off-by: Hou Zhiqiang [Rebased] Signed-off-by: Priyanka Jain --- include/configs/ls1012a2g5rdb.h | 1 - include/configs/ls1012afrdm.h | 2 +- include/configs/ls1012afrwy.h | 1 - include/configs/ls1012aqds.h | 1 - include/configs/ls1012ardb.h | 1 - include/configs/ls1021atsn.h | 1 - include/configs/ls1021atwr.h | 4 +--- include/configs/ls1028aqds.h | 3 +-- include/configs/ls1028ardb.h | 3 +-- include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls1088ardb.h | 2 -- include/configs/ls2080ardb.h | 2 -- include/configs/lx2160a_common.h | 1 - 14 files changed, 4 insertions(+), 20 deletions(-) diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 835eca7726d..f0248e64646 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -19,7 +19,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x800000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 44518cdf641..cb79d6362fc 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #ifndef __LS1012ARDB_H__ @@ -21,7 +22,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "fdt_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ "fdtheader_addr_r=0x80100000\0" \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 16ce89233fb..a1d23b64630 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -35,7 +35,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernel_size_sd=0x16000\0" \ "kernelhdr_size_sd=0x10\0" \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index e7a0294644c..b5992366cf4 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -89,7 +89,6 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x600000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 2490ba3212a..c57b598d70d 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -44,7 +44,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x600000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 546c4fcdb95..09168a28e7d 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -114,7 +114,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b4383d4bbdb..b36c8dccf17 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #ifndef __CONFIG_H @@ -209,7 +209,6 @@ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x65000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ @@ -266,7 +265,6 @@ "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index b9c05943ec2..35363ccda1a 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #ifndef __LS1028A_QDS_H @@ -68,7 +68,6 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 15ac1f565e4..91223789b83 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #ifndef __LS1028A_RDB_H @@ -64,7 +64,6 @@ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "bootm_size=0x10000000\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 61c6d456764..26db8ffe7e2 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -173,7 +173,6 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index f9279e4ab46..fb2011aa559 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -165,7 +165,6 @@ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "bootm_size=0x10000000\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 693a2f64b6c..c69003018bf 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -271,7 +271,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ "kernelhdr_addr_sd=0x3000\0" \ @@ -340,7 +339,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ "kernelhdr_addr_sd=0x3000\0" \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index de269f4c7ed..52a48bd4b89 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -323,7 +323,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x581000000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x800000\0" \ @@ -386,7 +385,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x581000000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x600000\0" \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index d5690148195..aaba8fc26d9 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -164,7 +164,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x600000\0" \ "scriptaddr=0x80000000\0" \ From 9c18c695f820198c37aad812ce82e6a78195051e Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 22 Feb 2022 13:38:39 -0500 Subject: [PATCH 02/56] armv8: fsl-layerscape: Respect Kconfig for erratum A009007 There is a Kconfig for this erratum, but it is ignored for armv8. Respect it. Signed-off-by: Sean Anderson Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d3a5cfaac19..926f8f21b63 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -206,6 +206,9 @@ static void erratum_a008997(void) static void erratum_a009007(void) { + if (!IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A009007)) + return; + #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ defined(CONFIG_ARCH_LS1012A) void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; From 881284b36a3785328ac611bab4aedd9a2a8563e6 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 22 Apr 2022 14:01:36 +0530 Subject: [PATCH 03/56] arm: layerscape: Disable erratum A009007 on LS1021A, LS1043A, and LS1046A This erratum is reported to cause problems on these processors [1-3]. The problem is usually with the clocking, which is supposed to be configured by the RCW [4]. However, if it is not set, or if the default clocking is not correct, then this erratum will cause an SError. However, according to Ran Wang in [1]: " ... this erratum is used to pass USB compliance test only, you could disable this workaround on your board if you don't any USB issue on normal use case, I think it's fine." So just disable this erratum by default for these processors. [1] https://lore.kernel.org/all/761ddd61-05c1-d9b8-ac90-b8f425afde6c@denx.de/ [2] https://community.nxp.com/t5/Layerscape/LS1046A-U-BOOT-HALT-AT-ERRATUM-A0090078/m-p/742993 [3] https://community.nxp.com/t5/QorIQ/Why-does-the-LS1043A-U-Boot-hang-at-code-that-fixes-erratum/m-p/644412 [4] https://source.codeaurora.org/external/qoriq/qoriq-components/rcw/tree/ls1046ardb/usb_phy_freq.rcw Signed-off-by: Sean Anderson Acked-by: Ran Wang [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv7/ls102xa/Kconfig | 1 - arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 -- 2 files changed, 3 deletions(-) diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index ef1f45650f3..c496e643919 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -7,7 +7,6 @@ config ARCH_LS1021A select SYS_FSL_ERRATUM_A008407 select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR select SYS_FSL_ERRATUM_A008997 if USB - select SYS_FSL_ERRATUM_A009007 if USB select SYS_FSL_ERRATUM_A009008 if USB select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009798 if USB diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5ea99c459ce..dd953803dcd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -74,7 +74,6 @@ config ARCH_LS1043A select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009660 if !TFABOOT select SYS_FSL_ERRATUM_A009663 if !TFABOOT @@ -112,7 +111,6 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A008511 if !TFABOOT select SYS_FSL_ERRATUM_A008850 if !TFABOOT select SYS_FSL_ERRATUM_A008997 - select SYS_FSL_ERRATUM_A009007 select SYS_FSL_ERRATUM_A009008 select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009801 From eb217200efab6c400f96fb039474dcc840bb8404 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 28 Feb 2022 13:48:37 +0100 Subject: [PATCH 04/56] armv8: include psci_update_dt() unconditionally psci_update_dt() is also required if CONFIG_ARMV8_PSCI is set, that is, if u-boot is the PSCI provider. Guard the check which is intended to call into the PSCI implementation in the secure firmware, by the proper macro SEC_FIRMWARE_ARMV8_PSCI. Mark the function as weak because - unfortunately - there is already a stub of the same function in arch/arm/mach-rmobile/psci-r8a779a0.c which does not the same as the common one. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/cpu-dt.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c index 61c38b17cbf..9bfe3815e51 100644 --- a/arch/arm/cpu/armv8/cpu-dt.c +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -8,9 +8,9 @@ #include #include #include +#include -#if CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) -int psci_update_dt(void *fdt) +__weak int psci_update_dt(void *fdt) { /* * If the PSCI in SEC Firmware didn't work, avoid to update the @@ -18,8 +18,10 @@ int psci_update_dt(void *fdt) * number to support detecting PSCI dynamically and then switching * the SMP boot method between PSCI and spin-table. */ - if (sec_firmware_support_psci_version() == PSCI_INVALID_VER) + if (CONFIG_IS_ENABLED(SEC_FIRMWARE_ARMV8_PSCI) && + sec_firmware_support_psci_version() == PSCI_INVALID_VER) return 0; + fdt_psci(fdt); #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE) @@ -30,4 +32,3 @@ int psci_update_dt(void *fdt) return 0; } -#endif From cb14cc8867cde068aa798375ba14eaef12cff6c4 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 22 Apr 2022 14:53:27 +0530 Subject: [PATCH 05/56] armv8: layerscape: get rid of smc_call() There are two different implementations to do a secure monitor call: smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and seems to be an ad-hoc implementation. The latter is imported from linux. smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined. This makes it impossible to have both PSCI calls and PSCI implementation in one u-boot build. The layerscape SoC code decide at runtime via check_psci() if there is a PSCI support. Therefore, this is a prerequisite patch to add PSCI implementation support for the layerscape SoCs. Note, for the TFA part, this is only compile time tested with (ls1028ardb_tfa_defconfig). Signed-off-by: Michael Walle [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 49 +++++++++-------------- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 11 ++--- arch/arm/cpu/armv8/sec_firmware.c | 19 ++++----- 4 files changed, 31 insertions(+), 49 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index dd953803dcd..6f8d5cb72fd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -333,6 +333,7 @@ menu "Layerscape architecture" config FSL_LAYERSCAPE bool + select ARM_SMCCC config HAS_FEATURE_GIC64K_ALIGN bool diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index cf469804c51..a71ee636afe 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -768,7 +769,7 @@ enum boot_src __get_boot_src(u32 porsr1) enum boot_src get_boot_src(void) { - struct pt_regs regs; + struct arm_smccc_res res; u32 porsr1 = 0; #if defined(CONFIG_FSL_LSCH3) @@ -778,11 +779,9 @@ enum boot_src get_boot_src(void) #endif if (current_el() == 2) { - regs.regs[0] = SIP_SVC_RCW; - - smc_call(®s); - if (!regs.regs[0]) - porsr1 = regs.regs[1]; + arm_smccc_smc(SIP_SVC_RCW, 0, 0, 0, 0, 0, 0, 0, &res); + if (!res.a0) + porsr1 = res.a1; } if (current_el() == 3 || !porsr1) { @@ -1081,9 +1080,9 @@ static void config_core_prefetch(void) char *buf = NULL; char buffer[HWCONFIG_BUFFER_SIZE]; const char *prefetch_arg = NULL; + struct arm_smccc_res res; size_t arglen; unsigned int mask; - struct pt_regs regs; if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; @@ -1101,11 +1100,10 @@ static void config_core_prefetch(void) } #define SIP_PREFETCH_DISABLE_64 0xC200FF13 - regs.regs[0] = SIP_PREFETCH_DISABLE_64; - regs.regs[1] = mask; - smc_call(®s); + arm_smccc_smc(SIP_PREFETCH_DISABLE_64, mask, 0, 0, 0, 0, 0, 0, + &res); - if (regs.regs[0]) + if (res.a0) printf("Prefetch disable config failed for mask "); else printf("Prefetch disable config passed for mask "); @@ -1345,25 +1343,20 @@ phys_size_t get_effective_memsize(void) #ifdef CONFIG_TFABOOT phys_size_t tfa_get_dram_size(void) { - struct pt_regs regs; - phys_size_t dram_size = 0; + struct arm_smccc_res res; - regs.regs[0] = SMC_DRAM_BANK_INFO; - regs.regs[1] = -1; - - smc_call(®s); - if (regs.regs[0]) + arm_smccc_smc(SMC_DRAM_BANK_INFO, -1, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) return 0; - dram_size = regs.regs[1]; - return dram_size; + return res.a1; } static int tfa_dram_init_banksize(void) { int i = 0, ret = 0; - struct pt_regs regs; phys_size_t dram_size = tfa_get_dram_size(); + struct arm_smccc_res res; debug("dram_size %llx\n", dram_size); @@ -1371,19 +1364,15 @@ static int tfa_dram_init_banksize(void) return -EINVAL; do { - regs.regs[0] = SMC_DRAM_BANK_INFO; - regs.regs[1] = i; - - smc_call(®s); - if (regs.regs[0]) { + arm_smccc_smc(SMC_DRAM_BANK_INFO, i, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) { ret = -EINVAL; break; } - debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1], - regs.regs[2]); - gd->bd->bi_dram[i].start = regs.regs[1]; - gd->bd->bi_dram[i].size = regs.regs[2]; + debug("bank[%d]: start %lx, size %lx\n", i, res.a1, res.a2); + gd->bd->bi_dram[i].start = res.a1; + gd->bd->bi_dram[i].size = res.a2; dram_size -= gd->bd->bi_dram[i].size; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 2e2688eadca..72221191493 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -302,6 +302,7 @@ int cpu_release(u32 nr, int argc, char *const argv[]) u64 boot_addr; u64 *table = get_spin_tbl_addr(); int pos; + int ret; boot_addr = simple_strtoull(argv[0], NULL, 16); @@ -326,16 +327,10 @@ int cpu_release(u32 nr, int argc, char *const argv[]) asm volatile("sev"); } else { /* Use PSCI to kick the core */ - struct pt_regs regs; - printf("begin to kick cpu core #%d to address %llx\n", nr, boot_addr); - regs.regs[0] = PSCI_0_2_FN64_CPU_ON; - regs.regs[1] = nr; - regs.regs[2] = boot_addr; - regs.regs[3] = 0; - smc_call(®s); - if (regs.regs[0]) + ret = invoke_psci_fn(PSCI_0_2_FN64_CPU_ON, nr, boot_addr, 0); + if (ret) return -1; } diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index 267894fbcb3..7e6e4064ffe 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -374,29 +375,25 @@ bool sec_firmware_support_hwrng(void) */ int sec_firmware_get_random(uint8_t *rand, int bytes) { + struct arm_smccc_res res; unsigned long long num; - struct pt_regs regs; int param1; if (!bytes || bytes > 8) { printf("Max Random bytes genration supported is 8\n"); return -1; } -#define SIP_RNG_64 0xC200FF11 - regs.regs[0] = SIP_RNG_64; - if (bytes <= 4) param1 = 0; else param1 = 1; - regs.regs[1] = param1; - smc_call(®s); - - if (regs.regs[0]) +#define SIP_RNG_64 0xC200FF11 + arm_smccc_smc(SIP_RNG_64, param1, 0, 0, 0, 0, 0, 0, &res); + if (res.a0) return -1; - num = regs.regs[1]; + num = res.a1; memcpy(rand, &num, bytes); return 0; @@ -473,8 +470,8 @@ int fdt_fixup_kaslr(void *fdt) return 0; } - ret = sec_firmware_get_random(rand, 8); - if (ret < 0) { + err = sec_firmware_get_random(rand, 8); + if (err < 0) { printf("WARNING: No random number to set kaslr-seed\n"); return 0; } From de58ac49a5d941a053008bf395c862efc34b5595 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 28 Feb 2022 13:48:39 +0100 Subject: [PATCH 06/56] armv8: psci: skip setup code if we are not EL3 If we are running in EL2 skip PSCI implementation setup. This avoids an exception if CONFIG_ARMV8_PSCI is set, but u-boot is started by TF-A. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c index ea40c55dd2c..db5d460eb46 100644 --- a/arch/arm/cpu/armv8/cpu.c +++ b/arch/arm/cpu/armv8/cpu.c @@ -79,6 +79,9 @@ static void relocate_secure_section(void) void armv8_setup_psci(void) { + if (current_el() != 3) + return; + relocate_secure_section(); secure_ram_addr(psci_setup_vectors)(); secure_ram_addr(psci_arch_init)(); From 49bb245f1dc447152a80b522cce7b964e0972517 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 28 Feb 2022 13:48:40 +0100 Subject: [PATCH 07/56] armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig option There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the same meaning but is just for the ls1043ardb board. As no in-tree config uses this, drop it and replace it with something more sophiticated: ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE option which is used as the base to relocate the PSCI code (or any code in the secure region, but that is only PSCI). A SoC (or board) can now opt-in into having such a secure region by enabling SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was possible to relocate the PSCI code before as well as on the LS1028A SoC where there will be PSCI support soon. Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/Kconfig | 34 ++++++++++++++--------- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 ++ board/freescale/ls1043ardb/Kconfig | 8 ------ 3 files changed, 23 insertions(+), 21 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 4d4469c8843..09f3f50fa22 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -90,6 +90,7 @@ config SPL_RECOVER_DATA_SECTION config SEC_FIRMWARE_ARMV8_PSCI bool "PSCI implementation in secure monitor firmware" depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT + depends on ARMV8_PSCI=n help This config enables the ARMv8 PSCI implementation in secure monitor firmware. This is a private PSCI implementation and different from @@ -131,6 +132,9 @@ config PSCI_RESET Select Y here to make use of PSCI calls for system reset +config SYS_HAS_ARMV8_SECURE_BASE + bool + config ARMV8_PSCI bool "Enable PSCI support" if EXPERT help @@ -158,23 +162,27 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER A value 0 or no definition of it works for single cluster system. System with multi-cluster should difine their own exact value. +config ARMV8_PSCI_RELOCATE + bool "Relocate PSCI code" + depends on ARMV8_PSCI + depends on SYS_HAS_ARMV8_SECURE_BASE + help + Relocate PSCI code, for example to a secure memory on the SoC. If not + set, the PSCI sections are placed together with the u-boot and the + regions will be marked as reserved before linux is started. + +config ARMV8_SECURE_BASE + hex "Secure address for PSCI image" + depends on ARMV8_PSCI_RELOCATE + default 0x18000000 if ARCH_LS1028A + help + Address for placing the PSCI text, data and stack sections. + + config ARMV8_EA_EL3_FIRST bool "External aborts and SError interrupt exception are taken in EL3" help Exception handling at all exception levels for External Abort and SError interrupt exception are taken in EL3. -if SYS_HAS_ARMV8_SECURE_BASE - -config ARMV8_SECURE_BASE - hex "Secure address for PSCI image" - depends on ARMV8_PSCI - help - Address for placing the PSCI text, data and stack sections. - If not defined, the PSCI sections are placed together with the u-boot - but platform can choose to place PSCI code image separately in other - places such as some secure RAM built-in SOC etc. - -endif - endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 6f8d5cb72fd..80a1642447d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -55,6 +55,7 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A011334 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select RESV_RAM if GIC_V3_ITS + select SYS_HAS_ARMV8_SECURE_BASE imply PANIC_HANG config ARCH_LS1043A @@ -90,6 +91,7 @@ config ARCH_LS1043A select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C select SYS_I2C_MXC_I2C4 if !DM_I2C + select SYS_HAS_ARMV8_SECURE_BASE imply CMD_PCI imply ID_EEPROM diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig index 778b8d8d5a5..d66c7804b13 100644 --- a/board/freescale/ls1043ardb/Kconfig +++ b/board/freescale/ls1043ardb/Kconfig @@ -13,14 +13,6 @@ config SYS_SOC config SYS_CONFIG_NAME default "ls1043ardb" -config SYS_HAS_ARMV8_SECURE_BASE - bool "Enable secure address for PSCI image" - depends on ARMV8_PSCI - help - PSCI image can be re-located to secure RAM. - If enabled, please also define the value for ARMV8_SECURE_BASE, - for LS1043ARDB, it could be some address in OCRAM. - if FSL_LS_PPA config SYS_LS_PPA_FW_ADDR hex "PPA Firmware Addr" From 20759b2973e77d86ffea11a7eff3fccbc0e37dd9 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 25 Apr 2022 09:25:08 +0530 Subject: [PATCH 08/56] board: sl28: add basic PSCI implementation For now, this only provides reset and poweroff functions. Signed-off-by: Michael Walle [Rebased] Signed-off-by: Priyanka Jain --- board/kontron/sl28/Makefile | 2 ++ board/kontron/sl28/psci.c | 42 ++++++++++++++++++++++++++++++++++ configs/kontron_sl28_defconfig | 2 ++ 3 files changed, 46 insertions(+) create mode 100644 board/kontron/sl28/psci.c diff --git a/board/kontron/sl28/Makefile b/board/kontron/sl28/Makefile index 5d220f07447..084c11da376 100644 --- a/board/kontron/sl28/Makefile +++ b/board/kontron/sl28/Makefile @@ -6,6 +6,8 @@ endif obj-y += common.o ddr.o +obj-$(CONFIG_ARMV8_PSCI) += psci.o + ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-$(CONFIG_SPL_ATF) += spl_atf.o diff --git a/board/kontron/sl28/psci.c b/board/kontron/sl28/psci.c new file mode 100644 index 00000000000..19f0ef3b6df --- /dev/null +++ b/board/kontron/sl28/psci.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include +#include +#include +#include +#include + +#define GPIO2_GPDIR 0x2310000 +#define GPIO2_GPDAT 0x2310008 +#define RSTCR 0x1e60000 +#define RESET_REQ BIT(1) + +u32 __secure psci_version(void) +{ + return ARM_PSCI_VER_0_2; +} + +void __secure psci_system_reset(void) +{ + writel(RESET_REQ, RSTCR); + + while (1) + wfi(); +} + +void __secure psci_system_off(void) +{ + int i; + + writel(0x02000000, GPIO2_GPDIR); + writel(0, GPIO2_GPDAT); + + /* make sure the management controller has sampled the input */ + for (i = 0; i < (1 << 11); i++) + asm("nop"); + + writel(RESET_REQ, RSTCR); + + while (1) + wfi(); +} diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 7a00e48ebcc..dc8c28f8cca 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -20,6 +20,8 @@ CONFIG_ENV_OFFSET_REDUND=0x3f0000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y # CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_PSCI=y +CONFIG_ARMV8_PSCI_RELOCATE=y CONFIG_SYS_LOAD_ADDR=0x82000000 CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y From aaaa1be8f043ff9412f9c35c62a05bcf218eda34 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 9 Mar 2022 15:37:22 +0800 Subject: [PATCH 09/56] armv8: layerscape: fix the function mismatch issue Signed-off-by: Yuantian Tang Reviewed-by: Andre Przywara Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 2fb4e404a24..87410c73a92 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014-2015 Freescale Semiconductor - * Copyright 2019 NXP + * Copyright 2019-2022 NXP * * Extracted from armv8/start.S */ @@ -344,7 +344,7 @@ ENTRY(fsl_ocram_clear_ecc_err) ldr x0, =DCSR_DCFG_MBEESR2 str w1, [x0] ret -ENDPROC(fsl_ocram_init) +ENDPROC(fsl_ocram_clear_ecc_err) #endif #ifdef CONFIG_FSL_LSCH3 From 3b06577ab4eefd954348f1dc0f5abb3408d10d0c Mon Sep 17 00:00:00 2001 From: Stephen Carlson Date: Tue, 29 Mar 2022 14:51:10 -0700 Subject: [PATCH 10/56] armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES) that can be configured for the application. Interfaces not used by the application can be set to protocol 0 to turn them off and save power, but U-Boot would emit a warning that 0 was invalid for a SERDES protocol on boot. Replace the warning text with a notice that the SERDES is disabled. Signed-off-by: Stephen Carlson Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index fad7a935662..181bd9c1b4e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -147,10 +147,14 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, cfg >>= sd_prctl_shift; cfg = serdes_get_number(sd, cfg); - printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); + if (cfg == 0) { + printf("SERDES%d is disabled\n", sd + 1); + } else { + printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); - if (!is_serdes_prtcl_valid(sd, cfg)) - printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + if (!is_serdes_prtcl_valid(sd, cfg)) + printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg); + } for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane); From 2dcf776ebcf7f224f2a2e6720e863aca493a5cd9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 25 Apr 2022 09:29:08 +0530 Subject: [PATCH 11/56] powerpc: mpc85xx: Drop _start symbol MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit _start symbol contains only 32-bit data number 0x27051956 despite it is marked as text section. This magic number is IH_MAGIC which is used for marking uboot image header. mpc85xx start.S code does not define valid uboot image header, so IH_MAGIC number in _start symbol is useless there. Moreover this _start symbol is not used at all. Entry point is at symbol _start_e500. So because this _start symbol is not used for anything, completely remove it with IH_MAGIC number. After _start symbol was _start_cont symbol, so replace all relative address calculations by _start_cont. Signed-off-by: Pali Rohár [Rebased] Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/start.S | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9ddd3711190..07e855e89b4 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -46,7 +46,6 @@ GOT_ENTRY(_FIXUP_TABLE_) #ifndef MINIMAL_SPL - GOT_ENTRY(_start) GOT_ENTRY(_start_of_vectors) GOT_ENTRY(_end_of_vectors) GOT_ENTRY(transfer_to_handler) @@ -1128,16 +1127,12 @@ switch_as: /*--------------------------------------------------------------*/ lis r3,CONFIG_VAL(SYS_MONITOR_BASE)@h ori r3,r3,CONFIG_VAL(SYS_MONITOR_BASE)@l - addi r3,r3,_start_cont - _start + addi r3,r3,_start_cont - _start_cont mtlr r3 blr #endif .text - .globl _start -_start: - .long 0x27051956 /* U-BOOT Magic Number */ - .globl _start_cont _start_cont: /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ @@ -1604,7 +1599,7 @@ relocate_code: * initialization, now running from RAM. */ - addi r0,r10,in_ram - _start + addi r0,r10,in_ram - _start_cont /* * As IVPR is going to point RAM address, From de14a5a95c14b0a5349c430ea35b8b07975f7ce5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:05:09 +0200 Subject: [PATCH 12/56] powerpc: mpc85xx: Rename _start_e500 symbol to _start MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The real entry point is _start_e500. There is no _start symbol at all. So rename _start_e500 to _start for convension that _start symbol is used as entry point. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/resetvec.S | 2 +- arch/powerpc/cpu/mpc85xx/start.S | 4 ++-- arch/powerpc/cpu/mpc85xx/u-boot.lds | 2 +- doc/README.mpc85xx | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/resetvec.S b/arch/powerpc/cpu/mpc85xx/resetvec.S index 29555d4a009..9a552f6624e 100644 --- a/arch/powerpc/cpu/mpc85xx/resetvec.S +++ b/arch/powerpc/cpu/mpc85xx/resetvec.S @@ -1,2 +1,2 @@ .section .resetvec,"ax" - b _start_e500 + b _start diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 07e855e89b4..2b2ad973599 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -70,9 +70,9 @@ */ .section .bootpg,"ax" - .globl _start_e500 + .globl _start -_start_e500: +_start: /* Enable debug exception */ li r1,MSR_DE mtmsr r1 diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 22bbac51aa3..17a0e631ca3 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -16,7 +16,7 @@ #endif OUTPUT_ARCH(powerpc) -ENTRY(_start_e500) +ENTRY(_start) PHDRS { diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx index 8464e7f4d8a..3c6ebbdb0e6 100644 --- a/doc/README.mpc85xx +++ b/doc/README.mpc85xx @@ -45,7 +45,7 @@ Note: Sequence number is in order of execution A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 1) TLB entry to overcome e500 v1/v2 debug restriction - Location : Label "_start_e500" + Location : Label "_start" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE Properties : 256K, AS0, I, IPROT @@ -91,7 +91,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 1) TLB entry to overcome e500 v1/v2 debug restriction - Location : Label "_start_e500" + Location : Label "_start" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB #if defined(CONFIG_NXP_ESBC) EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW From efd9914ffa05dc89f7d2830267b27ba2f06ecad1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:05:10 +0200 Subject: [PATCH 13/56] powerpc: mpc85xx: Show e500 core version MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Distinguish between e500v1 and e500v2. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index cc1d02df811..a82516a75bd 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -143,8 +143,10 @@ int checkcpu (void) printf("Core: "); switch(ver) { case PVR_VER_E500_V1: + puts("e500v1"); + break; case PVR_VER_E500_V2: - puts("e500"); + puts("e500v2"); break; case PVR_VER_E500MC: puts("e500mc"); From 0f58f033d410e91466723bb288d555c710de49fc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:16:59 +0200 Subject: [PATCH 14/56] mmc: fsl_esdhc_spl: pre-PBL: check for BOOT signature instead of MBR/DBR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pre-PBL BootROMs (MPC8536E, MPC8569E, P2020, P1011, P1012, P1013, P1020, P1021, P1022) require custom BOOT signature on sector 0 and MBR/DBR signature is not required at all. So add check for BOOT signature and remove check for MBR/DBR. This allows U-Boot SPL to load proper U-Boot on pre-PBL BootROMs platforms also from SD cards which do not have MBR/DBR signature on sector 0. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc_spl.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index bee76572ac6..109f558dcad 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -14,6 +14,8 @@ * on SDCard, so we must read the MBR to get the start address and code * length of the u-boot image, then calculate the address of the env. */ +#define ESDHC_BOOT_SIGNATURE_OFF 0x40 +#define ESDHC_BOOT_SIGNATURE 0x424f4f54 #define ESDHC_BOOT_IMAGE_SIZE 0x48 #define ESDHC_BOOT_IMAGE_ADDR 0x50 #define MBRDBR_BOOT_SIG_55 0x1fe @@ -61,6 +63,9 @@ void __noreturn mmc_boot(void) uchar *tmp_buf; u32 blklen; uchar val; +#ifndef CONFIG_SPL_FSL_PBL + u32 val32; +#endif uint i, byte_num; #endif u32 offset, code_len; @@ -94,16 +99,34 @@ void __noreturn mmc_boot(void) hang(); } +#ifdef CONFIG_SPL_FSL_PBL val = *(tmp_buf + MBRDBR_BOOT_SIG_55); if (0x55 != val) { - puts("spl: mmc signature is not valid!!\n"); + puts("spl: mmc MBR/DBR signature is not valid!!\n"); hang(); } val = *(tmp_buf + MBRDBR_BOOT_SIG_AA); if (0xAA != val) { - puts("spl: mmc signature is not valid!!\n"); + puts("spl: mmc MBR/DBR signature is not valid!!\n"); hang(); } +#else + /* + * Booting from On-Chip ROM (eSDHC or eSPI), Document Number: AN3659, Rev. 2, 06/2012. + * Pre-PBL BootROMs (MPC8536E, MPC8569E, P2020, P1011, P1012, P1013, P1020, P1021, P1022) + * require custom BOOT signature on sector 0 and MBR/DBR signature is not required at all. + */ + byte_num = 4; + val32 = 0; + for (i = 0; i < byte_num; i++) { + val = *(tmp_buf + ESDHC_BOOT_SIGNATURE_OFF + i); + val32 = (val32 << 8) + val; + } + if (val32 != ESDHC_BOOT_SIGNATURE) { + puts("spl: mmc BOOT signature is not valid!!\n"); + hang(); + } +#endif byte_num = 4; offset = 0; From a91998d8affc0405bafeade583204f66db81e252 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:17:00 +0200 Subject: [PATCH 15/56] mmc: fsl_esdhc_spl: pre-PBL: fix determining U-Boot size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In pre-PBL header is stored size of code which BootROM copies from SD card to L2/SRAM. This size has upper limit of L2 cache size. In most cases this is size of U-Boot SPL or size of L2 cache. Therefore this size in pre-PBL header cannot be used for determining size of proper U-Boot. So always use CONFIG_SYS_MMC_U_BOOT_SIZE for determining size of proper U-Boot which stored on SD card. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc_spl.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 109f558dcad..b87597a88e1 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -79,7 +79,6 @@ void __noreturn mmc_boot(void) #ifdef CONFIG_FSL_CORENET offset = CONFIG_SYS_MMC_U_BOOT_OFFS; - code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; #else blklen = mmc->read_bl_len; tmp_buf = malloc(blklen); @@ -135,18 +134,11 @@ void __noreturn mmc_boot(void) offset = (offset << 8) + val; } offset += CONFIG_SYS_MMC_U_BOOT_OFFS; - /* Get the code size from offset 0x48 */ - byte_num = 4; - code_len = 0; - for (i = 0; i < byte_num; i++) { - val = *(tmp_buf + ESDHC_BOOT_IMAGE_SIZE + i); - code_len = (code_len << 8) + val; - } - code_len -= CONFIG_SYS_MMC_U_BOOT_OFFS; +#endif /* * Load U-Boot image from mmc into RAM */ -#endif + code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, From 57d527e753bb5efe89fceea341e7d327bf58e312 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:17:01 +0200 Subject: [PATCH 16/56] mmc: fsl_esdhc_spl: Call mmc_init() before booting from SD card MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If env is stored on SD card then U-Boot SPL automatically calls mmc_init() before it is going to load proper U-Boot from SD card. If env is not stored on SD card then U-Boot SPL fails to read proper U-Boot from SD card due to missing mmc_init() call. So add missing mmc_init() call into fsl_esdhc_spl's mmc_boot() function. It fixes booting from SD card on P2020 boards without env support in SPL. mmc_init() returns early if card was already initialized, so there is no issue with calling this function more times. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc_spl.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index b87597a88e1..0146a231b22 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -77,6 +77,11 @@ void __noreturn mmc_boot(void) hang(); } + if (mmc_init(mmc)) { + puts("spl: mmc device init failed!\n"); + hang(); + } + #ifdef CONFIG_FSL_CORENET offset = CONFIG_SYS_MMC_U_BOOT_OFFS; #else From 48467e47698a27a2a32961bf8bdf19b0e236704c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:20:10 +0200 Subject: [PATCH 17/56] mmc: mmc_mode_name() is used also when LOGLEVEL >= LOGL_DEBUG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When CONFIG_LOGLEVEL is set to LOGL_DEBUG or higher then linker throws error about undefined symbol mmc_mode_name(). So compile mmc_mode_name() also when CONFIG_LOGLEVEL is set to LOGL_DEBUG or higher. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f6ccd837aa4..8a7d0739006 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -132,7 +132,7 @@ void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) } #endif -#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) +#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) || CONFIG_VAL(LOGLEVEL) >= LOGL_DEBUG const char *mmc_mode_name(enum bus_mode mode) { static const char *const names[] = { From d64a8fd0a9021ef0a87e6f3e315c8d65a8dd7bd0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:24:25 +0200 Subject: [PATCH 18/56] hwconfig: Allow to compile it without env support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When env support is disabled then usage of env_get() generates linker errors. So do not compile env_get() when env support is disabled (for example when disabled only in SPL). Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- common/hwconfig.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/hwconfig.c b/common/hwconfig.c index 63b3ccaf84e..43566b81bd4 100644 --- a/common/hwconfig.c +++ b/common/hwconfig.c @@ -83,7 +83,9 @@ static const char *__hwconfig(const char *opt, size_t *arglen, "and before environment is ready\n"); return NULL; } +#if CONFIG_IS_ENABLED(ENV_SUPPORT) env_hwconfig = env_get("hwconfig"); +#endif } if (env_hwconfig) { From 78cdaf405311682281d9c5f58dc0b4455e72da61 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:24:26 +0200 Subject: [PATCH 19/56] ddr: fsl: Allow to compile it without env support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When env support is disabled then usage of env_get_f() generates linker errors. So do not compile env_get_f() when env support is disabled (for example when disabled only in SPL). Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/ddr/fsl/options.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index c000a45f8ea..9555b9a29d4 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -761,7 +761,9 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, * Extract hwconfig from environment since we have not properly setup * the environment but need it for ddr config params */ +#if CONFIG_IS_ENABLED(ENV_SUPPORT) if (env_get_f("hwconfig", buf, sizeof(buf)) < 0) +#endif buf[0] = '\0'; #if defined(CONFIG_SYS_FSL_DDR3) || \ @@ -1408,7 +1410,9 @@ int fsl_use_spd(void) * Extract hwconfig from environment since we have not properly setup * the environment but need it for ddr config params */ +#if CONFIG_IS_ENABLED(ENV_SUPPORT) if (env_get_f("hwconfig", buf, sizeof(buf)) < 0) +#endif buf[0] = '\0'; /* if hwconfig is not enabled, or "sdram" is not defined, use spd */ From 03edf23376cd63142624bca8a58477e0c99f4cb0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:24:27 +0200 Subject: [PATCH 20/56] board: freescale: p1_p2_rdb_pc: Allow to compile it without env support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When env support is disabled then usage of env_init() or env_relocate() generates linker errors. So do not compile env_init() or env_relocate() in SPL code when env support is disabled in SPL. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/spl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index f855f3a81c3..22156f2824e 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -83,12 +83,15 @@ void board_init_r(gd_t *gd, ulong dest_addr) CONFIG_SPL_RELOC_MALLOC_SIZE); gd->flags |= GD_FLG_FULL_MALLOC_INIT; +#ifdef CONFIG_SPL_ENV_SUPPORT #ifndef CONFIG_SPL_NAND_BOOT env_init(); #endif +#endif #ifdef CONFIG_SPL_MMC_BOOT mmc_initialize(bd); #endif +#ifdef CONFIG_SPL_ENV_SUPPORT /* relocate environment function pointers etc. */ #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, @@ -98,6 +101,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #else env_relocate(); #endif +#endif #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) i2c_init_all(); From 77b0c4a6c6eeab642107c6d5051b8484db7cf723 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:42:25 +0200 Subject: [PATCH 21/56] powerpc: dts: p2020: Add fsl/p2020si-pre.dtsi and fsl/p2020si-post.dtsi symlinks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit P2020 DTS files in upstream Linux kernel use fsl/p2020si-pre.dtsi and fsl/p2020si-post.dtsi include device tree files. Add symlinks for these include device tree files into U-Boot powerpc directory and points them to U-Boot inline device tree files p2020.dtsi and p2020-post.dtsi. This allows to use P2020 DTS files from upstream Linux kernel in U-Boot. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/fsl/p2020si-post.dtsi | 1 + arch/powerpc/dts/fsl/p2020si-pre.dtsi | 1 + 2 files changed, 2 insertions(+) create mode 120000 arch/powerpc/dts/fsl/p2020si-post.dtsi create mode 120000 arch/powerpc/dts/fsl/p2020si-pre.dtsi diff --git a/arch/powerpc/dts/fsl/p2020si-post.dtsi b/arch/powerpc/dts/fsl/p2020si-post.dtsi new file mode 120000 index 00000000000..b51ebf58b7a --- /dev/null +++ b/arch/powerpc/dts/fsl/p2020si-post.dtsi @@ -0,0 +1 @@ +../p2020-post.dtsi \ No newline at end of file diff --git a/arch/powerpc/dts/fsl/p2020si-pre.dtsi b/arch/powerpc/dts/fsl/p2020si-pre.dtsi new file mode 120000 index 00000000000..1e4b16fbe46 --- /dev/null +++ b/arch/powerpc/dts/fsl/p2020si-pre.dtsi @@ -0,0 +1 @@ +../p2020.dtsi \ No newline at end of file From cfbf84330f2669a8c6570aec71e2af0ad2ea055b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Sun, 3 Apr 2022 00:42:26 +0200 Subject: [PATCH 22/56] powerpc: dts: p2020: Add serial0 and serial1 via pq3-duart-0.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Import pq3-duart-0.dtsi device tree include file from upstream Linux kernel for P2020. This allows U-Boot to use P2020 device tree files from upstream Linux kernel which reference serial0 or serial1 devices. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 1 + arch/powerpc/dts/pq3-duart-0.dtsi | 51 +++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/powerpc/dts/pq3-duart-0.dtsi diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 6d46f7d8dd7..8d30fa212c4 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -49,6 +49,7 @@ /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" +/include/ "pq3-duart-0.dtsi" /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-1.dtsi" diff --git a/arch/powerpc/dts/pq3-duart-0.dtsi b/arch/powerpc/dts/pq3-duart-0.dtsi new file mode 100644 index 00000000000..5e268fdb9d1 --- /dev/null +++ b/arch/powerpc/dts/pq3-duart-0.dtsi @@ -0,0 +1,51 @@ +/* + * PQ3 DUART device tree stub [ controller @ offset 0x4000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <0>; + interrupts = <42 2 0 0>; +}; + +serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <0>; + interrupts = <42 2 0 0>; +}; From 974f66a4700ca4e433e0e39526ac5bd3012cbe43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 4 Apr 2022 18:17:18 +0200 Subject: [PATCH 23/56] mtd: rawnand: fsl_elbc: Implement RNDOUT command MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is needed for SW ECC. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mtd/nand/raw/fsl_elbc_nand.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index ddfd75d32d0..f8698ec0158 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -312,6 +312,14 @@ static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, fsl_elbc_run_command(mtd); return; + /* RNDOUT moves the pointer inside the page */ + case NAND_CMD_RNDOUT: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n", + column); + + ctrl->index = column; + return; + /* READOOB reads only the OOB because no ECC is performed. */ case NAND_CMD_READOOB: vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" From da98ddaf732098b30ee4169f4fa01059261fa9ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 4 Apr 2022 18:17:19 +0200 Subject: [PATCH 24/56] mtd: rawnand: fsl_elbc: Add device tree support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This allows boards to specify NAND settings via standard DT properties. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mtd/nand/raw/Kconfig | 4 +++ drivers/mtd/nand/raw/fsl_elbc_nand.c | 42 ++++++++++++++++++++++++++-- 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 1eab21e2064..d75f371c951 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -158,6 +158,10 @@ config NAND_FSL_ELBC help Enable the Freescale Enhanced Local Bus Controller FCM NAND driver. +config NAND_FSL_ELBC_DT + bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)" + depends on NAND_FSL_ELBC + config NAND_FSL_IFC bool "Support Freescale Integrated Flash Controller NAND driver" select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index f8698ec0158..f8d2bdfb130 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -20,6 +20,10 @@ #include #include +#ifdef CONFIG_NAND_FSL_ELBC_DT +#include +#endif + #ifdef VERBOSE_DEBUG #define DEBUG_ELBC #define vdbg(format, arg...) printf("DEBUG: " format, ##arg) @@ -664,7 +668,7 @@ static void fsl_elbc_ctrl_init(void) elbc_ctrl->addr = NULL; } -static int fsl_elbc_chip_init(int devnum, u8 *addr) +static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) { struct mtd_info *mtd; struct nand_chip *nand; @@ -712,6 +716,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) elbc_ctrl->chips[priv->bank] = priv; /* fill in nand_chip structure */ + nand->flash_node = flash_node; + /* set up function call table */ nand->read_byte = fsl_elbc_read_byte; nand->write_buf = fsl_elbc_write_buf; @@ -804,6 +810,8 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) return 0; } +#ifndef CONFIG_NAND_FSL_ELBC_DT + #ifndef CONFIG_SYS_NAND_BASE_LIST #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #endif @@ -816,5 +824,35 @@ void board_nand_init(void) int i; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - fsl_elbc_chip_init(i, (u8 *)base_address[i]); + fsl_elbc_chip_init(i, (u8 *)base_address[i], ofnode_null()); } + +#else + +static int fsl_elbc_nand_probe(struct udevice *dev) +{ + return fsl_elbc_chip_init(0, (void *)dev_read_addr(dev), dev_ofnode(dev)); +} + +static const struct udevice_id fsl_elbc_nand_dt_ids[] = { + { .compatible = "fsl,elbc-fcm-nand", }, + {} +}; + +U_BOOT_DRIVER(fsl_elbc_nand) = { + .name = "fsl_elbc_nand", + .id = UCLASS_MTD, + .of_match = fsl_elbc_nand_dt_ids, + .probe = fsl_elbc_nand_probe, +}; + +void board_nand_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(fsl_elbc_nand), &dev); + if (ret && ret != -ENODEV) + printf("Failed to initialize fsl_elbc_nand NAND controller. (error %d)\n", ret); +} +#endif From c9ea9019c5aaeac474d2a243dc1482e1db2b7c6d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 4 Apr 2022 18:17:20 +0200 Subject: [PATCH 25/56] mtd: rawnand: fsl_elbc: Use ECC configuration from device tree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initialize ECC configuration after nand_scan_ident() call and only in case nand_scan_ident() have not done it. nand_scan_ident() fills ECC configuration from device tree. Fixes usage of NAND_ECC_SOFT_BCH when it is specified in device tree. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mtd/nand/raw/fsl_elbc_nand.c | 55 +++++++++++++++------------- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index f8d2bdfb130..e734139b5ea 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -737,37 +737,40 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) nand->controller = &elbc_ctrl->controller; nand_set_controller_data(nand, priv); - nand->ecc.read_page = fsl_elbc_read_page; - nand->ecc.write_page = fsl_elbc_write_page; - nand->ecc.write_subpage = fsl_elbc_write_subpage; - priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT); - /* If CS Base Register selects full hardware ECC then use it */ - if ((br & BR_DECC) == BR_DECC_CHK_GEN) { - nand->ecc.mode = NAND_ECC_HW; - - nand->ecc.layout = (priv->fmr & FMR_ECCM) ? - &fsl_elbc_oob_sp_eccm1 : - &fsl_elbc_oob_sp_eccm0; - - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.steps = 1; - nand->ecc.strength = 1; - } else { - /* otherwise fall back to software ECC */ -#if defined(CONFIG_NAND_ECC_BCH) - nand->ecc.mode = NAND_ECC_SOFT_BCH; -#else - nand->ecc.mode = NAND_ECC_SOFT; -#endif - } - ret = nand_scan_ident(mtd, 1, NULL); if (ret) return ret; + /* If nand_scan_ident() has not selected ecc.mode, do it now */ + if (nand->ecc.mode == NAND_ECC_NONE) { + /* If CS Base Register selects full hardware ECC then use it */ + if ((br & BR_DECC) == BR_DECC_CHK_GEN) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = (priv->fmr & FMR_ECCM) ? + &fsl_elbc_oob_sp_eccm1 : + &fsl_elbc_oob_sp_eccm0; + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.steps = 1; + nand->ecc.strength = 1; + } else { + /* otherwise fall back to software ECC */ +#if defined(CONFIG_NAND_ECC_BCH) + nand->ecc.mode = NAND_ECC_SOFT_BCH; +#else + nand->ecc.mode = NAND_ECC_SOFT; +#endif + } + } + + if (nand->ecc.mode == NAND_ECC_HW) { + nand->ecc.read_page = fsl_elbc_read_page; + nand->ecc.write_page = fsl_elbc_write_page; + nand->ecc.write_subpage = fsl_elbc_write_subpage; + } + /* Large-page-specific setup */ if (mtd->writesize == 2048) { setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or, @@ -785,7 +788,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr, ofnode flash_node) priv->fmr |= FMR_ECCM; /* adjust ecc setup if needed */ - if ((br & BR_DECC) == BR_DECC_CHK_GEN) { + if (nand->ecc.mode == NAND_ECC_HW) { nand->ecc.steps = 4; nand->ecc.layout = (priv->fmr & FMR_ECCM) ? &fsl_elbc_oob_lp_eccm1 : From 06ef911447fce6c3321e303e968dbb1945b23d38 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 4 Apr 2022 18:17:21 +0200 Subject: [PATCH 26/56] mtd: nand: raw: Add support for DT property nand-ecc-algo=bch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Linux kernel DT schema nand-controller.yaml, using DT property nand-ecc-algo=bch is the correct way for specifying BCH as ECC algorithm. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mtd/nand/raw/nand_base.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index a007603df14..6f81257cf1f 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4598,6 +4598,12 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode nod ecc_mode = NAND_ECC_SOFT_BCH; } + if (ecc_mode == NAND_ECC_SOFT) { + str = ofnode_read_string(node, "nand-ecc-algo"); + if (str && !strcmp(str, "bch")) + ecc_mode = NAND_ECC_SOFT_BCH; + } + ecc_strength = ofnode_read_s32_default(node, "nand-ecc-strength", -1); ecc_step = ofnode_read_s32_default(node, From 44564e79eb2eac4b38f5493748018906e7239e2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 4 Apr 2022 18:32:13 +0200 Subject: [PATCH 27/56] mmc: fsl_esdhc: Define macro ESDHCCTL_SNOOP for Snoop attribute MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc.c | 2 +- include/fsl_esdhc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 05a6d0ce156..fdf2cc290e0 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -724,7 +724,7 @@ static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs) setbits_be32(&sysconf->sdhccr, 0x02000000); #else - esdhc_write32(®s->esdhcctl, 0x00000040); + esdhc_write32(®s->esdhcctl, ESDHCCTL_SNOOP); #endif } diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index f86afe5dad8..7ab1460abc6 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -76,6 +76,7 @@ /* eSDHC control register */ #define ESDHCCTL 0x0002e40c +#define ESDHCCTL_SNOOP (0x00000040) #define ESDHCCTL_PCS (0x00080000) #define ESDHCCTL_FAF (0x00040000) From 0980cbba7b3cdec23bafb9cf6dbedc22979a38a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 4 Apr 2022 18:33:11 +0200 Subject: [PATCH 28/56] mmc: fsl_esdhc_spl: pre-PBL: implement redundancy support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit QorIQ pre-PBL BootROM scans first 24 SD card sectors (each with fixed 512 bytes length) for boot signature. Implement same redundancy behavior in fsl_esdhc_spl driver to allow loading proper U-Boot when boot sector is not the first one. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- drivers/mmc/fsl_esdhc_spl.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 0146a231b22..ea8f4cd6696 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -20,7 +20,6 @@ #define ESDHC_BOOT_IMAGE_ADDR 0x50 #define MBRDBR_BOOT_SIG_55 0x1fe #define MBRDBR_BOOT_SIG_AA 0x1ff -#define CONFIG_CFG_DATA_SECTOR 0 void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst) @@ -62,11 +61,13 @@ void __noreturn mmc_boot(void) #ifndef CONFIG_FSL_CORENET uchar *tmp_buf; u32 blklen; + u32 blk_off; uchar val; #ifndef CONFIG_SPL_FSL_PBL u32 val32; #endif uint i, byte_num; + u32 sector; #endif u32 offset, code_len; struct mmc *mmc; @@ -86,30 +87,37 @@ void __noreturn mmc_boot(void) offset = CONFIG_SYS_MMC_U_BOOT_OFFS; #else blklen = mmc->read_bl_len; + if (blklen < 512) + blklen = 512; tmp_buf = malloc(blklen); if (!tmp_buf) { puts("spl: malloc memory failed!!\n"); hang(); } + + sector = 0; +again: memset(tmp_buf, 0, blklen); /* * Read source addr from sd card */ - err = mmc->block_dev.block_read(&mmc->block_dev, - CONFIG_CFG_DATA_SECTOR, 1, tmp_buf); + blk_start = (sector * 512) / mmc->read_bl_len; + blk_off = (sector * 512) % mmc->read_bl_len; + blk_cnt = DIV_ROUND_UP(512, mmc->read_bl_len); + err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, tmp_buf); if (err != 1) { puts("spl: mmc read failed!!\n"); hang(); } #ifdef CONFIG_SPL_FSL_PBL - val = *(tmp_buf + MBRDBR_BOOT_SIG_55); + val = *(tmp_buf + blk_off + MBRDBR_BOOT_SIG_55); if (0x55 != val) { puts("spl: mmc MBR/DBR signature is not valid!!\n"); hang(); } - val = *(tmp_buf + MBRDBR_BOOT_SIG_AA); + val = *(tmp_buf + blk_off + MBRDBR_BOOT_SIG_AA); if (0xAA != val) { puts("spl: mmc MBR/DBR signature is not valid!!\n"); hang(); @@ -123,10 +131,13 @@ void __noreturn mmc_boot(void) byte_num = 4; val32 = 0; for (i = 0; i < byte_num; i++) { - val = *(tmp_buf + ESDHC_BOOT_SIGNATURE_OFF + i); + val = *(tmp_buf + blk_off + ESDHC_BOOT_SIGNATURE_OFF + i); val32 = (val32 << 8) + val; } if (val32 != ESDHC_BOOT_SIGNATURE) { + /* BOOT signature may be on the first 24 sectors (each being 512 bytes) */ + if (++sector < 24) + goto again; puts("spl: mmc BOOT signature is not valid!!\n"); hang(); } @@ -135,7 +146,7 @@ void __noreturn mmc_boot(void) byte_num = 4; offset = 0; for (i = 0; i < byte_num; i++) { - val = *(tmp_buf + ESDHC_BOOT_IMAGE_ADDR + i); + val = *(tmp_buf + blk_off + ESDHC_BOOT_IMAGE_ADDR + i); offset = (offset << 8) + val; } offset += CONFIG_SYS_MMC_U_BOOT_OFFS; From 7d1d31db91d897380bbbd88d448ddb72f8e816a2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 5 Apr 2022 11:15:21 +0200 Subject: [PATCH 29/56] powerpc: dts: p2020: Add localbus node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This node is required for NAND and NOR support. Node is taken from the upstream Linux kernel DTS file. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 7 +++++++ arch/powerpc/dts/p2020rdb-pc.dts | 4 ++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 4 ++++ 3 files changed, 15 insertions(+) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 8d30fa212c4..0a9e81a4248 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -85,3 +85,10 @@ device_type = "pci"; bus-range = <0x0 0xff>; }; + +&lbc { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus"; + interrupts = <19 2 0 0>; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index b37931ac449..67fa340d09d 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -15,6 +15,10 @@ #size-cells = <2>; interrupt-parent = <&mpic>; + lbc: localbus@ffe05000 { + reg = <0 0xffe05000 0 0x1000>; + }; + soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index ecdc022d997..6f251960031 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -15,6 +15,10 @@ #size-cells = <2>; interrupt-parent = <&mpic>; + lbc: localbus@fffe05000 { + reg = <0xf 0xffe05000 0 0x1000>; + }; + soc: soc@fffe00000 { ranges = <0x0 0xf 0xffe00000 0x100000>; }; From 74b7d69e613ac8fb7dcc21ea5248237e60b2cf1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 5 Apr 2022 11:23:25 +0200 Subject: [PATCH 30/56] powerpc: dts: p1020/p2020: Fix esdhc node name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For compatibility with Linux kernel DTS files and also with other U-Boot powerpc DTS files, rename esdhc@2e000 node to sdhc@2e000 in p1020-post.dtsi and p2020-post.dtsi include files. Linux kernel DTS files which include these dtsi files, expect that esdhc node has name sdhc@2e000 and do not work with other node names. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p1020-post.dtsi | 2 +- arch/powerpc/dts/p2020-post.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 03b68869918..668ca0fa07e 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -37,7 +37,7 @@ last-interrupt-source = <255>; }; - esdhc: esdhc@2e000 { + esdhc: sdhc@2e000 { compatible = "fsl,esdhc"; reg = <0x2e000 0x1000>; /* Filled in by U-Boot */ diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 0a9e81a4248..6debae7720a 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -31,7 +31,7 @@ last-interrupt-source = <255>; }; - esdhc: esdhc@2e000 { + esdhc: sdhc@2e000 { compatible = "fsl,esdhc"; reg = <0x2e000 0x1000>; /* Filled in by U-Boot */ From e8c0e0064c8a7b0665fd1393c2e3266f80e884a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 5 Apr 2022 15:12:30 +0200 Subject: [PATCH 31/56] powerpc: mpc85xx: Fix CONFIG_OF_SEPARATE support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently CONFIG_OF_SEPARATE is completely broken and U-Boot for some mpc85xx board (e.g. P2020) has to be compiled with CONFIG_OF_EMBED. Otherwise it crashes during early init. When debug console is enabled and all debug logging options are turned on then U-Boot on P2020 with CONFIG_OF_SEPARATE prints following error: No valid device tree binary found at 110dc300 initcall sequence 110d3560 failed at call 1109535c (err=-1) ### ERROR ### Please RESET the board ### Problem is with appended DTB. When CONFIG_SYS_MPC85XX_NO_RESETVEC is set U-Boot binary image without DTB ends immediately after the .u_boot_list section. At this position is defined _end symbol at which U-Boot expects start of the appended DTB. Problem is that after .u_boot_list section are in linker script defined another sections with 256 byte long padding which are completely empty. During conversion of U-Boot ELF binary to RAW binary u-boot-nodtb.bin, objcopy removes trailing zero padding and therefore DTB is appended at wrong position. Changing alignment from 256 bytes to 4 bytes fixes this issue. And appended DTB is finally at he correct position. With this fix U-Boot on P2020 with CONFIG_OF_SEPARATE option starts working again. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot.lds | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 17a0e631ca3..48509dbdae0 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -75,11 +75,11 @@ SECTIONS __ex_table : { *(__ex_table) } __stop___ex_table = .; - . = ALIGN(256); + . = ALIGN(4); __init_begin = .; .text.init : { *(.text.init) } .data.init : { *(.data.init) } - . = ALIGN(256); + . = ALIGN(4); __init_end = .; _end = .; From 0038f2362a24478a6c9a7fb186887851f2b32512 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 25 Apr 2022 09:32:03 +0530 Subject: [PATCH 32/56] powerpc: mpc85xx: Remove u-boot-nand_spl.lds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit mpc85xx SPL NAND linker script u-boot-nand_spl.lds is not used since Jun 2014 commit 0234446fd171 ("nand_spl: remove MPC8536DS support"). Remove it. Signed-off-by: Pali Rohár [Rebased] Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds | 68 -------------------- 1 file changed, 68 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds deleted file mode 100644 index a2193bf7680..00000000000 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de - * - * Copyright 2009 Freescale Semiconductor, Inc. - */ - -#include "config.h" - -OUTPUT_ARCH(powerpc) -SECTIONS -{ - . = 0xfff00000; - .text : { - *(.text*) - } - _etext = .; - - .reloc : { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - . = ALIGN(8); - .data : { - *(.rodata*) - *(.data*) - *(.sdata*) - } - _edata = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(8); - __init_begin = .; - __init_end = .; - _end = .; -#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ - .bootpg ADDR(.text) + 0x1000 : - { - start.o (.bootpg) - } -#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */ -#elif defined(CONFIG_FSL_ELBC) -#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */ -#else -#error unknown NAND controller -#endif - .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { - KEEP(*(.resetvec)) - } = 0xffff - - __bss_start = .; - .bss : { - *(.sbss*) - *(.bss*) - } - __bss_end = .; -} -ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big"); From ab37df9d221e12adf709c7391c001b9dd5d33606 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 25 Apr 2022 14:21:20 +0530 Subject: [PATCH 33/56] powerpc: mpc85xx: Remove duplicate u-boot-nand.lds Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot-nand.lds | 97 ------------------------ configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 - configs/P1010RDB-PA_NAND_defconfig | 2 - configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 - configs/P1010RDB-PB_NAND_defconfig | 2 - configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 - configs/P1020RDB-PC_NAND_defconfig | 2 - configs/P1020RDB-PD_NAND_defconfig | 2 - configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 - configs/P2020RDB-PC_NAND_defconfig | 2 - configs/T1024RDB_NAND_defconfig | 2 - configs/T1042D4RDB_NAND_defconfig | 2 - configs/T2080QDS_NAND_defconfig | 2 - configs/T2080RDB_NAND_defconfig | 2 - configs/T2080RDB_revD_NAND_defconfig | 2 - include/configs/P1010RDB.h | 4 + include/configs/T102xRDB.h | 3 + include/configs/T104xRDB.h | 3 + include/configs/T208xQDS.h | 3 + include/configs/T208xRDB.h | 3 + include/configs/p1_p2_rdb_pc.h | 4 + 21 files changed, 20 insertions(+), 125 deletions(-) delete mode 100644 arch/powerpc/cpu/mpc85xx/u-boot-nand.lds diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds deleted file mode 100644 index 75b0285e4e5..00000000000 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2012 Freescale Semiconductor, Inc. - */ - -#include "config.h" - -#ifndef CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#endif - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -PHDRS -{ - text PT_LOAD; - bss PT_LOAD; -} - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .text : - { - *(.text*) - } :text - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } :text - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - _end = .; - - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - - . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.sbss*) - *(.bss*) - *(COMMON) - } :bss - - . = ALIGN(4); - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index de67892a456..b44264f41d6 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -16,8 +16,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index c980adffffc..9cb7f55ecf4 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PA=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index ac56d416670..67659cfc906 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -16,8 +16,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 0954e76bb80..18215d8f358 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB_PB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index f739ca0977f..56b984e5ae6 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -16,8 +16,6 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index be29f9eac4f..00d847d50af 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 38e5633f82c..0d713624d48 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 905b1edc2b2..e167468ed38 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -16,8 +16,6 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 5b140525f02..29d90c91400 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -15,8 +15,6 @@ CONFIG_SPL=y CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index a5d80c9857b..c86c5c15309 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -14,8 +14,6 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 1ec838aaa0f..978c6c0bb65 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -11,8 +11,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 4721795c5eb..f5fc3e19b58 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -18,8 +18,6 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y CONFIG_TARGET_T2080QDS=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index bef6fe8f59a..1c73bfb3d01 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -17,8 +17,6 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T2080RDB=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 10f7e2cd18b..e9d78e92c95 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -18,8 +18,6 @@ CONFIG_TARGET_T2080RDB=y CONFIG_T2080RDB_REV_D=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 0d8f13eeb06..0c19b92940e 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -81,6 +81,10 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#else +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_TPL_PAD_TO 0x20000 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index bedd931b186..e7cc39e78a9 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -36,6 +36,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8ef6068cb91..de31f695c60 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -40,6 +40,9 @@ #endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 5a338f743a3..82e0fc46c7b 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -44,6 +44,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 3c13905729a..94385443253 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -39,6 +39,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 17b9021fbf8..81dc0177c0c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -111,6 +111,10 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#else +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif /* not CONFIG_TPL_BUILD */ #define CONFIG_SPL_PAD_TO 0x20000 From c45f000f294e096f6f5060bd528b65d14f6c6f12 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 5 Apr 2022 15:12:33 +0200 Subject: [PATCH 34/56] powerpc: mpc85xx: Remove useless SIZEOF_HEADERS and .interp from ld script MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit .interp section is not available in output ELF binary and SIZEOF_HEADERS is needed at all. There is no change in generated u-boot.bin binary. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot.lds | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 48509dbdae0..565d5deb530 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -27,8 +27,6 @@ PHDRS SECTIONS { /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } .text : { *(.text*) From 1b780b654f20055f40a049da4f2ef12207757690 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 5 Apr 2022 15:12:34 +0200 Subject: [PATCH 35/56] powerpc: mpc85xx: Put bss after image when not including reset vector MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linker knows exact size of the image, so there is no need to use CONFIG_SYS_MONITOR_LEN macro (which should be upper limit). Remove usage of CONFIG_SYS_MONITOR_LEN macro to simplify setup. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot.lds | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 565d5deb530..9d0f0d58d80 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -11,10 +11,6 @@ #define RESET_VECTOR_ADDRESS 0xfffffffc #endif -#ifndef CONFIG_SYS_MONITOR_LEN -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#endif - OUTPUT_ARCH(powerpc) ENTRY(_start) @@ -86,7 +82,7 @@ SECTIONS { KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) } :text = 0xffff - . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN; + . = _end; #else .bootpg RESET_VECTOR_ADDRESS - 0xffc : { From 1245c6e2582cb67db2a84e60a61cfe5a8d77e068 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Tue, 5 Apr 2022 15:12:35 +0200 Subject: [PATCH 36/56] powerpc: mpc85xx: Define linker sections in ascending order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is too confusing if sections are defined in non-ascending order. Also linker has to go backward and then again forward when generating final binary. To make future changes easier, define all linker sections in ascending order. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 20 +++++++++++--------- arch/powerpc/cpu/mpc85xx/u-boot.lds | 15 ++++++++------- 2 files changed, 19 insertions(+), 16 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 27a5fe6306a..1b4d1e05a4a 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -18,6 +18,13 @@ PHDRS #endif SECTIONS { +/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg IMAGE_TEXT_BASE - 0x1000 : + { + KEEP(*(.bootpg)) + } :text = 0xffff +#endif . = IMAGE_TEXT_BASE; .text : { *(.text*) @@ -67,18 +74,13 @@ SECTIONS __bss_end = .; #endif -/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(*(.bootpg)) - } :text = 0xffff -#else +/* For nor and nand is needed the SPL with section .resetvec */ +#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */ #ifndef BOOT_PAGE_OFFSET #define BOOT_PAGE_OFFSET 0x1000 #endif - .bootpg ADDR(.text) + BOOT_PAGE_OFFSET : + .bootpg IMAGE_TEXT_BASE + BOOT_PAGE_OFFSET : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) } @@ -90,7 +92,7 @@ SECTIONS #else #error unknown NAND controller #endif - .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : { + .resetvec IMAGE_TEXT_BASE + RESET_VECTOR_OFFSET : { KEEP(*(.resetvec)) } = 0xffff #endif diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 9d0f0d58d80..e1bbee43bcb 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -23,6 +23,13 @@ PHDRS SECTIONS { /* Read-only sections, merged into text segment: */ +#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC + .bootpg CONFIG_SYS_TEXT_BASE - 0x1000 : + { + KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) + } :text = 0xffff + . = CONFIG_SYS_TEXT_BASE; +#endif .text : { *(.text*) @@ -77,13 +84,7 @@ SECTIONS __init_end = .; _end = .; -#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC - .bootpg ADDR(.text) - 0x1000 : - { - KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) - } :text = 0xffff - . = _end; -#else +#ifndef CONFIG_SYS_MPC85XX_NO_RESETVEC .bootpg RESET_VECTOR_ADDRESS - 0xffc : { arch/powerpc/cpu/mpc85xx/start.o (.bootpg) From ccad59dc5cc5f4ba5151a0f9aac2df7f441fb7b2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:14 +0200 Subject: [PATCH 37/56] board: freescale: p1_p2_rdb_pc: Do not hang in checkboard() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Like in all other checks in checkboard() function, do not hang on error. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index b6f0d204267..1e6dfe87d8b 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -191,7 +191,7 @@ int checkboard(void) if (ret) { printf("%s: Cannot find udev for a bus %d\n", __func__, bus_num); - return -ENXIO; + return 0; /* Don't want to hang() on this error */ } if (dm_i2c_read(dev, 0, &in, 1) < 0 || From 4aceaec585d925eed468c3bd25fdcdfd7568033e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:15 +0200 Subject: [PATCH 38/56] board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As written in comment, P2020 has two possible SD switch configurations. Extend code to detect both of them. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 ++++ include/configs/p1_p2_rdb_pc.h | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 1e6dfe87d8b..dde0c1dcd2d 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -216,6 +216,10 @@ int checkboard(void) puts("rom_loc: "); if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) { puts("sd"); +#ifdef __SW_BOOT_SD2 + } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD2) { + puts("sd"); +#endif #ifdef __SW_BOOT_SPI } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) { puts("spi"); diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 81dc0177c0c..cc703309e3e 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -57,7 +57,8 @@ #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_SPI 0x28 -#define __SW_BOOT_SD 0x68 /* or 0x18 */ +#define __SW_BOOT_SD 0x68 +#define __SW_BOOT_SD2 0x18 #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 #define CONFIG_SYS_L2_SIZE (512 << 10) From 0992c2be776b51c5ca7d85147050908fbcc96d80 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:17 +0200 Subject: [PATCH 39/56] board: freescale: p1_p2_rdb_pc: Do not set MPC85xx_PMUXCR_SDHC_WP bit when SDHC_WP is used as GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When MPC85xx_PMUXCR_SDHC_WP is set then SDHC controller automatically makes inserted SD card readonly if GPIO[9] is active. In some design GPIO[9] pin does not have to be connected to SD card write-protect pin and can be used as GPIO. So do not set MPC85xx_PMUXCR_SDHC_WP bit when GPIO[9] is not used for SDHC_WP functionality. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index dde0c1dcd2d..bed2033e36f 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -147,8 +147,10 @@ int board_early_init_f(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - setbits_be32(&gur->pmuxcr, - (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD); +#ifndef SDHC_WP_IS_GPIO + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_WP); +#endif clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); From 0b30cb3de70fbaa4525d169a6fc09f732b290d97 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:18 +0200 Subject: [PATCH 40/56] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded attribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and also allow speculative loading (by not setting Guarded attribute). Also enable Memory Coherency attribute for second 1G SDRAM map. In commit 316f0d0f8f3c ("powerpc: mpc85xx: Fix static TLB table for SDRAM") it was enabled for all SDRAM maps on all other boards, just missed this one case. As a last thing, first 1G SDRAM map has wrong comment, so adjust it. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/tlb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index fcd7a55199f..5931ec650bd 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -79,16 +79,16 @@ struct fsl_e_tlb_entry tlb_table[] = { #if defined(CONFIG_SYS_RAMBOOT) || \ (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR)) - /* *I*G - eSDHC/eSPI/NAND boot */ + /* **M** - 1G DDR for eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), #if defined(CONFIG_TARGET_P1020RDB_PD) - /* 2G DDR on P1020MBG, map the second 1G */ + /* **M** - 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 9, BOOKE_PAGESZ_1G, 1), #endif #endif /* RAMBOOT/SPL */ From 71dcf8128c39c81edfc4ccb10f9463837df5d37d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:19 +0200 Subject: [PATCH 41/56] board: freescale: p1_p2_rdb_pc: Move ifdef for USB/eLBC check to correct place MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Whole section about USB/eLBC configuration seems to be P1020 specific. So add ifdefs to not compile it on other platforms (e.g. P2020). Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index bed2033e36f..6665aa4ba94 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -359,9 +359,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) const char *soc_usb_compat = "fsl-usb2-dr"; int usb_err, usb1_off, usb2_off; -#endif #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) int err; +#endif #endif ft_cpu_setup(blob, bd); @@ -380,6 +380,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fsl_fdt_fixup_dr_usb(blob, bd); #endif +#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) /* Delete eLBC node as it is muxed with USB2 controller */ if (hwconfig("usb2")) { @@ -401,7 +402,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) } #endif -#if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC) /* Delete USB2 node as it is muxed with eLBC */ usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat); From ac56055c41ae56756ee07805f998eaf9bc33f332 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:20 +0200 Subject: [PATCH 42/56] board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not stringify env $vscfw_addr two times (once implicitly via string operator "" and second time explicitly via __stringify() macro) and allow to compile U-Boot without CONFIG_VSC7385_ENET (when __VSCFW_ADDR was not defined and so macro name was stringified into CONFIG_EXTRA_ENV_SETTINGS). Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- include/configs/p1_p2_rdb_pc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index cc703309e3e..c3df6381835 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -325,7 +325,7 @@ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET -#define __VSCFW_ADDR "vscfw_addr=ef000000" +#define __VSCFW_ADDR "vscfw_addr=ef000000\0" #define CONFIG_SYS_VSC7385_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT @@ -344,6 +344,10 @@ #define CONFIG_VSC7385_IMAGE_SIZE 8192 #endif +#ifndef __VSCFW_ADDR +#define __VSCFW_ADDR "" +#endif + /* * Config the L2 Cache as L2 SRAM */ @@ -581,7 +585,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "ramdisk_size=120000\0" \ "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ -__stringify(__VSCFW_ADDR)"\0" \ +__VSCFW_ADDR \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ From 6496a89a5723a24dfaaf904384177f4119cae2c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:21 +0200 Subject: [PATCH 43/56] board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace hardcoded boot i2c bus num and address by existing macros when generating env for CONFIG_EXTRA_ENV_SETTINGS. Same macros are used in U-Boot board code when reading information from boot i2c data. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- include/configs/p1_p2_rdb_pc.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c3df6381835..08e3f8de030 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -535,28 +535,28 @@ #ifdef __SW_BOOT_NOR #define __NOR_RST_CMD \ -norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_SPI #define __SPI_RST_CMD \ -spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_SD #define __SD_RST_CMD \ -sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_NAND #define __NAND_RST_CMD \ -nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_PCIE #define __PCIE_RST_CMD \ -pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -583,9 +583,9 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "nandbootaddr=100000\0" \ "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ -"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ -"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ __VSCFW_ADDR \ +"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ +"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ From c7d0295c25c1a4d287eb5126e78b6d380893e141 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:22 +0200 Subject: [PATCH 44/56] board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace hardcoded i2c hex values for NOR banks by named SW macros in map_lowernorbank/map_uppernorbank env commands. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- include/configs/p1_p2_rdb_pc.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 08e3f8de030..f6ecf2a7a8b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -21,6 +21,9 @@ #define __SW_BOOT_SD 0x9c #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -46,6 +49,9 @@ #define __SW_BOOT_SD 0x24 #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -61,6 +67,9 @@ #define __SW_BOOT_SD2 0x18 #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (512 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -584,8 +593,8 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ +"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ +"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ From ec52b55b93dda92b50a24662ce7a5c9a01e4229b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:50 +0200 Subject: [PATCH 45/56] powerpc: dts: p2020: Add gpio-controller@fc00 node via pq3-gpio-0.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Import pq3-gpio-0.dtsi device tree include file from upstream Linux kernel for P2020. This allows U-Boot to use P2020 device tree files from upstream Linux kernel which reference gpio-controller@fc00 device. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 1 + arch/powerpc/dts/pq3-gpio-0.dtsi | 41 ++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) create mode 100644 arch/powerpc/dts/pq3-gpio-0.dtsi diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 6debae7720a..804db73c377 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -50,6 +50,7 @@ /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" /include/ "pq3-duart-0.dtsi" +/include/ "pq3-gpio-0.dtsi" /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-1.dtsi" diff --git a/arch/powerpc/dts/pq3-gpio-0.dtsi b/arch/powerpc/dts/pq3-gpio-0.dtsi new file mode 100644 index 00000000000..a1b48546b02 --- /dev/null +++ b/arch/powerpc/dts/pq3-gpio-0.dtsi @@ -0,0 +1,41 @@ +/* + * PQ3 GPIO device tree stub [ controller @ offset 0xfc00 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +gpio-controller@fc00 { + #gpio-cells = <2>; + compatible = "fsl,pq3-gpio"; + reg = <0xfc00 0x100>; + interrupts = <47 0x2 0 0>; + gpio-controller; +}; From 1a0800ac40c0bd65fbd12b2e00ad2b2f2067530b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:51 +0200 Subject: [PATCH 46/56] powerpc: dts: p2020: Make PCIe nodes compatible for Linux kernel driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux P2020 PCIe kernel driver uses compatible string fsl,mpc8548-pcie and needs more DT properties. Copy P2020 PCIe nodes and definitions from upstream Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 65 ++++++++++++++++++++++++++++++-- 1 file changed, 62 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 804db73c377..6eb6fedd415 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -59,32 +59,91 @@ /* PCIe controller base address 0x8000 */ &pci2 { - compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie"; law_trgt_if = <0>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <24 2 0 0>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <24 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0 + >; + }; }; /* PCIe controller base address 0x9000 */ &pci1 { - compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie"; law_trgt_if = <1>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <25 2 0 0>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <25 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0 + >; + }; }; /* PCIe controller base address 0xa000 */ &pci0 { - compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq", "fsl,mpc8548-pcie"; law_trgt_if = <2>; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x0 0xff>; + clock-frequency = <33333333>; + interrupts = <26 2 0 0>; + + pcie@0 { + reg = <0 0 0 0 0>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + interrupts = <26 2 0 0>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0 */ + 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 + 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0 + 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0 + 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0 + >; + }; }; &lbc { From 0e33f68b239988a10ecef5fea691d9bfd05b2ad2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:52 +0200 Subject: [PATCH 47/56] powerpc: dts: p2020: Add ptp_clock@24e00 node via pq3-etsec1-timer-0.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Import pq3-etsec1-timer-0.dtsi device tree include file from upstream Linux kernel for P2020. This allows U-Boot to use P2020 device tree files from upstream Linux kernel which reference ptp_clock@24e00 device. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 6 ++++ arch/powerpc/dts/pq3-etsec1-timer-0.dtsi | 39 ++++++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 arch/powerpc/dts/pq3-etsec1-timer-0.dtsi diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 6eb6fedd415..7709f3f9ade 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -53,6 +53,12 @@ /include/ "pq3-gpio-0.dtsi" /include/ "pq3-etsec1-0.dtsi" +/include/ "pq3-etsec1-timer-0.dtsi" + + ptp_clock@24e00 { + interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>; + }; + /include/ "pq3-etsec1-1.dtsi" /include/ "pq3-etsec1-2.dtsi" }; diff --git a/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi new file mode 100644 index 00000000000..efe2ca04bce --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-timer-0.dtsi @@ -0,0 +1,39 @@ +/* + * PQ3 eTSEC Timer (IEEE 1588) device tree stub [ @ offsets 0x24e00 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +ptp_clock@24e00 { + compatible = "fsl,etsec-ptp"; + reg = <0x24e00 0xb0>; + interrupts = <68 2 0 0 69 2 0 0>; +}; From d1721ea6d96c8d29b666278ca326fdc9a0b27023 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:53 +0200 Subject: [PATCH 48/56] powerpc: dts: p2020: Add Linux compatible string and property for eSDHC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux kernel eSDHC driver for P2020 requires additional compatible string fsl,p2020-esdhc and interrupts property. Add them to p2020-post.dtsi file to make U-Boot board DTS files compatible for Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 7709f3f9ade..d1559739404 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -32,8 +32,9 @@ }; esdhc: sdhc@2e000 { - compatible = "fsl,esdhc"; + compatible = "fsl,p2020-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; + interrupts = <72 0x2 0 0>; /* Filled in by U-Boot */ clock-frequency = <0>; }; From 15d086ded9f2f7fcbf8e163d95f2740b00414eff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:54 +0200 Subject: [PATCH 49/56] powerpc: dts: p2020: Do not automatically disable spi@7000 node in p2020-post.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Device tree include file p2020-post.dtsi should be included after the board device tree file and overrides settings of the board. So it should not disable some node as board cannot enable it via normal way (it has to enable it after inclusion of p2020-post.dtsi file). Fix it by removal of explicit disable in p2020-post.dtsi file and then remove explicit post-post enable in all P2020 board device tree files. Currently no P2020 board has spi@7000 node disabled. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 1 - arch/powerpc/dts/p2020rdb-pc.dts | 1 - arch/powerpc/dts/p2020rdb-pc_36b.dts | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index d1559739404..248b504b8fc 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -45,7 +45,6 @@ #size-cells = <0>; reg = <0x7000 0x1000>; fsl,espi-num-chipselects = <4>; - status = "disabled"; }; /include/ "pq3-i2c-0.dtsi" diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 67fa340d09d..84d32360baa 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -49,7 +49,6 @@ /include/ "p2020-post.dtsi" &espi0 { - status = "okay"; flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 6f251960031..c847417df99 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -49,7 +49,6 @@ /include/ "p2020-post.dtsi" &espi0 { - status = "okay"; flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; From 7b074129ad5701500d33d22a8492e1577b1209ac Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:55 +0200 Subject: [PATCH 50/56] powerpc: dts: p2020: Add missing interrupts property to spi@7000 node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit interrupts property for spi@7000 node is needed for compatibility with Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 248b504b8fc..2135710ccc3 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -44,6 +44,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x7000 0x1000>; + interrupts = < 0x3b 0x02 0x00 0x00 >; fsl,espi-num-chipselects = <4>; }; From 787d2c024bb43bb99cda20c38629a3aa6b3ac376 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:56 +0200 Subject: [PATCH 51/56] powerpc: dts: p2020: Make usb@22000 node compatible for Linux kernel driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux P2020 USB kernel driver uses compatible string fsl-usb2-dr-v1.6 and needs more DT properties. Copy P2020 usb@22000 properties from upstream Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 2135710ccc3..0a296cffe56 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -14,8 +14,11 @@ bus-frequency = <0x0>; usb@22000 { - compatible = "fsl-usb2-dr"; + compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr"; reg = <0x22000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <28 0x2 0 0>; phy_type = "ulpi"; }; From fd3dc72945474ca3665cd76c96350f7c0e7d95cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:57 +0200 Subject: [PATCH 52/56] powerpc: dts: p2020: Define L2 cache node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy definition of L2 cache node from upstream Linux kernel P2020 dts files. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/p2020-post.dtsi | 8 ++++++++ arch/powerpc/dts/p2020.dtsi | 2 ++ 2 files changed, 10 insertions(+) diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 0a296cffe56..1c3f78798ef 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -56,6 +56,14 @@ /include/ "pq3-duart-0.dtsi" /include/ "pq3-gpio-0.dtsi" + L2: l2-cache-controller@20000 { + compatible = "fsl,p2020-l2-cache-controller"; + reg = <0x20000 0x1000>; + cache-line-size = <32>; /* 32 bytes */ + cache-size = <0x80000>; /* L2,512K */ + interrupts = <16 2 0 0>; + }; + /include/ "pq3-etsec1-0.dtsi" /include/ "pq3-etsec1-timer-0.dtsi" diff --git a/arch/powerpc/dts/p2020.dtsi b/arch/powerpc/dts/p2020.dtsi index 7c4c2061d4c..7fdcb85c809 100644 --- a/arch/powerpc/dts/p2020.dtsi +++ b/arch/powerpc/dts/p2020.dtsi @@ -22,10 +22,12 @@ cpu0: PowerPC,P2020@0 { device_type = "cpu"; reg = <0>; + next-level-cache = <&L2>; }; cpu1: PowerPC,P2020@1 { device_type = "cpu"; reg = <1>; + next-level-cache = <&L2>; }; }; }; From e8c9148bc90e83b809cc8ecd8db73304b4755eae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 8 Apr 2022 14:39:58 +0200 Subject: [PATCH 53/56] powerpc: dts: p2020: Set dfsrr property for i2c nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Linux kernel dts files pq3-i2c-*.dtsi also sets this dfsrr property for i2c nodes. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/pq3-i2c-0.dtsi | 1 + arch/powerpc/dts/pq3-i2c-1.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/powerpc/dts/pq3-i2c-0.dtsi b/arch/powerpc/dts/pq3-i2c-0.dtsi index 86a91e63365..0ed519c2e53 100644 --- a/arch/powerpc/dts/pq3-i2c-0.dtsi +++ b/arch/powerpc/dts/pq3-i2c-0.dtsi @@ -12,4 +12,5 @@ i2c@3000 { u-boot,dm-pre-reloc; reg = <0x3000 0x100>; interrupts = <43 2 0 0>; + dfsrr; }; diff --git a/arch/powerpc/dts/pq3-i2c-1.dtsi b/arch/powerpc/dts/pq3-i2c-1.dtsi index 5d79b1fb4c3..78b0fcf81dc 100644 --- a/arch/powerpc/dts/pq3-i2c-1.dtsi +++ b/arch/powerpc/dts/pq3-i2c-1.dtsi @@ -12,4 +12,5 @@ i2c@3100 { u-boot,dm-pre-reloc; reg = <0x3100 0x100>; interrupts = <43 2 0 0>; + dfsrr; }; From 95f8dfe8fb94d8de8abe8f5f7088c7c5ec234dd0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 14 Apr 2022 22:52:03 +0200 Subject: [PATCH 54/56] pci: fsl: Change compatible string for mpc8548 to "fsl, mpc8548-pcie" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upstream Linux kernel uses for mpc8548-based PCIe controllers compatible string "fsl,mpc8548-pcie". So change U-Boot fsl PCIe driver and all DTS files to use "fsl,mpc8548-pcie" instead of "fsl,pcie-mpc8548" to be compatible with Linux kernel. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- arch/powerpc/dts/mpc8548-post.dtsi | 2 +- drivers/pci/pcie_fsl.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi index 2206f2da9fe..97c3ce6e74d 100644 --- a/arch/powerpc/dts/mpc8548-post.dtsi +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -27,7 +27,7 @@ }; &pcie { - compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + compatible = "fsl,mpc8548-pcie", "fsl,pcie-fsl-qoriq"; law_trgt_if = <2>; #address-cells = <3>; #size-cells = <2>; diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index f5ba34970f1..59c38f90577 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -646,7 +646,7 @@ static struct fsl_pcie_data t2080_data = { }; static const struct udevice_id fsl_pcie_ids[] = { - { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data }, + { .compatible = "fsl,mpc8548-pcie", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, From 7026c1ee702dec01afca15ce8022fab0e5af5104 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 19 Apr 2022 17:06:31 -0400 Subject: [PATCH 55/56] board: ls1046afrwy: Remove Manish Tomar's email Manish Tomar's email bounces. Remove it, and reassign the config he was maintaining to the primary maintainer for the board. Signed-off-by: Sean Anderson Reviewed-by: Priyanka Jain --- board/freescale/ls1046afrwy/MAINTAINERS | 4 ---- 1 file changed, 4 deletions(-) diff --git a/board/freescale/ls1046afrwy/MAINTAINERS b/board/freescale/ls1046afrwy/MAINTAINERS index cb8aa8c3780..8f360e1820f 100644 --- a/board/freescale/ls1046afrwy/MAINTAINERS +++ b/board/freescale/ls1046afrwy/MAINTAINERS @@ -5,8 +5,4 @@ F: board/freescale/ls1046afrwy/ F: board/freescale/ls1046afrwy/ls1046afrwy.c F: include/configs/ls1046afrwy.h F: configs/ls1046afrwy_tfa_defconfig - -LS1046AFRWY_SECURE_BOOT BOARD -M: Manish Tomar -S: Maintained F: configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig From 182d45ddff8944e291c805d94a01d7dd29d0d3b6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 22 Apr 2022 15:32:21 +0200 Subject: [PATCH 56/56] cpu: 83xx: Add missing dependency on CPU_MPC83XX It looks quite weird that for non PPC platforms cpu driver for MPC83xx can be selected. That's why define proper dependency. Signed-off-by: Michal Simek Reviewed-by: Tom Rini Reviewed-by: Priyanka Jain --- drivers/cpu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig index 3d5729f6dca..789728167ce 100644 --- a/drivers/cpu/Kconfig +++ b/drivers/cpu/Kconfig @@ -9,7 +9,7 @@ config CPU config CPU_MPC83XX bool "Enable MPC83xx CPU driver" - depends on CPU + depends on CPU && MPC83xx select CLK_MPC83XX help Support CPU cores for SoCs of the MPC83xx series.