board: bsh: imx6ulz_smm_m2: Add support for 256 MiB DRAM
Calibration values were calculated using the NXP tool I.MX6ULL_DDR3_Script_Aid_V0.01.xlsx Signed-off-by: Wolfgang Birkner <wolfgang.birkner@bshg.com> Signed-off-by: Simon Holesch <simon.holesch@bshg.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
This commit is contained in:
Simon Holesch
committed by
Fabio Estevam
Fabio Estevam
parent
da6547acb8
commit
8c2987396a
@@ -2,5 +2,5 @@
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# (C) Copyright 2021 Amarula Solutions B.V.
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# (C) Copyright 2021 Amarula Solutions B.V.
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obj-y := imx6ulz_smm_m2.o
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obj-y := imx6ulz_smm_m2.o
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obj-$(CONFIG_XPL_BUILD) += spl.o
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obj-$(CONFIG_XPL_BUILD) += spl.o ddr3l_timing_256m.o ddr3l_timing_128m.o
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169
board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c
Normal file
169
board/bsh/imx6ulz_smm_m2/ddr3l_timing_128m.c
Normal file
@@ -0,0 +1,169 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include "spl_mtypes.h"
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static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = {
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/* IOMUX */
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/* DDR IO Type: */
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{0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
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{0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
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/* Clock: */
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{0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
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/* Address: */
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{0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
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{0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
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{0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
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/* Control: */
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{0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
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{0x020e0270, 0x00000000}, /*
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* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured
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* using Group Control Register IOMUXC_SW_PAD_CTL_GRP_CTLDS
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*/
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{0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
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{0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
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{0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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/* Data Strobes: */
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{0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
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{0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
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{0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
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/* Data: */
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{0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
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{0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
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{0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
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{0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
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{0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
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/*
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* =============================================================================
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* DDR Controller Registers
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* =============================================================================
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* Manufacturer:ISSI
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* Device Part Number:IS43TR16640BL-125JBLI
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* Clock Freq.: 400MHz
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* Density per CS in Gb: 1
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* Chip Selects used:1
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* Number of Banks:8
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* Row address: 13
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* Column address: 10
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* Data bus width16
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* =============================================================================
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*/
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{0x021b001c, 0x00008000}, /*
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* MMDC0_MDSCR, set the Configuration request bit
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* during MMDC set up
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*/
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/*
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* =============================================================================
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* Calibration setup.
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* =============================================================================
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*/
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{0x021b0800, 0xA1390003}, /*
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* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic
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* HW ZQ calibration.
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*/
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/*
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* For target board, may need to run write leveling calibration to fine tune
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* these settings.
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*/
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{0x021b080c, 0x00000000},
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/* Read DQS Gating calibration */
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{0x021b083c, 0x41480148}, /* MPDGCTRL0 PHY0 */
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/* Read calibration */
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{0x021b0848, 0x40403A3E}, /* MPRDDLCTL PHY0 */
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/* Write calibration */
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{0x021b0850, 0x4040362E}, /* MPWRDLCTL PHY0 */
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/*
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* Read data bit delay: 3 is the recommended default value, although out of reset
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* value is 0.
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*/
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{0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */
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{0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */
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/* Write data bit delay: */
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{0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */
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{0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */
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/* DQS&CLK Duty Cycle */
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{0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
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/* Complete calibration by forced measurement: */
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{0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
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/*
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* =============================================================================
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* Calibration setup end
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* =============================================================================
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*/
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/* MMDC init: */
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{0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */
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{0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */
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{0x021b000c, 0x2B2F52F3}, /* MMDC0_MDCFG0 */
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{0x021b0010, 0xB66D0B63}, /* MMDC0_MDCFG1 */
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{0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
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/*
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* MDMISC: RALAT kept to the high level of 5.
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* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
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* Lower RALAT benefits:
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* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
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* b. Small performance improvement
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*/
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{0x021b0018, 0x00211740}, /* MMDC0_MDMISC */
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{0x021b001c, 0x00008000}, /*
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* MMDC0_MDSCR, set the Configuration request bit during
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* MMDC set up
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*/
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{0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */
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{0x021b0030, 0x002F1023}, /* MMDC0_MDOR */
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{0x021b0040, 0x00000043}, /* Chan0 CS0_END */
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{0x021b0000, 0x82180000}, /* MMDC0_MDCTL */
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{0x021b0890, 0x00400000}, /* MPPDCMPR2 */
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/* Mode register writes */
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{0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
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{0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
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{0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
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{0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */
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{0x021b001c, 0x04008040}, /*
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* MMDC0_MDSCR, ZQ calibration command sent to device
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* on CS0
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*/
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{0x021b0020, 0x00007800}, /* MMDC0_MDREF */
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{0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
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{0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */
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{0x021b0404, 0x00011006}, /*
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* MMDC0_MAPSR ADOPT power down enabled,
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* MMDC will enter automatically to self-refresh
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* while the number of idle cycle reached.
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*/
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{0x021b001c, 0x00000000}, /*
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* MMDC0_MDSCR, clear this register (especially the
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* configuration bit as initialization is complete)
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*/
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};
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struct dram_timing_info bsh_dram_timing_128mb = {
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.ddrc_cfg = ddr_ddrc_cfg_128mb,
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.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb),
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};
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168
board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c
Normal file
168
board/bsh/imx6ulz_smm_m2/ddr3l_timing_256m.c
Normal file
@@ -0,0 +1,168 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include "spl_mtypes.h"
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static const struct dram_cfg_param ddr_ddrc_cfg_256mb[] = {
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/* IOMUX */
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/* DDR IO Type: */
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{0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
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{0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
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/* Clock: */
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{0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
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/* Address: */
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{0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
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{0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
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{0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
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/* Control: */
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{0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
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{0x020e0270, 0x00000000}, /*
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* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured
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* using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
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*/
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{0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
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{0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
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{0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
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/* Data Strobes: */
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{0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
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{0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
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{0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
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/* Data: */
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{0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
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{0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
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{0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
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{0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
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{0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
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/*
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* =============================================================================
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* DDR Controller Registers
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* =============================================================================
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* Manufacturer:ISSI
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* Device Part Number:IS43TR16640BL-125JBLI
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* Clock Freq.: 400MHz
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* Density per CS in Gb: 2
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* Chip Selects used:1
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* Number of Banks:8
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* Row address: 14
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* Column address: 10
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* Data bus width16
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* =============================================================================
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*/
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{0x021b001c, 0x00008000}, /*
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* MMDC0_MDSCR, set the Configuration request bit during
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* MMDC set up
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*/
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/*
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* =============================================================================
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* Calibration setup.
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* =============================================================================
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*/
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{0x021b0800, 0xA1390003}, /*
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* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic
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* HW ZQ calibration
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*/
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/*
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* For target board, may need to run write leveling calibration to fine tune these settings
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*/
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{0x021b080c, 0x00050005},
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/* Read DQS Gating calibration */
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{0x021b083c, 0x01480144}, /* MPDGCTRL0 PHY0 */
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/* Read calibration */
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{0x021b0848, 0x4040363A}, /* MPRDDLCTL PHY0 */
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/* Write calibration */
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{0x021b0850, 0x40402E2C}, /* MPWRDLCTL PHY0 */
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/*
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* Read data bit delay: 3 is the reccommended default value, although out of reset value
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* is 0
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*/
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{0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */
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{0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */
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/* Write data bit delay: */
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{0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */
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{0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */
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/* DQS&CLK Duty Cycle */
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{0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
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/* Complete calibration by forced measurement: */
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{0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
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/*
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* =============================================================================
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* Calibration setup end
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* =============================================================================
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*/
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/* MMDC init: */
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{0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */
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{0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */
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{0x021b000c, 0x3F435333}, /* MMDC0_MDCFG0 */
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{0x021b0010, 0xB68E0B63}, /* MMDC0_MDCFG1 */
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{0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
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/*
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* MDMISC: RALAT kept to the high level of 5.
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* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
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* Lower RALAT benefits:
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* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
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* b. Small performence improvment
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*/
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{0x021b0018, 0x00211740}, /* MMDC0_MDMISC */
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{0x021b001c, 0x00008000}, /*
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* MMDC0_MDSCR, set the Configuration request bit during
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* MMDC set up
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*/
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{0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */
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{0x021b0030, 0x00431023}, /* MMDC0_MDOR */
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{0x021b0040, 0x00000047}, /* Chan0 CS0_END */
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{0x021b0000, 0x83180000}, /* MMDC0_MDCTL */
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{0x021b0890, 0x00400000}, /* MPPDCMPR2 */
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/* Mode register writes */
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||||||
|
{0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
|
||||||
|
{0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
|
||||||
|
{0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
|
||||||
|
{0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */
|
||||||
|
{0x021b001c, 0x04008040}, /*
|
||||||
|
* MMDC0_MDSCR, ZQ calibration command sent to device
|
||||||
|
* on CS0
|
||||||
|
*/
|
||||||
|
|
||||||
|
{0x021b0020, 0x00007800}, /* MMDC0_MDREF */
|
||||||
|
|
||||||
|
{0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
|
||||||
|
|
||||||
|
{0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */
|
||||||
|
|
||||||
|
{0x021b0404, 0x00011006}, /*
|
||||||
|
* MMDC0_MAPSR ADOPT power down enabled, MMDC will enter
|
||||||
|
* automatically to self-refresh while the number of idle
|
||||||
|
* cycle reached
|
||||||
|
*/
|
||||||
|
|
||||||
|
{0x021b001c, 0x00000000}, /*
|
||||||
|
* MMDC0_MDSCR, clear this register (especially the
|
||||||
|
* configuration bit as initialization is complete)
|
||||||
|
*/
|
||||||
|
};
|
||||||
|
|
||||||
|
struct dram_timing_info bsh_dram_timing_256mb = {
|
||||||
|
.ddrc_cfg = ddr_ddrc_cfg_256mb,
|
||||||
|
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_256mb),
|
||||||
|
};
|
||||||
@@ -17,6 +17,8 @@
|
|||||||
#include <spl.h>
|
#include <spl.h>
|
||||||
#include <asm/arch/mx6-ddr.h>
|
#include <asm/arch/mx6-ddr.h>
|
||||||
|
|
||||||
|
#include "spl_mtypes.h"
|
||||||
|
|
||||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||||
@@ -31,190 +33,15 @@ static void setup_iomux_uart(void)
|
|||||||
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
|
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
|
||||||
}
|
}
|
||||||
|
|
||||||
struct dram_cfg_param {
|
|
||||||
unsigned int reg;
|
|
||||||
unsigned int val;
|
|
||||||
};
|
|
||||||
|
|
||||||
struct dram_timing_info {
|
|
||||||
const struct dram_cfg_param *ddrc_cfg;
|
|
||||||
unsigned int ddrc_cfg_num;
|
|
||||||
};
|
|
||||||
|
|
||||||
static const struct dram_cfg_param ddr_ddrc_cfg_128mb[] = {
|
|
||||||
/* IOMUX */
|
|
||||||
|
|
||||||
/* DDR IO Type: */
|
|
||||||
{0x020e04b4, 0x000C0000}, /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
|
|
||||||
{0x020e04ac, 0x00000000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
|
|
||||||
|
|
||||||
/* Clock: */
|
|
||||||
{0x020e027c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
|
|
||||||
|
|
||||||
/* Address: */
|
|
||||||
{0x020e0250, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
|
|
||||||
{0x020e024c, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
|
|
||||||
{0x020e0490, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
|
|
||||||
|
|
||||||
/* Control: */
|
|
||||||
{0x020e0288, 0x000C0028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
|
|
||||||
|
|
||||||
{0x020e0270, 0x00000000}, /*
|
|
||||||
* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured
|
|
||||||
* using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS
|
|
||||||
*/
|
|
||||||
|
|
||||||
{0x020e0260, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
|
|
||||||
{0x020e0264, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
|
|
||||||
{0x020e04a0, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
|
|
||||||
|
|
||||||
/* Data Strobes: */
|
|
||||||
{0x020e0494, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
|
|
||||||
{0x020e0280, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
|
|
||||||
{0x020e0284, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
|
|
||||||
|
|
||||||
/* Data: */
|
|
||||||
{0x020e04b0, 0x00020000}, /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
|
|
||||||
{0x020e0498, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
|
|
||||||
{0x020e04a4, 0x00000028}, /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
|
|
||||||
|
|
||||||
{0x020e0244, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
|
|
||||||
{0x020e0248, 0x00000028}, /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* =============================================================================
|
|
||||||
* DDR Controller Registers
|
|
||||||
* =============================================================================
|
|
||||||
* Manufacturer:ISSI
|
|
||||||
* Device Part Number:IS43TR16640BL-125JBLI
|
|
||||||
* Clock Freq.: 400MHz
|
|
||||||
* Density per CS in Gb: 1
|
|
||||||
* Chip Selects used:1
|
|
||||||
* Number of Banks:8
|
|
||||||
* Row address: 13
|
|
||||||
* Column address: 10
|
|
||||||
* Data bus width16
|
|
||||||
* =============================================================================
|
|
||||||
*/
|
|
||||||
|
|
||||||
{0x021b001c, 0x00008000}, /*
|
|
||||||
* MMDC0_MDSCR, set the Configuration request bit during
|
|
||||||
* MMDC set up
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* =============================================================================
|
|
||||||
* Calibration setup
|
|
||||||
* =============================================================================
|
|
||||||
*/
|
|
||||||
|
|
||||||
{0x021b0800, 0xA1390003}, /*
|
|
||||||
* DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic
|
|
||||||
* HW ZQ calibration.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For target board, may need to run write leveling calibration to fine tune these
|
|
||||||
* settings.
|
|
||||||
*/
|
|
||||||
{0x021b080c, 0x00000000},
|
|
||||||
|
|
||||||
/* Read DQS Gating calibration */
|
|
||||||
{0x021b083c, 0x41480148}, /* MPDGCTRL0 PHY0 */
|
|
||||||
|
|
||||||
/* Read calibration */
|
|
||||||
{0x021b0848, 0x40403A3E}, /* MPRDDLCTL PHY0 */
|
|
||||||
|
|
||||||
/* Write calibration */
|
|
||||||
{0x021b0850, 0x4040362E}, /* MPWRDLCTL PHY0 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Read data bit delay: 3 is the recommended default value, although out of reset
|
|
||||||
* value is 0
|
|
||||||
*/
|
|
||||||
{0x021b081c, 0x33333333}, /* MMDC_MPRDDQBY0DL */
|
|
||||||
{0x021b0820, 0x33333333}, /* MMDC_MPRDDQBY1DL */
|
|
||||||
|
|
||||||
/* Write data bit delay: */
|
|
||||||
{0x021b082c, 0xF3333333}, /* MMDC_MPWRDQBY0DL */
|
|
||||||
{0x021b0830, 0xF3333333}, /* MMDC_MPWRDQBY1DL */
|
|
||||||
|
|
||||||
/* DQS&CLK Duty Cycle */
|
|
||||||
{0x021b08c0, 0x00944009}, /* [MMDC_MPDCCR] MMDC Duty Cycle Control Register */
|
|
||||||
|
|
||||||
/* Complete calibration by forced measurement: */
|
|
||||||
{0x021b08b8, 0x00000800}, /* DDR_PHY_P0_MPMUR0, frc_msr */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* =============================================================================
|
|
||||||
* Calibration setup end
|
|
||||||
* =============================================================================
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* MMDC init: */
|
|
||||||
{0x021b0004, 0x0002002D}, /* MMDC0_MDPDC */
|
|
||||||
{0x021b0008, 0x1B333030}, /* MMDC0_MDOTC */
|
|
||||||
{0x021b000c, 0x2B2F52F3}, /* MMDC0_MDCFG0 */
|
|
||||||
{0x021b0010, 0xB66D0B63}, /* MMDC0_MDCFG1 */
|
|
||||||
{0x021b0014, 0x01FF00DB}, /* MMDC0_MDCFG2 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MDMISC: RALAT kept to the high level of 5.
|
|
||||||
* MDMISC: consider reducing RALAT if your 528MHz board design allow that.
|
|
||||||
* Lower RALAT benefits:
|
|
||||||
* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3
|
|
||||||
* b. Small performance improvement
|
|
||||||
*/
|
|
||||||
{0x021b0018, 0x00211740}, /* MMDC0_MDMISC */
|
|
||||||
{0x021b001c, 0x00008000}, /*
|
|
||||||
* MMDC0_MDSCR, set the Configuration request
|
|
||||||
* bit during MMDC set up
|
|
||||||
*/
|
|
||||||
{0x021b002c, 0x000026D2}, /* MMDC0_MDRWD */
|
|
||||||
{0x021b0030, 0x002F1023}, /* MMDC0_MDOR */
|
|
||||||
{0x021b0040, 0x00000043}, /* Chan0 CS0_END */
|
|
||||||
{0x021b0000, 0x82180000}, /* MMDC0_MDCTL */
|
|
||||||
|
|
||||||
{0x021b0890, 0x00400000}, /* MPPDCMPR2 */
|
|
||||||
|
|
||||||
/* Mode register writes */
|
|
||||||
{0x021b001c, 0x02808032}, /* MMDC0_MDSCR, MR2 write, CS0 */
|
|
||||||
{0x021b001c, 0x00008033}, /* MMDC0_MDSCR, MR3 write, CS0 */
|
|
||||||
{0x021b001c, 0x00048031}, /* MMDC0_MDSCR, MR1 write, CS0 */
|
|
||||||
{0x021b001c, 0x15208030}, /* MMDC0_MDSCR, MR0write, CS0 */
|
|
||||||
{0x021b001c, 0x04008040}, /*
|
|
||||||
* MMDC0_MDSCR, ZQ calibration command sent to
|
|
||||||
* device on CS0
|
|
||||||
*/
|
|
||||||
{0x021b0020, 0x00007800}, /* MMDC0_MDREF */
|
|
||||||
|
|
||||||
{0x021b0818, 0x00000227}, /* DDR_PHY_P0_MPODTCTRL */
|
|
||||||
|
|
||||||
{0x021b0004, 0x0002552D}, /* MMDC0_MDPDC now SDCTL power down enabled */
|
|
||||||
|
|
||||||
{0x021b0404, 0x00011006}, /*
|
|
||||||
* MMDC0_MAPSR ADOPT power down enabled,
|
|
||||||
* MMDC will enter automatically to self-refresh
|
|
||||||
* while the number of idle cycle reached.
|
|
||||||
*/
|
|
||||||
|
|
||||||
{0x021b001c, 0x00000000}, /*
|
|
||||||
* MMDC0_MDSCR, clear this register
|
|
||||||
* (especially the configuration bit as initialization
|
|
||||||
* is complete)
|
|
||||||
*/
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct dram_timing_info dram_timing_128mb = {
|
|
||||||
.ddrc_cfg = ddr_ddrc_cfg_128mb,
|
|
||||||
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg_128mb),
|
|
||||||
};
|
|
||||||
|
|
||||||
static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info)
|
static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
const struct dram_cfg_param *ddrc_cfg = dram_timing_info->ddrc_cfg;
|
const struct dram_cfg_param *ddrc_cfg = dram_timing_info->ddrc_cfg;
|
||||||
const int ddrc_cfg_num = dram_timing_info->ddrc_cfg_num;
|
const int ddrc_cfg_num = dram_timing_info->ddrc_cfg_num;
|
||||||
|
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
|
||||||
|
|
||||||
|
clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
|
||||||
|
clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
|
||||||
|
|
||||||
for (i = 0; i < ddrc_cfg_num; i++) {
|
for (i = 0; i < ddrc_cfg_num; i++) {
|
||||||
debug("Writing 0x%x to register 0x%x\n", ddrc_cfg->val,
|
debug("Writing 0x%x to register 0x%x\n", ddrc_cfg->val,
|
||||||
@@ -226,12 +53,22 @@ static void ddr_cfg_write(const struct dram_timing_info *dram_timing_info)
|
|||||||
|
|
||||||
static void spl_dram_init(void)
|
static void spl_dram_init(void)
|
||||||
{
|
{
|
||||||
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
|
/* Configure memory to maximum supported size for detection */
|
||||||
|
ddr_cfg_write(&bsh_dram_timing_256mb);
|
||||||
|
|
||||||
clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */
|
/* Detect memory physically present */
|
||||||
clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */
|
gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_256M);
|
||||||
|
|
||||||
ddr_cfg_write(&dram_timing_128mb);
|
/* Reconfigure memory for actual detected size */
|
||||||
|
switch (gd->ram_size) {
|
||||||
|
case SZ_256M:
|
||||||
|
/* Already configured, nothing to do */
|
||||||
|
break;
|
||||||
|
case SZ_128M:
|
||||||
|
default:
|
||||||
|
ddr_cfg_write(&bsh_dram_timing_128mb);
|
||||||
|
break;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void ccgr_init(void)
|
static void ccgr_init(void)
|
||||||
|
|||||||
26
board/bsh/imx6ulz_smm_m2/spl_mtypes.h
Normal file
26
board/bsh/imx6ulz_smm_m2/spl_mtypes.h
Normal file
@@ -0,0 +1,26 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||||
|
/*
|
||||||
|
* Copyright 2025 BSH Hausgeraete GmbH
|
||||||
|
*
|
||||||
|
* Written by: Simon Holesch <simon.holesch@bshg.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef SPL_MTYPES_H
|
||||||
|
#define SPL_MTYPES_H
|
||||||
|
|
||||||
|
#include <spl.h>
|
||||||
|
|
||||||
|
struct dram_cfg_param {
|
||||||
|
unsigned int reg;
|
||||||
|
unsigned int val;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct dram_timing_info {
|
||||||
|
const struct dram_cfg_param *ddrc_cfg;
|
||||||
|
unsigned int ddrc_cfg_num;
|
||||||
|
};
|
||||||
|
|
||||||
|
extern struct dram_timing_info bsh_dram_timing_128mb;
|
||||||
|
extern struct dram_timing_info bsh_dram_timing_256mb;
|
||||||
|
|
||||||
|
#endif /* SPL_MTYPES_H */
|
||||||
@@ -61,8 +61,6 @@
|
|||||||
|
|
||||||
/* Physical Memory Map */
|
/* Physical Memory Map */
|
||||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||||
#define PHYS_SDRAM_SIZE SZ_128M
|
|
||||||
|
|
||||||
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
|
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||||
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||||
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||||
|
|||||||
Reference in New Issue
Block a user