From 14a4792a71db3561bea065415ac1f2ac69ef32b5 Mon Sep 17 00:00:00 2001 From: Mayuresh Chitale Date: Fri, 4 Apr 2025 14:48:55 +0000 Subject: [PATCH 01/23] riscv: image: Add new image type for RV64 Similar to ARM and X86, introduce a new image type which allows u-boot to distinguish between images built for 32-bit vs 64-bit Risc-V CPUs. Signed-off-by: Mayuresh Chitale Reviewed-by: Maxim Moskalets --- boot/image.c | 3 ++- include/image.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/boot/image.c b/boot/image.c index 139c5bd035a..45299a7dc33 100644 --- a/boot/image.c +++ b/boot/image.c @@ -92,7 +92,8 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_ARC, "arc", "ARC", }, { IH_ARCH_X86_64, "x86_64", "AMD x86_64", }, { IH_ARCH_XTENSA, "xtensa", "Xtensa", }, - { IH_ARCH_RISCV, "riscv", "RISC-V", }, + { IH_ARCH_RISCV, "riscv", "RISC-V 32 Bit",}, + { IH_ARCH_RISCV64, "riscv64", "RISC-V 64 Bit",}, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index c1db8383459..4620782c069 100644 --- a/include/image.h +++ b/include/image.h @@ -138,7 +138,8 @@ enum { IH_ARCH_ARC, /* Synopsys DesignWare ARC */ IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ IH_ARCH_XTENSA, /* Xtensa */ - IH_ARCH_RISCV, /* RISC-V */ + IH_ARCH_RISCV, /* RISC-V 32 bit*/ + IH_ARCH_RISCV64, /* RISC-V 64 bit*/ IH_ARCH_COUNT, }; From 027a316828528da95a77d20632370b1bc2823f0b Mon Sep 17 00:00:00 2001 From: Mayuresh Chitale Date: Fri, 4 Apr 2025 14:48:56 +0000 Subject: [PATCH 02/23] riscv: Select appropriate image type Select between the 32-bit or 64-bit arch type for the image headers depending on how the build is configured. Signed-off-by: Mayuresh Chitale Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/binman.dtsi | 14 ++++++++++---- arch/riscv/include/asm/u-boot.h | 4 ++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index 5aeeeddb59f..f8c10837aa3 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -5,6 +5,12 @@ #include +#ifdef CONFIG_64BIT +#define ARCH "riscv64" +#else +#define ARCH "riscv" + +#endif / { binman: binman { multiple-images; @@ -31,7 +37,7 @@ description = "U-Boot"; type = "standalone"; os = "U-Boot"; - arch = "riscv"; + arch = ARCH; compression = "none"; load = /bits/ 64 ; @@ -44,7 +50,7 @@ description = "Linux"; type = "standalone"; os = "Linux"; - arch = "riscv"; + arch = ARCH; compression = "none"; load = /bits/ 64 ; @@ -57,7 +63,7 @@ tee { description = "OP-TEE"; type = "tee"; - arch = "riscv"; + arch = ARCH; compression = "none"; os = "tee"; load = /bits/ 64 ; @@ -71,7 +77,7 @@ description = "OpenSBI fw_dynamic Firmware"; type = "firmware"; os = "opensbi"; - arch = "riscv"; + arch = ARCH; compression = "none"; load = /bits/ 64 ; entry = /bits/ 64 ; diff --git a/arch/riscv/include/asm/u-boot.h b/arch/riscv/include/asm/u-boot.h index d5e1d5f3231..a90cc4c21cf 100644 --- a/arch/riscv/include/asm/u-boot.h +++ b/arch/riscv/include/asm/u-boot.h @@ -23,6 +23,10 @@ #include /* For image.h:image_check_target_arch() */ +#ifdef CONFIG_64BIT +#define IH_ARCH_DEFAULT IH_ARCH_RISCV64 +#else #define IH_ARCH_DEFAULT IH_ARCH_RISCV +#endif #endif /* _U_BOOT_H_ */ From 37b0b22d8b7bbed6aa95b6daed06dcbf4a66f211 Mon Sep 17 00:00:00 2001 From: Mayuresh Chitale Date: Fri, 4 Apr 2025 14:48:57 +0000 Subject: [PATCH 03/23] booti/bootm: riscv: Verify image arch type Unlike ARM and X86, booting 32-bit images on 64-bit CPUs is currently not supported for Risc-V. Hence, for bootm, disallow booting a FIT or a legacy image that was built for an arch type which is different than the current arch and for booti, set the arch type to be the same as the current arch. Signed-off-by: Mayuresh Chitale Reviewed-by: Heinrich Schuchardt --- arch/riscv/lib/bootm.c | 4 ++++ cmd/booti.c | 7 +++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index 9544907ab1e..c98c5e76633 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -90,6 +90,10 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) announce_and_cleanup(fake); if (!fake) { + if (images->os.arch != IH_ARCH_DEFAULT) { + printf("Image arch not compatible with host arch.\n"); + hang(); + } if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) { #ifdef CONFIG_SMP ret = smp_call_function(images->ep, diff --git a/cmd/booti.c b/cmd/booti.c index 1a57fe91397..ced2c1047ab 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -130,8 +130,11 @@ int do_booti(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) bootm_disable_interrupts(); images.os.os = IH_OS_LINUX; - if (IS_ENABLED(CONFIG_RISCV_SMODE)) - images.os.arch = IH_ARCH_RISCV; + if (IS_ENABLED(CONFIG_RISCV)) + if (IS_ENABLED(CONFIG_64BIT)) + images.os.arch = IH_ARCH_RISCV64; + else + images.os.arch = IH_ARCH_RISCV; else if (IS_ENABLED(CONFIG_ARM64)) images.os.arch = IH_ARCH_ARM64; From 60163080949a57ba28bc10cb599dc2a9b53c75c4 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Sat, 26 Apr 2025 17:26:02 +0000 Subject: [PATCH 04/23] riscv: dts: binman.dtsi: Drop filename property for proper U-Boot Drop filename property for proper U-Boot entry since binman takes "u-boot-nodtb.bin" as the default filename for u-boot-nodtb entries. This follows efe9c12322b ("riscv: dts: binman.dtsi: Switch to u-boot-nodtb entry for proper U-Boot") to clean binman.dtsi up. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/binman.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index f8c10837aa3..c5b0464d6a7 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -42,7 +42,6 @@ load = /bits/ 64 ; uboot_blob: u-boot-nodtb { - filename = "u-boot-nodtb.bin"; }; }; #else From 307666be28db0d89cbdcfafd2cf0e0cf5bf386db Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Sun, 27 Apr 2025 14:50:11 +0000 Subject: [PATCH 05/23] riscv: Access gd with inline assembly when building with LTO or Clang Similar to AArch64's case, Clang may wrongly fold accesses to gd pointer which is defined with register qualifier into constants, breaking various components. This patch defines gd as a macro when building with Clang or LTO, which expands to get_gd() that accesses gp pointer in assembly, making RISC-V ports function properly and preparing for introduction of LTO in the future. Board initialization code is also adapted for non-assignable gd. Reported-by: Nathaniel Hourt Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/cpu.c | 6 ++++++ arch/riscv/include/asm/global_data.h | 19 +++++++++++++++++++ common/board_r.c | 4 +++- common/init/board_init.c | 7 +++++-- 4 files changed, 33 insertions(+), 3 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 5b31da64cbd..15c4e14599d 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -746,3 +747,8 @@ __weak int cleanup_before_linux(void) return 0; } + +void arch_setup_gd(gd_t *new_gd) +{ + set_gd(new_gd); +} diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index d356752a56a..47b5e2cfc8f 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -14,6 +14,7 @@ #include #include #include +#include /* Architecture-specific global data */ struct arch_global_data { @@ -47,8 +48,26 @@ struct arch_global_data { #include +#if defined(__clang__) || CONFIG_IS_ENABLED(LTO) + +#define DECLARE_GLOBAL_DATA_PTR +#define gd get_gd() + +static inline gd_t *get_gd(void) +{ + gd_t *gd_ptr; + + __asm__ volatile ("mv %0, gp\n" : "=r" (gd_ptr)); + + return gd_ptr; +} + +#else + #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp") +#endif + static inline void set_gd(volatile gd_t *gd_ptr) { #ifdef CONFIG_64BIT diff --git a/common/board_r.c b/common/board_r.c index b90a4d9ff69..41c8dec8d49 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -815,7 +815,9 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) if (CONFIG_IS_ENABLED(X86_64) && !IS_ENABLED(CONFIG_EFI_APP)) arch_setup_gd(new_gd); -#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#if defined(CONFIG_RISCV) + set_gd(new_gd); +#elif !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) gd = new_gd; #endif gd->flags &= ~GD_FLG_LOG_READY; diff --git a/common/init/board_init.c b/common/init/board_init.c index a06ec1caa2c..2a6f39f51ad 100644 --- a/common/init/board_init.c +++ b/common/init/board_init.c @@ -13,8 +13,11 @@ DECLARE_GLOBAL_DATA_PTR; -/* Unfortunately x86 or ARM can't compile this code as gd cannot be assigned */ -#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) +/* + * Unfortunately x86, ARM and RISC-V can't compile this code as gd is defined + * as macro and cannot be assigned. + */ +#if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_RISCV) __weak void arch_setup_gd(struct global_data *gd_ptr) { gd = gd_ptr; From fa317411ba564055d892e2b909112ca825449a42 Mon Sep 17 00:00:00 2001 From: Mayuresh Chitale Date: Mon, 28 Apr 2025 04:48:45 +0000 Subject: [PATCH 06/23] riscv: insn-def.h: Fix header guard Fix the erroneous header guard for insn-def.h to reflect the correct header name. Fixes: bfc8ca3f7f6 ("riscv: Add support for defining instructions") Signed-off-by: Mayuresh Chitale Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/insn-def.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index 19a10cad84c..1869342b167 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -5,8 +5,8 @@ * Ported from linux insn-def.h. */ -#ifndef _ASM_RISCV_BARRIER_H -#define _ASM_RISCV_BARRIER_H +#ifndef _ASM_RISCV_INSN_DEF_H +#define _ASM_RISCV_INSN_DEF_H #define INSN_I_SIMM12_SHIFT 20 #define INSN_I_RS1_SHIFT 15 @@ -36,4 +36,4 @@ __INSN_I(RV_##opcode, RV_##func3, RV_##rd, \ RV_##rs1, RV_##simm12) -#endif /* _ASM_RISCV_BARRIER_H */ +#endif /* _ASM_RISCV_INSN_DEF_H */ From 97833f4cf6f681a341e76771bbf42bc8f8611d82 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sat, 3 May 2025 04:52:52 -0700 Subject: [PATCH 07/23] riscv: starfive: jh7110: move uart0 clock frequency to config header Move unnecessary clock frequency assignment out of device-tree and into the board config header so that the ns16550 serial driver can successfully init during SPL after failing to resolve the parent clock from upstream dts. The serial driver will then resolve clock frequency from device-tree node parent clock at init during Main app as it is expected by upstream. Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-common-u-boot.dtsi | 1 - include/configs/starfive-visionfive2.h | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi index 6d85b2d91a7..049b0a7ce28 100644 --- a/arch/riscv/dts/jh7110-common-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -27,7 +27,6 @@ bootph-pre-ram; reg-offset = <0>; current-speed = <115200>; - clock-frequency = <24000000>; }; &mmc0 { diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 049b0a06301..e7001b26abf 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -39,4 +39,6 @@ "partitions=" PARTS_DEFAULT "\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" +#define CFG_SYS_NS16550_CLK 24000000 + #endif /* _STARFIVE_VISIONFIVE2_H */ From 8b43f4a7beddcadce9d07decc59f69e3e7ce0555 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sat, 3 May 2025 14:25:54 -0700 Subject: [PATCH 08/23] riscv: dts: jh7110: remove redundant parent nodes - use upstream alias name for cpu and timer nodes - remove bootph-pre-ram hint from parent nodes - drop S7 cpu core "okay" status Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-u-boot.dtsi | 72 ++++++++++++------------------- 1 file changed, 28 insertions(+), 44 deletions(-) diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index a9e318c4a31..b4b656b444b 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -6,46 +6,6 @@ #include / { - cpus: cpus { - bootph-pre-ram; - - S7_0: cpu@0 { - bootph-pre-ram; - status = "okay"; - cpu0_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - - U74_1: cpu@1 { - bootph-pre-ram; - cpu1_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - - U74_2: cpu@2 { - bootph-pre-ram; - cpu2_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - - U74_3: cpu@3 { - bootph-pre-ram; - cpu3_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - - U74_4: cpu@4 { - bootph-pre-ram; - cpu4_intc: interrupt-controller { - bootph-pre-ram; - }; - }; - }; - timer { compatible = "riscv,timer"; interrupts-extended = <&cpu0_intc 5>, @@ -58,10 +18,6 @@ soc { bootph-pre-ram; - clint: timer@2000000 { - bootph-pre-ram; - }; - dmc: dmc@15700000 { bootph-pre-ram; compatible = "starfive,jh7110-dmc"; @@ -78,6 +34,34 @@ }; }; +&clint { + bootph-pre-ram; +}; + +&cpu0_intc { + bootph-pre-ram; +}; + +&cpu1_intc { + bootph-pre-ram; +}; + +&cpu2_intc { + bootph-pre-ram; +}; + +&cpu3_intc { + bootph-pre-ram; +}; + +&cpu4_intc { + bootph-pre-ram; +}; + +&cpus { + bootph-pre-ram; +}; + &osc { bootph-pre-ram; }; From bbf5f79bba07703c85ab9e3f4101758afb402c09 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sat, 10 May 2025 11:42:27 -0700 Subject: [PATCH 09/23] riscv: dts: jh7110: override syscrg assigned clock rates with defaults JH7110 drivers are missing support for CPU frequency scaling, so override upstream device-tree to use default clock rates for syscrg. This override duplicates a portion of jh7110-common-u-boot.dtsi file planned for removal. Signed-off-by: E Shattow Reviewed-by: Leo Liang --- arch/riscv/dts/jh7110-u-boot.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index b4b656b444b..f8d13277d24 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -91,6 +91,7 @@ }; &syscrg { + assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */ bootph-pre-ram; }; From 3dbff9eecc869bc28ce010cf97d2cfee25c44f3a Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:04:54 +0000 Subject: [PATCH 10/23] riscv: lib: Split out support for T-Head cache management operations Designed before a standard set of cache management operations defined in RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the customized extension XTheadCMO, which has been used in the CV1800B port of U-Boot. This patch splits XTheadCMO-related code into a generic module, allowing SoCs shipping T-Head cores to share the code. Link: https://github.com/XUANTIE-RV/thead-extension-spec Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 8 ++++++++ arch/riscv/cpu/cv1800b/Kconfig | 1 + arch/riscv/cpu/cv1800b/Makefile | 1 - arch/riscv/lib/Makefile | 1 + arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} | 0 5 files changed, 10 insertions(+), 1 deletion(-) rename arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} (100%) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b24623590f2..dc36d9b8566 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -77,6 +77,14 @@ config SYS_DCACHE_OFF help Do not enable data cache in U-Boot. +config SYS_CACHE_THEAD_CMO + bool "THEAD non-standard cache operations" + depends on !SYS_DCACHE_OFF + default n + help + Support for non-standard cache management operations on SoCs based on + T-Head C906/C910 cores. + config SPL_SYS_DCACHE_OFF bool "Do not enable dcache in SPL" depends on SPL diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig index 7225b1210c5..57f724ae043 100644 --- a/arch/riscv/cpu/cv1800b/Kconfig +++ b/arch/riscv/cpu/cv1800b/Kconfig @@ -6,6 +6,7 @@ config SOPHGO_CV1800B bool select ARCH_EARLY_INIT_R select SYS_CACHE_SHIFT_6 + select SYS_CACHE_THEAD_CMO imply CPU imply CPU_RISCV imply RISCV_TIMER diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile index 95beb34b51a..da12e0f64e1 100644 --- a/arch/riscv/cpu/cv1800b/Makefile +++ b/arch/riscv/cpu/cv1800b/Makefile @@ -4,4 +4,3 @@ obj-y += dram.o obj-y += cpu.o -obj-y += cache.o diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 189b35c24d3..db8d235c699 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o +obj-$(CONFIG_SYS_CACHE_THEAD_CMO) += thead_cmo.o ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y) obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/lib/thead_cmo.c similarity index 100% rename from arch/riscv/cpu/cv1800b/cache.c rename to arch/riscv/lib/thead_cmo.c From acf9384d8cc372fc71a5857363cfe10c240c497a Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:04:55 +0000 Subject: [PATCH 11/23] configs: th1520_lpi4a: Add UART clock frequency The BROM of TH1520 always initializes UART0's parent clock and configures the baudrate to 115200. Describe the clock frequency to make UART function correctly in SPL without introducing CCF. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- include/configs/th1520_lpi4a.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h index 87496a52c4c..7a9b70a3678 100644 --- a/include/configs/th1520_lpi4a.h +++ b/include/configs/th1520_lpi4a.h @@ -9,6 +9,7 @@ #include +#define CFG_SYS_NS16550_CLK 100000000 #define CFG_SYS_SDRAM_BASE 0x00000000 #define UART_BASE 0xffe7014000 From 5fe9ced3552ddeb40478b56507d3b48968be2939 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:04:56 +0000 Subject: [PATCH 12/23] riscv: cpu: Add TH1520 CPU support Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 1 + arch/riscv/cpu/th1520/Kconfig | 21 ++++++++++++++++ arch/riscv/cpu/th1520/Makefile | 8 ++++++ arch/riscv/cpu/th1520/cache.c | 32 ++++++++++++++++++++++++ arch/riscv/cpu/th1520/cpu.c | 21 ++++++++++++++++ arch/riscv/cpu/th1520/dram.c | 21 ++++++++++++++++ arch/riscv/cpu/th1520/spl.c | 31 +++++++++++++++++++++++ arch/riscv/include/asm/arch-th1520/cpu.h | 9 +++++++ arch/riscv/include/asm/arch-th1520/spl.h | 10 ++++++++ 9 files changed, 154 insertions(+) create mode 100644 arch/riscv/cpu/th1520/Kconfig create mode 100644 arch/riscv/cpu/th1520/Makefile create mode 100644 arch/riscv/cpu/th1520/cache.c create mode 100644 arch/riscv/cpu/th1520/cpu.c create mode 100644 arch/riscv/cpu/th1520/dram.c create mode 100644 arch/riscv/cpu/th1520/spl.c create mode 100644 arch/riscv/include/asm/arch-th1520/cpu.h create mode 100644 arch/riscv/include/asm/arch-th1520/spl.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index dc36d9b8566..8c6feae5735 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -126,6 +126,7 @@ source "arch/riscv/cpu/generic/Kconfig" source "arch/riscv/cpu/jh7110/Kconfig" source "arch/riscv/cpu/k1/Kconfig" source "arch/riscv/cpu/k230/Kconfig" +source "arch/riscv/cpu/th1520/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig new file mode 100644 index 00000000000..a916d364e6c --- /dev/null +++ b/arch/riscv/cpu/th1520/Kconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, Bin Meng +# Copyright (C) 2025, Yao Zi + +config THEAD_TH1520 + bool + select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 + select SUPPORT_SPL + select BINMAN if SPL + select SYS_CACHE_THEAD_CMO + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply RISCV_ACLINT if RISCV_MMODE + imply SPL_RISCV_ACLINT if SPL_RISCV_MMODE + imply CMD_CPU + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT diff --git a/arch/riscv/cpu/th1520/Makefile b/arch/riscv/cpu/th1520/Makefile new file mode 100644 index 00000000000..5d806c06e2e --- /dev/null +++ b/arch/riscv/cpu/th1520/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025, Yao Zi + +obj-y += cache.o +obj-y += cpu.o +obj-y += dram.o +obj-y += spl.o diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c new file mode 100644 index 00000000000..08aa1f789fd --- /dev/null +++ b/arch/riscv/cpu/th1520/cache.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Yao Zi + */ + +#include +#include +#include + +#define CSR_MHCR 0x7c1 +#define CSR_MHCR_IE BIT(0) +#define CSR_MHCR_DE BIT(1) + +void icache_enable(void) +{ + csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE); +} + +void dcache_enable(void) +{ + csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_DE); +} + +int icache_status(void) +{ + return (csr_read(CSR_MHCR) & CSR_MHCR_IE) != 0; +} + +int dcache_status(void) +{ + return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0; +} diff --git a/arch/riscv/cpu/th1520/cpu.c b/arch/riscv/cpu/th1520/cpu.c new file mode 100644 index 00000000000..b83f1272c67 --- /dev/null +++ b/arch/riscv/cpu/th1520/cpu.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 Yao Zi + * + * TH1520 SoC has a set of undocumented customized PMP registers that are + * configured through MMIO operation. It must be disabled before entering + * the DRAM region, or an exception will be raised. + */ + +#include +#include + +#define TH1520_PMP_BASE (void *)0xffdc020000 + +void th1520_invalidate_pmp(void) +{ + /* Invalidate the PMP configuration as in vendor U-Boot code */ + writel(0x0, TH1520_PMP_BASE + 0x0); + + invalidate_icache_all(); +} diff --git a/arch/riscv/cpu/th1520/dram.c b/arch/riscv/cpu/th1520/dram.c new file mode 100644 index 00000000000..91007c0a3d3 --- /dev/null +++ b/arch/riscv/cpu/th1520/dram.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c new file mode 100644 index 00000000000..aec398528d1 --- /dev/null +++ b/arch/riscv/cpu/th1520/spl.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Yao Zi + */ +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_dram_init(void) +{ + int ret; + struct udevice *dev; + + ret = fdtdec_setup_mem_size_base(); + if (ret) { + printf("failed to setup memory size and base: %d\n", ret); + return ret; + } + + /* DDR init */ + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("DRAM init failed: %d\n", ret); + return ret; + } + + return 0; +} diff --git a/arch/riscv/include/asm/arch-th1520/cpu.h b/arch/riscv/include/asm/arch-th1520/cpu.h new file mode 100644 index 00000000000..837f0b8d06b --- /dev/null +++ b/arch/riscv/include/asm/arch-th1520/cpu.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2025 Yao Zi + */ + +#ifndef _ASM_TH1520_CPU_H_ +#define _ASM_TH1520_CPU_H_ +void th1520_invalidate_pmp(void); +#endif /* _ASM_TH1520_CPU_H_ */ diff --git a/arch/riscv/include/asm/arch-th1520/spl.h b/arch/riscv/include/asm/arch-th1520/spl.h new file mode 100644 index 00000000000..59aed8cad62 --- /dev/null +++ b/arch/riscv/include/asm/arch-th1520/spl.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Yao Zi + */ +#ifndef _ASM_ARCH_TH1520_SPL_H_ +#define _ASM_ARCH_TH1520_SPL_H_ + +void spl_dram_init(void); + +#endif // _ASM_ARCH_TH1520_SPL_H_ From 05240d541a407fbb62eec43f40a2b831bb1c1fe0 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:04:57 +0000 Subject: [PATCH 13/23] ram: thead: Add initial DDR controller support for TH1520 This patch cleans the vendor code of DDR initialization up, converts the driver to fit in DM framework and use a firmware[1] packaged by binman to ship PHY configuration. Currently the driver is only capable of initializing the controller to work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants of LicheePi 4A boards and I could test with. Support for other configurations could be easily added later. Link: https://github.com/ziyao233/th1520-firmware # [1] Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- drivers/ram/Kconfig | 1 + drivers/ram/Makefile | 4 + drivers/ram/thead/Kconfig | 5 + drivers/ram/thead/Makefile | 1 + drivers/ram/thead/th1520_ddr.c | 787 +++++++++++++++++++++++++++++++++ 5 files changed, 798 insertions(+) create mode 100644 drivers/ram/thead/Kconfig create mode 100644 drivers/ram/thead/Makefile create mode 100644 drivers/ram/thead/th1520_ddr.c diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 2a40b0c9f81..39d03e8d3d3 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -135,3 +135,4 @@ source "drivers/ram/sifive/Kconfig" source "drivers/ram/stm32mp1/Kconfig" source "drivers/ram/starfive/Kconfig" source "drivers/ram/sunxi/Kconfig" +source "drivers/ram/thead/Kconfig" diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index f92e86eaa3f..82afd5fcbcc 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -30,3 +30,7 @@ obj-$(CONFIG_ARCH_OCTEON) += octeon/ obj-$(CONFIG_ARCH_RENESAS) += renesas/ obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/ + +ifdef CONFIG_XPL_BUILD +obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += thead/ +endif diff --git a/drivers/ram/thead/Kconfig b/drivers/ram/thead/Kconfig new file mode 100644 index 00000000000..7b05abb6986 --- /dev/null +++ b/drivers/ram/thead/Kconfig @@ -0,0 +1,5 @@ +config SPL_THEAD_TH1520_DDR + bool "T-Head TH1520 DDR driver in SPL" + depends on SPL_RAM && THEAD_TH1520 + help + This enables DDR support for T-Head TH1520 platforms. diff --git a/drivers/ram/thead/Makefile b/drivers/ram/thead/Makefile new file mode 100644 index 00000000000..ad4d053cfc2 --- /dev/null +++ b/drivers/ram/thead/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SPL_THEAD_TH1520_DDR) += th1520_ddr.o diff --git a/drivers/ram/thead/th1520_ddr.c b/drivers/ram/thead/th1520_ddr.c new file mode 100644 index 00000000000..bb4736b0236 --- /dev/null +++ b/drivers/ram/thead/th1520_ddr.c @@ -0,0 +1,787 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2024 Alibaba Group Holding Limited + * Copyright (C) 2025 Yao Zi + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#pragma pack(push, 1) + +struct th1520_ddr_fw { + u64 magic; + u8 type, ranknum, bitwidth, freq; + u8 reserved[8]; + + u32 cfgnum; + union th1520_ddr_cfg { + u32 opaddr; + + struct th1520_ddr_phy { + u32 opaddr; + u16 data; + } phy; + + struct th1520_ddr_range { + u32 opaddr; + u32 num; + u16 data[]; + } range; + } cfgs[]; +}; + +#pragma pack(pop) + +/* Firmware constants */ +#define TH1520_DDR_MAGIC 0x4452444445415448 + +#define TH1520_DDR_TYPE_LPDDR4 0 +#define TH1520_DDR_TYPE_LPDDR4X 1 + +#define TH1520_DDR_FREQ_2133 0 +#define TH1520_DDR_FREQ_3200 1 +#define TH1520_DDR_FREQ_3733 2 +#define TH1520_DDR_FREQ_4266 3 + +#define TH1520_DDR_CFG_OP GENMASK(31, 24) +#define TH1520_DDR_CFG_ADDR GENMASK(23, 0) + +#define TH1520_DDR_CFG_PHY0 0 +#define TH1520_DDR_CFG_PHY1 1 +#define TH1520_DDR_CFG_PHY 2 +#define TH1520_DDR_CFG_RANGE 3 +#define TH1520_DDR_CFG_WAITFW0 4 +#define TH1520_DDR_CFG_WAITFW1 5 + +/* Driver constants */ +#define TH1520_SYS_PLL_TIMEOUT_US 30 +#define TH1520_CTRL_INIT_TIMEOUT_US 1000000 +#define TH1520_PHY_MSG_TIMEOUT_US 1000000 + +/* System configuration registers */ +#define TH1520_SYS_DDR_CFG0 0x00 +#define TH1520_SYS_DDR_CFG0_APB_RSTN BIT(4) +#define TH1520_SYS_DDR_CFG0_CTRL_RSTN BIT(5) +#define TH1520_SYS_DDR_CFG0_PHY_PWROK_RSTN BIT(6) +#define TH1520_SYS_DDR_CFG0_PHY_CORE_RSTN BIT(7) +#define TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(n) BIT(n + 4 + 4) +#define TH1520_SYS_DDR_CFG1 0x04 +#define TH1520_SYS_PLL_CFG0 0x08 +#define TH1520_SYS_PLL_CFG0_POSTDIV2 GENMASK(26, 24) +#define TH1520_SYS_PLL_CFG0_POSTDIV1 GENMASK(22, 20) +#define TH1520_SYS_PLL_CFG0_FBDIV GENMASK(19, 8) +#define TH1520_SYS_PLL_CFG0_REFDIV GENMASK(5, 0) +#define TH1520_SYS_PLL_CFG1 0x0c +#define TH1520_SYS_PLL_CFG1_RST BIT(30) +#define TH1520_SYS_PLL_CFG1_FOUTPOSTDIVPD BIT(27) +#define TH1520_SYS_PLL_CFG1_FOUT4PHASEPD BIT(25) +#define Th1520_SYS_PLL_CFG1_DACPD BIT(24) +#define TH1520_SYS_PLL_CFG2 0x10 +#define TH1520_SYS_PLL_CFG3 0x14 +#define TH1520_SYS_PLL_STS 0x18 +#define TH1520_SYS_PLL_STS_EN BIT(16) +#define TH1520_SYS_PLL_STS_LOCKED BIT(0) + +/* DDR Controller Registers */ +#define TH1520_CTRL_MSTR 0x0000 +#define TH1520_CTRL_STAT 0x0004 +#define TH1520_CTRL_MRCTRL0 0x0010 +#define TH1520_CTRL_MRCTRL1 0x0014 +#define TH1520_CTRL_MRSTAT 0x0018 +#define TH1520_CTRL_DERATEEN 0x0020 +#define TH1520_CTRL_DERATEINT 0x0024 +#define TH1520_CTRL_DERATECTL 0x002c +#define TH1520_CTRL_PWRCTL 0x0030 +#define TH1520_CTRL_PWRTMG 0x0034 +#define TH1520_CTRL_HWLPCTL 0x0038 +#define TH1520_CTRL_RFSHCTL0 0x0050 +#define TH1520_CTRL_RFSHCTL1 0x0054 +#define TH1520_CTRL_RFSHCTL3 0x0060 +#define TH1520_CTRL_RFSHTMG 0x0064 +#define TH1520_CTRL_RFSHTMG1 0x0068 +#define TH1520_CTRL_CRCPARCTL0 0x00c0 +#define TH1520_CTRL_CRCPARSTAT 0x00cc +#define TH1520_CTRL_INIT0 0x00d0 +#define TH1520_CTRL_INIT1 0x00d4 +#define TH1520_CTRL_INIT2 0x00d8 +#define TH1520_CTRL_INIT3 0x00dc +#define TH1520_CTRL_INIT4 0x00e0 +#define TH1520_CTRL_INIT5 0x00e4 +#define TH1520_CTRL_INIT6 0x00e8 +#define TH1520_CTRL_INIT7 0x00ec +#define TH1520_CTRL_DIMMCTL 0x00f0 +#define TH1520_CTRL_RANKCTL 0x00f4 +#define TH1520_CTRL_RANKCTL1 0x00f8 +#define TH1520_CTRL_DRAMTMG0 0x0100 +#define TH1520_CTRL_DRAMTMG1 0x0104 +#define TH1520_CTRL_DRAMTMG2 0x0108 +#define TH1520_CTRL_DRAMTMG3 0x010c +#define TH1520_CTRL_DRAMTMG4 0x0110 +#define TH1520_CTRL_DRAMTMG5 0x0114 +#define TH1520_CTRL_DRAMTMG6 0x0118 +#define TH1520_CTRL_DRAMTMG7 0x011c +#define TH1520_CTRL_DRAMTMG8 0x0120 +#define TH1520_CTRL_DRAMTMG12 0x0130 +#define TH1520_CTRL_DRAMTMG13 0x0134 +#define TH1520_CTRL_DRAMTMG14 0x0138 +#define TH1520_CTRL_DRAMTMG17 0x0144 +#define TH1520_CTRL_ZQCTL0 0x0180 +#define TH1520_CTRL_ZQCTL1 0x0184 +#define TH1520_CTRL_ZQCTL2 0x0188 +#define TH1520_CTRL_ZQSTAT 0x018c +#define TH1520_CTRL_DFITMG0 0x0190 +#define TH1520_CTRL_DFITMG1 0x0194 +#define TH1520_CTRL_DFILPCFG0 0x0198 +#define TH1520_CTRL_DFIUPD0 0x01a0 +#define TH1520_CTRL_DFIUPD1 0x01a4 +#define TH1520_CTRL_DFIUPD2 0x01a8 +#define TH1520_CTRL_DFIMISC 0x01b0 +#define TH1520_CTRL_DFITMG2 0x01b4 +#define TH1520_CTRL_DFISTAT 0x01bc +#define TH1520_CTRL_DBICTL 0x01c0 +#define TH1520_CTRL_DFIPHYMSTR 0x01c4 +#define TH1520_CTRL_ADDRMAP0 0x0200 +#define TH1520_CTRL_ADDRMAP1 0x0204 +#define TH1520_CTRL_ADDRMAP2 0x0208 +#define TH1520_CTRL_ADDRMAP3 0x020c +#define TH1520_CTRL_ADDRMAP4 0x0210 +#define TH1520_CTRL_ADDRMAP5 0x0214 +#define TH1520_CTRL_ADDRMAP6 0x0218 +#define TH1520_CTRL_ADDRMAP7 0x021c +#define TH1520_CTRL_ADDRMAP8 0x0220 +#define TH1520_CTRL_ADDRMAP9 0x0224 +#define TH1520_CTRL_ADDRMAP10 0x0228 +#define TH1520_CTRL_ADDRMAP11 0x022c +#define TH1520_CTRL_ODTCFG 0x0240 +#define TH1520_CTRL_ODTMAP 0x0244 +#define TH1520_CTRL_SCHED 0x0250 +#define TH1520_CTRL_SCHED1 0x0254 +#define TH1520_CTRL_PERFHPR1 0x025c +#define TH1520_CTRL_PERFLPR1 0x0264 +#define TH1520_CTRL_PERFWR1 0x026c +#define TH1520_CTRL_SCHED3 0x0270 +#define TH1520_CTRL_SCHED4 0x0274 +#define TH1520_CTRL_DBG0 0x0300 +#define TH1520_CTRL_DBG1 0x0304 +#define TH1520_CTRL_DBGCAM 0x0308 +#define TH1520_CTRL_DBGCMD 0x030c +#define TH1520_CTRL_DBGSTAT 0x0310 +#define TH1520_CTRL_SWCTL 0x0320 +#define TH1520_CTRL_SWSTAT 0x0324 +#define TH1520_CTRL_SWCTLSTATIC 0x0328 +#define TH1520_CTRL_POISONCFG 0x036c +#define TH1520_CTRL_POISONSTAT 0x0370 +#define TH1520_CTRL_DERATESTAT 0x03f0 +#define TH1520_CTRL_PSTAT 0x03fc +#define TH1520_CTRL_PCCFG 0x0400 +#define TH1520_CTRL_PCFGR_0 0x0404 +#define TH1520_CTRL_PCFGW_0 0x0408 +#define TH1520_CTRL_PCTRL_0 0x0490 +#define TH1520_CTRL_PCFGQOS0_0 0x0494 +#define TH1520_CTRL_PCFGQOS1_0 0x0498 +#define TH1520_CTRL_PCFGWQOS0_0 0x049c +#define TH1520_CTRL_PCFGWQOS1_0 0x04a0 +#define TH1520_CTRL_PCFGR_1 0x04b4 +#define TH1520_CTRL_PCFGW_1 0x04b8 +#define TH1520_CTRL_PCTRL_1 0x0540 +#define TH1520_CTRL_PCFGQOS0_1 0x0544 +#define TH1520_CTRL_PCFGQOS1_1 0x0548 +#define TH1520_CTRL_PCFGWQOS0_1 0x054c +#define TH1520_CTRL_PCFGWQOS1_1 0x0550 +#define TH1520_CTRL_PCFGR_2 0x0564 +#define TH1520_CTRL_PCFGW_2 0x0568 +#define TH1520_CTRL_PCTRL_2 0x05f0 +#define TH1520_CTRL_PCFGQOS0_2 0x05f4 +#define TH1520_CTRL_PCFGQOS1_2 0x05f8 +#define TH1520_CTRL_PCFGWQOS0_2 0x05fc +#define TH1520_CTRL_PCFGWQOS1_2 0x0600 +#define TH1520_CTRL_PCFGR_3 0x0614 +#define TH1520_CTRL_PCFGW_3 0x0618 +#define TH1520_CTRL_PCTRL_3 0x06a0 +#define TH1520_CTRL_PCFGQOS0_3 0x06a4 +#define TH1520_CTRL_PCFGQOS1_3 0x06a8 +#define TH1520_CTRL_PCFGWQOS0_3 0x06ac +#define TH1520_CTRL_PCFGWQOS1_3 0x06b0 +#define TH1520_CTRL_PCFGR_4 0x06c4 +#define TH1520_CTRL_PCFGW_4 0x06c8 +#define TH1520_CTRL_PCTRL_4 0x0750 +#define TH1520_CTRL_PCFGQOS0_4 0x0754 +#define TH1520_CTRL_PCFGQOS1_4 0x0758 +#define TH1520_CTRL_PCFGWQOS0_4 0x075c +#define TH1520_CTRL_PCFGWQOS1_4 0x0760 +#define TH1520_CTRL_UMCTL2_VER_NUMBER 0x0ff0 +#define TH1520_CTRL_UMCTL2_VER_TYPE 0x0ff4 +#define TH1520_CTRL_DCH1_STAT 0x1b04 +#define TH1520_CTRL_DCH1_MRCTRL0 0x1b10 +#define TH1520_CTRL_DCH1_MRCTRL1 0x1b14 +#define TH1520_CTRL_DCH1_MRSTAT 0x1b18 +#define TH1520_CTRL_DCH1_DERATECTL 0x1b2c +#define TH1520_CTRL_DCH1_PWRCTL 0x1b30 +#define TH1520_CTRL_DCH1_HWLPCTL 0x1b38 +#define TH1520_CTRL_DCH1_CRCPARCTL0 0x1bc0 +#define TH1520_CTRL_DCH1_ZQCTL2 0x1c88 +#define TH1520_CTRL_DCH1_DFISTAT 0x1cbc +#define TH1520_CTRL_DCH1_ODTMAP 0x1d44 +#define TH1520_CTRL_DCH1_DBG1 0x1e04 +#define TH1520_CTRL_DCH1_DBGCMD 0x1e0c +#define TH1520_CTRL_DCH1_DBGCAM 0x1e08 + +/* PHY configuration registers */ +#define TH1520_DDR_PHY_REG(regid) ((regid) * 2) + +/* UctShadowRegs */ +#define TH1520_PHY_MSG_STATUS TH1520_DDR_PHY_REG(0xd0004) +#define TH1520_PHY_MSG_STATUS_EMPTY BIT(0) +/* DctWriteProt */ +#define TH1520_PHY_MSG_ACK TH1520_DDR_PHY_REG(0xd0031) +#define TH1520_PHY_MSG_ACK_EN BIT(0) +/* UctWriteOnlyShadow */ +#define TH1520_PHY_MSG_ID TH1520_DDR_PHY_REG(0xd0032) +#define TH1520_PHY_MSG_ID_COMPLETION 0x7 +#define TH1520_PHY_MSG_ID_ERROR 0xff +/* UctDatWriteOnlyShadow */ +#define TH1520_PHY_MSG_DATA TH1520_DDR_PHY_REG(0xd0034) + +struct th1520_ddr_priv { + void __iomem *phy0; + void __iomem *phy1; + void __iomem *ctrl; + void __iomem *sys; +}; + +binman_sym_declare(ulong, ddr_fw, image_pos); + +static int th1520_ddr_pll_config(void __iomem *sysreg, unsigned int frequency) +{ + u32 tmp; + int ret; + + tmp = TH1520_SYS_PLL_CFG1_RST | + TH1520_SYS_PLL_CFG1_FOUTPOSTDIVPD | + TH1520_SYS_PLL_CFG1_FOUT4PHASEPD | + Th1520_SYS_PLL_CFG1_DACPD; + writel(tmp, sysreg + TH1520_SYS_PLL_CFG1); + + switch (frequency) { + case TH1520_DDR_FREQ_3733: + writel(FIELD_PREP(TH1520_SYS_PLL_CFG0_REFDIV, 1) | + FIELD_PREP(TH1520_SYS_PLL_CFG0_FBDIV, 77) | + FIELD_PREP(TH1520_SYS_PLL_CFG0_POSTDIV1, 2) | + FIELD_PREP(TH1520_SYS_PLL_CFG0_POSTDIV2, 1), + sysreg + TH1520_SYS_PLL_CFG0); + break; + default: + return -EINVAL; + } + + udelay(2); + tmp &= ~TH1520_SYS_PLL_CFG1_RST; + writel(tmp, sysreg + TH1520_SYS_PLL_CFG1); + + ret = readl_poll_timeout(sysreg + TH1520_SYS_PLL_STS, tmp, + tmp & TH1520_SYS_PLL_STS_LOCKED, + TH1520_SYS_PLL_TIMEOUT_US); + + writel(TH1520_SYS_PLL_STS_EN, sysreg + TH1520_SYS_PLL_STS); + + return ret; +} + +static int th1520_ddr_ctrl_init(void __iomem *ctrlreg, struct th1520_ddr_fw *fw) +{ + int ret; + u32 tmp; + + writel(0x00000001, ctrlreg + TH1520_CTRL_DBG1); + writel(0x00000001, ctrlreg + TH1520_CTRL_PWRCTL); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_STAT, tmp, + tmp == 0x00000000, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + if (fw->ranknum == 2) + writel(0x03080020, ctrlreg + TH1520_CTRL_MSTR); + else + return -EINVAL; + + writel(0x00003030, ctrlreg + TH1520_CTRL_MRCTRL0); + writel(0x0002d90f, ctrlreg + TH1520_CTRL_MRCTRL1); + + switch (fw->freq) { + case TH1520_DDR_FREQ_3733: + writel(0x000013f3, ctrlreg + TH1520_CTRL_DERATEEN); + writel(0x40000000, ctrlreg + TH1520_CTRL_DERATEINT); + writel(0x00000001, ctrlreg + TH1520_CTRL_DERATECTL); + writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL); + writel(0x0040ae04, ctrlreg + TH1520_CTRL_PWRTMG); + writel(0x00430000, ctrlreg + TH1520_CTRL_HWLPCTL); + writel(0x00210004, ctrlreg + TH1520_CTRL_RFSHCTL0); + writel(0x000d0021, ctrlreg + TH1520_CTRL_RFSHCTL1); + writel(0x00000001, ctrlreg + TH1520_CTRL_RFSHCTL3); + writel(0x81c00084, ctrlreg + TH1520_CTRL_RFSHTMG); + writel(0x00540000, ctrlreg + TH1520_CTRL_RFSHTMG1); + writel(0x00000000, ctrlreg + TH1520_CTRL_CRCPARCTL0); + writel(0xc0020002, ctrlreg + TH1520_CTRL_INIT0); + writel(0x00010002, ctrlreg + TH1520_CTRL_INIT1); + writel(0x00001f00, ctrlreg + TH1520_CTRL_INIT2); + writel(0x00640036, ctrlreg + TH1520_CTRL_INIT3); + writel(0x00f20008, ctrlreg + TH1520_CTRL_INIT4); + writel(0x0004000b, ctrlreg + TH1520_CTRL_INIT5); + writel(0x00440012, ctrlreg + TH1520_CTRL_INIT6); + writel(0x0004001a, ctrlreg + TH1520_CTRL_INIT7); + writel(0x00000000, ctrlreg + TH1520_CTRL_DIMMCTL); + writel(0x0000ab9f, ctrlreg + TH1520_CTRL_RANKCTL); + writel(0x00000017, ctrlreg + TH1520_CTRL_RANKCTL1); + writel(0x1f263f28, ctrlreg + TH1520_CTRL_DRAMTMG0); + writel(0x00080839, ctrlreg + TH1520_CTRL_DRAMTMG1); + writel(0x08121d17, ctrlreg + TH1520_CTRL_DRAMTMG2); + writel(0x00d0e000, ctrlreg + TH1520_CTRL_DRAMTMG3); + writel(0x11040a12, ctrlreg + TH1520_CTRL_DRAMTMG4); + writel(0x02050e0e, ctrlreg + TH1520_CTRL_DRAMTMG5); + writel(0x01010008, ctrlreg + TH1520_CTRL_DRAMTMG6); + writel(0x00000502, ctrlreg + TH1520_CTRL_DRAMTMG7); + writel(0x00000101, ctrlreg + TH1520_CTRL_DRAMTMG8); + writel(0x00020000, ctrlreg + TH1520_CTRL_DRAMTMG12); + writel(0x0d100002, ctrlreg + TH1520_CTRL_DRAMTMG13); + writel(0x0000010c, ctrlreg + TH1520_CTRL_DRAMTMG14); + writel(0x03a50021, ctrlreg + TH1520_CTRL_ZQCTL0); + writel(0x02f00800, ctrlreg + TH1520_CTRL_ZQCTL1); + writel(0x00000000, ctrlreg + TH1520_CTRL_ZQCTL2); + writel(0x059f820c, ctrlreg + TH1520_CTRL_DFITMG0); + writel(0x000c0303, ctrlreg + TH1520_CTRL_DFITMG1); + writel(0x0351a101, ctrlreg + TH1520_CTRL_DFILPCFG0); + writel(0x00000011, ctrlreg + TH1520_CTRL_DFIMISC); + writel(0x00001f0c, ctrlreg + TH1520_CTRL_DFITMG2); + writel(0x00000007, ctrlreg + TH1520_CTRL_DBICTL); + writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR); + writel(0x06090b40, ctrlreg + TH1520_CTRL_ODTCFG); + break; + default: + return -EINVAL; + } + + writel(0x00400018, ctrlreg + TH1520_CTRL_DFIUPD0); + writel(0x00280032, ctrlreg + TH1520_CTRL_DFIUPD1); + writel(0x00000000, ctrlreg + TH1520_CTRL_DFIUPD2); + writel(0x00000000, ctrlreg + TH1520_CTRL_ODTMAP); + writel(0x1f829b1c, ctrlreg + TH1520_CTRL_SCHED); + writel(0x4400b00f, ctrlreg + TH1520_CTRL_SCHED1); + writel(0x0f000001, ctrlreg + TH1520_CTRL_PERFHPR1); + writel(0x0f00007f, ctrlreg + TH1520_CTRL_PERFLPR1); + writel(0x0f00007f, ctrlreg + TH1520_CTRL_PERFWR1); + writel(0x00000208, ctrlreg + TH1520_CTRL_SCHED3); + writel(0x08400810, ctrlreg + TH1520_CTRL_SCHED4); + writel(0x00000000, ctrlreg + TH1520_CTRL_DBG0); + writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1); + writel(0x00000000, ctrlreg + TH1520_CTRL_DBGCMD); + writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL); + writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTLSTATIC); + writel(0x00000001, ctrlreg + TH1520_CTRL_POISONCFG); + writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_0); + writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_1); + writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_2); + writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_3); + writel(0x00000001, ctrlreg + TH1520_CTRL_PCTRL_4); + writel(0x00003030, ctrlreg + TH1520_CTRL_DCH1_MRCTRL0); + writel(0x0002d90f, ctrlreg + TH1520_CTRL_DCH1_MRCTRL1); + writel(0x00000001, ctrlreg + TH1520_CTRL_DCH1_DERATECTL); + writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL); + writel(0x00430002, ctrlreg + TH1520_CTRL_DCH1_HWLPCTL); + writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_CRCPARCTL0); + writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_ZQCTL2); + writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_ODTMAP); + writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1); + writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBGCMD); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_RFSHCTL3, tmp, + tmp == 0x00000001, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + writel(0x00000010, ctrlreg + TH1520_CTRL_PCCFG); + writel(0x0000500f, ctrlreg + TH1520_CTRL_PCFGR_0); + writel(0x0000500f, ctrlreg + TH1520_CTRL_PCFGW_0); + writel(0x00005020, ctrlreg + TH1520_CTRL_PCFGR_1); + writel(0x0000501f, ctrlreg + TH1520_CTRL_PCFGW_1); + writel(0x0000501f, ctrlreg + TH1520_CTRL_PCFGR_2); + writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGW_2); + writel(0x000051ff, ctrlreg + TH1520_CTRL_PCFGR_3); + writel(0x000051ff, ctrlreg + TH1520_CTRL_PCFGW_3); + writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGR_4); + writel(0x0000503f, ctrlreg + TH1520_CTRL_PCFGW_4); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp, + tmp == 0x00000020, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp, + tmp == 0x00000020, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL); + writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp, + tmp == 0x00000020, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_PWRCTL, tmp, + tmp == 0x00000020, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + writel(0x00000020, ctrlreg + TH1520_CTRL_PWRCTL); + writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp, + tmp == 0x00000020, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_PWRCTL, tmp, + tmp == 0x00000020, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + writel(0x00000020, ctrlreg + TH1520_CTRL_DCH1_PWRCTL); + writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR); + writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL); + writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC); + writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC); + writel(0x00000002, ctrlreg + TH1520_CTRL_DBG1); + writel(0x00000002, ctrlreg + TH1520_CTRL_DCH1_DBG1); + + switch (fw->bitwidth) { + case 64: + writel(0x00040018, ctrlreg + TH1520_CTRL_ADDRMAP0); + writel(0x00090909, ctrlreg + TH1520_CTRL_ADDRMAP1); + writel(0x00000000, ctrlreg + TH1520_CTRL_ADDRMAP2); + writel(0x01010101, ctrlreg + TH1520_CTRL_ADDRMAP3); + writel(0x00001f1f, ctrlreg + TH1520_CTRL_ADDRMAP4); + writel(0x080f0808, ctrlreg + TH1520_CTRL_ADDRMAP5); + writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP6); + writel(0x00000f0f, ctrlreg + TH1520_CTRL_ADDRMAP7); + writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP9); + writel(0x08080808, ctrlreg + TH1520_CTRL_ADDRMAP10); + writel(0x00000008, ctrlreg + TH1520_CTRL_ADDRMAP11); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int th1520_ddr_read_msg(void __iomem *phyreg, u16 *id, u16 *data) +{ + u32 tmp; + int ret; + + ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp, + !(tmp & TH1520_PHY_MSG_STATUS_EMPTY), + TH1520_PHY_MSG_TIMEOUT_US); + if (ret) + return ret; + + *id = readw(phyreg + TH1520_PHY_MSG_ID); + *data = readw(phyreg + TH1520_PHY_MSG_DATA); + + writew(0, phyreg + TH1520_PHY_MSG_ACK); + + ret = readw_poll_timeout(phyreg + TH1520_PHY_MSG_STATUS, tmp, + tmp & TH1520_PHY_MSG_STATUS_EMPTY, + TH1520_PHY_MSG_TIMEOUT_US); + if (ret) + return ret; + + writew(TH1520_PHY_MSG_ACK_EN, phyreg + TH1520_PHY_MSG_ACK); + + return 0; +} + +static int th1520_phy_wait_pmu_completion(void __iomem *phyreg) +{ + u16 id, data; + int ret; + + do { + ret = th1520_ddr_read_msg(phyreg, &id, &data); + + if (ret) + return ret; + } while (id != TH1520_PHY_MSG_ID_COMPLETION && + id != TH1520_PHY_MSG_ID_ERROR && + !ret); + + return id == TH1520_PHY_MSG_ID_COMPLETION ? ret : -EIO; +} + +static int lpddr4_load_firmware(struct th1520_ddr_priv *priv, + struct th1520_ddr_fw *fw) +{ + union th1520_ddr_cfg *cfg; + size_t i, j; + int ret; + + for (cfg = fw->cfgs, i = 0; i < fw->cfgnum; i++) { + u32 addr = FIELD_GET(TH1520_DDR_CFG_ADDR, cfg->opaddr) * 2; + u32 op = FIELD_GET(TH1520_DDR_CFG_OP, cfg->opaddr); + + switch (op) { + case TH1520_DDR_CFG_PHY0: + writew(cfg->phy.data, priv->phy0 + addr); + break; + case TH1520_DDR_CFG_PHY1: + writew(cfg->phy.data, priv->phy1 + addr); + break; + case TH1520_DDR_CFG_PHY: + writew(cfg->phy.data, priv->phy0 + addr); + writew(cfg->phy.data, priv->phy1 + addr); + break; + case TH1520_DDR_CFG_RANGE: + for (j = 0; j < cfg->range.num; j++) { + writew(cfg->range.data[j], + priv->phy0 + addr + j * 2); + writew(cfg->range.data[j], + priv->phy1 + addr + j * 2); + } + break; + case TH1520_DDR_CFG_WAITFW0: + ret = th1520_phy_wait_pmu_completion(priv->phy0); + + if (ret) { + pr_err("phy 0 training failed: %d\n", ret); + return ret; + } + + break; + case TH1520_DDR_CFG_WAITFW1: + ret = th1520_phy_wait_pmu_completion(priv->phy1); + + if (ret) { + pr_err("phy 1 training failed: %d\n", ret); + return ret; + } + + break; + default: + pr_err("Unknown DRAM configuration %d\n", op); + + return -EOPNOTSUPP; + } + + if (op == TH1520_DDR_CFG_RANGE) + cfg = (void *)cfg + sizeof(cfg->range) + + cfg->range.num * sizeof(u16); + else + cfg = (union th1520_ddr_cfg *)(&cfg->phy + 1); + } + + return 0; +} + +static int th1520_ddr_ctrl_enable(void __iomem *ctrlreg, + struct th1520_ddr_fw *fw) +{ + u32 tmp; + int ret; + + writel(0x00000030, ctrlreg + TH1520_CTRL_DFIMISC); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DFISTAT, tmp, + tmp == 0x00000001, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_DFISTAT, tmp, + tmp == 0x00000001, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + writel(0x00000010, ctrlreg + TH1520_CTRL_DFIMISC); + writel(0x00000011, ctrlreg + TH1520_CTRL_DFIMISC); + writel(0x0000000a, ctrlreg + TH1520_CTRL_PWRCTL); + writel(0x0000000a, ctrlreg + TH1520_CTRL_DCH1_PWRCTL); + writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_SWSTAT, tmp, + tmp == 0x00000001, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_STAT, tmp, + tmp == 0x00000001, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_DCH1_STAT, tmp, + tmp == 0x00000001, + TH1520_CTRL_INIT_TIMEOUT_US); + if (ret) + return ret; + + writel(0x14000001, ctrlreg + TH1520_CTRL_DFIPHYMSTR); + writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL); + writel(0x00020002, ctrlreg + TH1520_CTRL_INIT0); + writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL); + + ret = readl_poll_timeout(ctrlreg + TH1520_CTRL_SWSTAT, tmp, + tmp == 0x00000001, + TH1520_CTRL_INIT_TIMEOUT_US); + + if (ret) + return ret; + + writel(0x00000000, ctrlreg + TH1520_CTRL_DBG1); + writel(0x00000000, ctrlreg + TH1520_CTRL_DCH1_DBG1); + + return 0; +} + +static void th1520_ddr_enable_self_refresh(void __iomem *ctrlreg, + void __iomem *sysreg) +{ + writel(0x00000000, ctrlreg + TH1520_CTRL_RFSHCTL3); + + writel(0x000a0000, sysreg + TH1520_SYS_DDR_CFG1); + + writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTL); + writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTLSTATIC); + writel(0x0040ae04, ctrlreg + TH1520_CTRL_PWRTMG); + writel(0x00430003, ctrlreg + TH1520_CTRL_HWLPCTL); + writel(0x00430003, ctrlreg + TH1520_CTRL_DCH1_HWLPCTL); + writel(0x00000001, ctrlreg + TH1520_CTRL_SWCTL); + writel(0x00000000, ctrlreg + TH1520_CTRL_SWCTLSTATIC); + writel(0x0000000b, ctrlreg + TH1520_CTRL_PWRCTL); + writel(0x0000000b, ctrlreg + TH1520_CTRL_DCH1_PWRCTL); +} + +static int th1520_ddr_init(struct th1520_ddr_priv *priv) +{ + struct th1520_ddr_fw *fw = (void *)binman_sym(ulong, ddr_fw, image_pos); + u32 reset; + int ret; + + ret = th1520_ddr_pll_config(priv->sys, fw->freq); + if (ret) { + pr_err("failed to configure PLL: %d\n", ret); + return ret; + } + + reset = TH1520_SYS_DDR_CFG0_PHY_PWROK_RSTN; + writel(reset, priv->sys + TH1520_SYS_DDR_CFG0); + reset |= TH1520_SYS_DDR_CFG0_PHY_CORE_RSTN; + writel(reset, priv->sys + TH1520_SYS_DDR_CFG0); + reset |= TH1520_SYS_DDR_CFG0_APB_RSTN; + writel(reset, priv->sys + TH1520_SYS_DDR_CFG0); + + ret = th1520_ddr_ctrl_init(priv->ctrl, fw); + if (ret) { + pr_err("failed to initialize DDR controller: %d\n", ret); + return ret; + } + + reset |= TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(0) | + TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(1) | + TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(2) | + TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(3) | + TH1520_SYS_DDR_CFG0_APB_PORT_RSTN(4) | + TH1520_SYS_DDR_CFG0_CTRL_RSTN; + writel(reset, priv->sys + TH1520_SYS_DDR_CFG0); + + lpddr4_load_firmware(priv, fw); + + ret = th1520_ddr_ctrl_enable(priv->ctrl, fw); + if (ret) { + pr_err("failed to enable DDR controller: %d\n", ret); + return ret; + } + + th1520_ddr_enable_self_refresh(priv->ctrl, priv->sys); + + return 0; +} + +static int th1520_ddr_probe(struct udevice *dev) +{ + struct th1520_ddr_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = dev_read_addr_name(dev, "phy-0"); + priv->phy0 = (void __iomem *)addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + addr = dev_read_addr_name(dev, "phy-1"); + priv->phy1 = (void __iomem *)addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + addr = dev_read_addr_name(dev, "ctrl"); + priv->ctrl = (void __iomem *)addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + addr = dev_read_addr_name(dev, "sys"); + priv->sys = (void __iomem *)addr; + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + return th1520_ddr_init(priv); +} + +static int th1520_ddr_get_info(struct udevice *dev, struct ram_info *info) +{ + info->base = gd->ram_base; + info->size = gd->ram_size; + + return 0; +} + +static struct ram_ops th1520_ddr_ops = { + .get_info = th1520_ddr_get_info, +}; + +static const struct udevice_id th1520_ddr_ids[] = { + { .compatible = "thead,th1520-ddrc" }, + { } +}; + +U_BOOT_DRIVER(th1520_ddr) = { + .name = "th1520_ddr", + .id = UCLASS_RAM, + .ops = &th1520_ddr_ops, + .of_match = th1520_ddr_ids, + .probe = th1520_ddr_probe, + .priv_auto = sizeof(struct th1520_ddr_priv), +}; From 976b90f9dac27a2d29064f23cfc3b3cd12417bc8 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:04:58 +0000 Subject: [PATCH 14/23] riscv: dts: th1520: Preserve necessary devices for SPL SPL for TH1520 requires CPU and boot UART nodes to function. Preserve them in SPL devicetree blob with bootph-pre-ram property. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/th1520.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index cbe3481fadd..b34ac323503 100644 --- a/arch/riscv/dts/th1520.dtsi +++ b/arch/riscv/dts/th1520.dtsi @@ -14,6 +14,7 @@ cpus: cpus { #address-cells = <1>; #size-cells = <0>; + bootph-pre-ram; timebase-frequency = <3000000>; c910_0: cpu@0 { @@ -21,6 +22,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <0>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -42,6 +44,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <1>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -63,6 +66,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <2>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -84,6 +88,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <3>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -173,6 +178,7 @@ uart0: serial@ffe7014000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7014000 0x0 0x100>; + bootph-pre-ram; interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart_sclk>; reg-shift = <2>; From 17582da96c30435d9356a0cd5b74bee41a48c578 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:04:59 +0000 Subject: [PATCH 15/23] riscv: dts: lichee-module-4a: Preserve memory node for SPL Memory node is necessary for TH1520 SPL to configure size and base address of DRAM. Let's preserve it in SPL devicetree blob. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi index 86a81bdcf77..20dbc4c7d24 100644 --- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -14,6 +14,7 @@ memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x2 0x00000000>; + bootph-pre-ram; }; }; From 64735e56aa0ae5cf37fed25dbcc16934bfb2bfce Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:05:00 +0000 Subject: [PATCH 16/23] riscv: dts: th1520: Add DRAM controller Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL devicetree blob. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/th1520.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index b34ac323503..4a523f8048b 100644 --- a/arch/riscv/dts/th1520.dtsi +++ b/arch/riscv/dts/th1520.dtsi @@ -371,6 +371,16 @@ status = "disabled"; }; + ddrc: ddrc@fffd000000 { + compatible = "thead,th1520-ddrc"; + reg = <0xff 0xfd000000 0x0 0x1000000>, + <0xff 0xfe000000 0x0 0x1000000>, + <0xff 0xff000000 0x0 0x4000>, + <0xff 0xff005000 0x0 0x1000>; + reg-names = "phy-0", "phy-1", "ctrl", "sys"; + bootph-pre-ram; + }; + timer4: timer@ffffc33000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33000 0x0 0x14>; From 19ec61b3e6c9c9b027d50eda9f03929bdd00b4a9 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:05:01 +0000 Subject: [PATCH 17/23] riscv: dts: th1520: Add binman configuration Add binman configuration for TH1520 SoC, whose BROM loads the image combined into SRAM and directly jumps to it. The configuration creates u-boot-with-spl.bin where the SPL code locates at the start and the DDR firmware is shipped. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/thead-th1520-binman.dtsi | 55 +++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 arch/riscv/dts/thead-th1520-binman.dtsi diff --git a/arch/riscv/dts/thead-th1520-binman.dtsi b/arch/riscv/dts/thead-th1520-binman.dtsi new file mode 100644 index 00000000000..f060639e1c6 --- /dev/null +++ b/arch/riscv/dts/thead-th1520-binman.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Yao Zi + */ + +#include + +/ { + binman: binman { + }; +}; + +&binman { + filename = "u-boot-with-spl.bin"; + + u-boot-spl { + }; + + ddr-fw { + filename = "th1520-ddr-firmware.bin"; + type = "blob-ext"; + }; + + fit { + offset = ; + + description = "Configuration to load M-mode U-Boot"; + + #address-cells = <2>; + fit,fdt-list = "of-list"; + + images { + uboot { + description = "U-Boot"; + type = "standalone"; + os = "U-boot"; + arch = "riscv"; + compression = "none"; + load = /bits/ 64 ; + + uboot_blob: u-boot { + }; + }; + }; + + configurations { + default = "conf-th1520-lichee-pi-4a"; + + conf-th1520-lichee-pi-4a { + description = "th1520-lichee-pi-4a"; + loadables = "uboot"; + }; + }; + }; +}; From 38ed760bc90722207060ff16e370e4ea3f7f3db3 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:05:02 +0000 Subject: [PATCH 18/23] board: thead: licheepi4a: Enable SPL support Adjust Kconfig and defconfig and add SPL initialization code for Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC earlier. The board devicetree is changed to use TH1520 binman configuration to generate bootable images. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/th1520-lichee-pi-4a.dts | 1 + board/thead/th1520_lpi4a/Kconfig | 5 +-- board/thead/th1520_lpi4a/Makefile | 1 + board/thead/th1520_lpi4a/spl.c | 48 ++++++++++++++++++++++++++ configs/th1520_lpi4a_defconfig | 18 ++++++++++ 5 files changed, 71 insertions(+), 2 deletions(-) create mode 100644 board/thead/th1520_lpi4a/spl.c diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts index a1248b2ee3a..49af88b7adf 100644 --- a/arch/riscv/dts/th1520-lichee-pi-4a.dts +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts @@ -4,6 +4,7 @@ */ #include "th1520-lichee-module-4a.dtsi" +#include "thead-th1520-binman.dtsi" / { model = "Sipeed Lichee Pi 4A"; diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig index 622246127c1..f139d5ff2bb 100644 --- a/board/thead/th1520_lpi4a/Kconfig +++ b/board/thead/th1520_lpi4a/Kconfig @@ -11,7 +11,7 @@ config SYS_VENDOR default "thead" config SYS_CPU - default "generic" + default "th1520" config SYS_CONFIG_NAME default "th1520_lpi4a" @@ -22,7 +22,7 @@ config TEXT_BASE default 0x01c00000 if RISCV_SMODE config SPL_TEXT_BASE - default 0x08000000 + default 0xffe0000000 config SPL_OPENSBI_LOAD_ADDR default 0x80000000 @@ -30,6 +30,7 @@ config SPL_OPENSBI_LOAD_ADDR config BOARD_SPECIFIC_OPTIONS def_bool y select ARCH_EARLY_INIT_R + select THEAD_TH1520 imply CPU imply CPU_RISCV imply RISCV_TIMER if RISCV_SMODE diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile index 9671b3bbb0b..a7ddfc48d40 100644 --- a/board/thead/th1520_lpi4a/Makefile +++ b/board/thead/th1520_lpi4a/Makefile @@ -3,3 +3,4 @@ # Copyright (c) 2023, Yixun Lan obj-y += board.o +obj-$(CONFIG_XPL_BUILD) += spl.o diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c new file mode 100644 index 00000000000..25dfa387c36 --- /dev/null +++ b/board/thead/th1520_lpi4a/spl.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025, Yao Zi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +u32 spl_boot_device(void) +{ + /* + * We don't bother to load proper U-Boot from an external device as + * it fits in the integrated SRAM nicely. + */ + return BOOT_DEVICE_RAM; +} + +void board_init_f(ulong dummy) +{ + int ret = spl_early_init(); + struct udevice *dev; + + if (ret) + panic("spl_early_init() failed %d\n", ret); + + preloader_console_init(); + + /* + * Manually bind CPU ahead of time to make sure in-core timers are + * available in SPL. + */ + ret = uclass_get_device(UCLASS_CPU, 0, &dev); + if (ret) + panic("failed to bind CPU: %d\n", ret); + + spl_dram_init(); + + icache_enable(); + dcache_enable(); + + th1520_invalidate_pmp(); +} diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig index d13c97463a8..b19dc009fde 100644 --- a/configs/th1520_lpi4a_defconfig +++ b/configs/th1520_lpi4a_defconfig @@ -90,3 +90,21 @@ CONFIG_ZLIB_UNCOMPRESS=y CONFIG_BZIP2=y CONFIG_ZSTD=y CONFIG_LIB_RATIONAL=y +CONFIG_SPL=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_LOAD_FIT_ADDRESS=0xffe0040000 +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_STACK=0xffe0170000 +CONFIG_SPL_BSS_START_ADDR=0xffe0160000 +CONFIG_SPL_BSS_MAX_SIZE=0x10000 +CONFIG_SPL_MAX_SIZE=0x40000 +CONFIG_SPL_RAM_DEVICE=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_SPL_THEAD_TH1520_DDR=y +CONFIG_SPL_GPIO=y +CONFIG_SPL_MMC_y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x10000000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x400000 From e1bd3b444549dfcd61fa8ea96cbfedf646dfca19 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:05:03 +0000 Subject: [PATCH 19/23] doc: thead: lpi4a: Update documentation Support for eMMC, SD card, GPIO and SPL have been available in LPi4A port. Update the documentation of support status and build instructions. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- doc/board/thead/lpi4a.rst | 58 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 55 insertions(+), 3 deletions(-) diff --git a/doc/board/thead/lpi4a.rst b/doc/board/thead/lpi4a.rst index e395c6ae12c..7e4c4ea81ee 100644 --- a/doc/board/thead/lpi4a.rst +++ b/doc/board/thead/lpi4a.rst @@ -32,6 +32,8 @@ Mainline support The support for following drivers are already enabled: 1. ns16550 UART Driver. +2. eMMC and SD card + Building ~~~~~~~~ @@ -43,15 +45,32 @@ Building export CROSS_COMPILE= -The U-Boot is capable of running in M-Mode, so we can directly build it. +3. Build DDR firmware + +DDR driver requires a firmware to function, to build it: + +.. code-block:: bash + + git clone --depth 1 https://github.com/ziyao233/th1520-firmware + cd th1520-firmware + lua5.4 ddr-generate.lua src/.lua th1520-ddr-firmware.bin + +4. Build U-Boot images + +The U-Boot is capable of running in M-Mode, so we can directly build it without +OpenSBI. The DDR firmware should be copied to U-Boot source directory before +building. .. code-block:: console cd + cp th1520-ddr-firmware.bin make th1520_lpi4a_defconfig make -This will generate u-boot-dtb.bin +This will generate u-boot-dtb.bin and u-boot-with-spl.bin. The former contains +only proper U-Boot and is for chainloading; the later contains also SPL and +DDR firmware and is ready for booting by BROM directly. Booting ~~~~~~~ @@ -61,7 +80,7 @@ and chain load the mainline u-boot image either via tftp or emmc storage, then bootup from it. Sample boot log from Lichee PI 4A board via tftp -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ .. code-block:: none @@ -127,3 +146,36 @@ Sample boot log from Lichee PI 4A board via tftp Err: serial@ffe7014000 Model: Sipeed Lichee Pi 4A LPI4A=> + +SPL support is still in an early stage and not all of the functionalities are +available when booting from mainline SPL. When using mainline SPL, +u-boot-with-spl.bin should be loaded to SRAM through fastboot. + +Sample boot log from Lichee PI 4A board via fastboot and mainline SPL +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. code-block:: none + + brom_ver 8 + [APP][E] protocol_connect failed, exit. + Starting download of 636588 bytes + + downloading of 636588 bytes finished + + U-Boot SPL 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000) + Trying to boot from RAM + + + U-Boot 2025.04-rc2-00049-geaa9fc99d4cd-dirty (Apr 26 2025 - 13:31:41 +0000) + + CPU: thead,c910 + Model: Sipeed Lichee Pi 4A + DRAM: 8 GiB + Core: 30 devices, 9 uclasses, devicetree: separate + MMC: mmc@ffe7080000: 0, mmc@ffe7090000: 1 + Loading Environment from ... OK + In: serial@ffe7014000 + Out: serial@ffe7014000 + Err: serial@ffe7014000 + Model: Sipeed Lichee Pi 4A + LPI4A=> From ce8f49ece23f410aec72be27d1f7e03696132b0a Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Fri, 16 May 2025 03:05:22 +0000 Subject: [PATCH 20/23] riscv: cpu: th1520: Initialize IOPMPs in SPL TH1520 SoC ships several IOPMPs protecting various on-chip peripherals. They must be configured before accessing the peripherals. Let's initialize them in SPL harts_early_init(). Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/th1520/spl.c | 65 ++++++++++++++++++++++ arch/riscv/include/asm/arch-th1520/iopmp.h | 42 ++++++++++++++ 2 files changed, 107 insertions(+) create mode 100644 arch/riscv/include/asm/arch-th1520/iopmp.h diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c index aec398528d1..362fe895f86 100644 --- a/arch/riscv/cpu/th1520/spl.c +++ b/arch/riscv/cpu/th1520/spl.c @@ -2,6 +2,8 @@ /* * Copyright (C) 2025 Yao Zi */ +#include +#include #include #include #include @@ -9,6 +11,16 @@ DECLARE_GLOBAL_DATA_PTR; +#define TH1520_SUBSYS_CLK (void __iomem *)(0xffff011000 + 0x220) +#define TH1520_SUBSYS_CLK_VO_EN BIT(2) +#define TH1520_SUBSYS_CLK_VI_EN BIT(1) +#define TH1520_SUBSYS_CLK_DSP_EN BIT(0) +#define TH1520_SUBSYS_RST (void __iomem *)(0xffff015000 + 0x220) +#define TH1520_SUBSYS_RST_VP_N BIT(3) +#define TH1520_SUBSYS_RST_VO_N BIT(2) +#define TH1520_SUBSYS_RST_VI_N BIT(1) +#define TH1520_SUBSYS_RST_DSP_N BIT(0) + int spl_dram_init(void) { int ret; @@ -29,3 +41,56 @@ int spl_dram_init(void) return 0; } + +static void __iomem *th1520_iopmp_regs[] = { + TH1520_IOPMP_EMMC, + TH1520_IOPMP_SDIO0, + TH1520_IOPMP_SDIO1, + TH1520_IOPMP_USB0, + TH1520_IOPMP_AO, + TH1520_IOPMP_AUD, + TH1520_IOPMP_CHIP_DBG, + TH1520_IOPMP_EIP120I, + TH1520_IOPMP_EIP120II, + TH1520_IOPMP_EIP120III, + TH1520_IOPMP_ISP0, + TH1520_IOPMP_ISP1, + TH1520_IOPMP_DW200, + TH1520_IOPMP_VIPRE, + TH1520_IOPMP_VENC, + TH1520_IOPMP_VDEC, + TH1520_IOPMP_G2D, + TH1520_IOPMP_FCE, + TH1520_IOPMP_NPU, + TH1520_IOPMP_DPU0, + TH1520_IOPMP_DPU1, + TH1520_IOPMP_GPU, + TH1520_IOPMP_GMAC1, + TH1520_IOPMP_GMAC2, + TH1520_IOPMP_DMAC, + TH1520_IOPMP_TEE_DMAC, + TH1520_IOPMP_DSP0, + TH1520_IOPMP_DSP1, +}; + +void harts_early_init(void) +{ + int i; + + /* + * Set IOPMPs to the default attribute, allowing the application + * processor to access various peripherals. Subsystem clocks should be + * enabled and resets should be deasserted ahead of time, or the HART + * will hang when configuring corresponding IOPMP entries. + */ + setbits_le32(TH1520_SUBSYS_CLK, TH1520_SUBSYS_CLK_VO_EN | + TH1520_SUBSYS_CLK_VI_EN | + TH1520_SUBSYS_CLK_DSP_EN); + setbits_le32(TH1520_SUBSYS_RST, TH1520_SUBSYS_RST_VP_N | + TH1520_SUBSYS_RST_VO_N | + TH1520_SUBSYS_RST_VI_N | + TH1520_SUBSYS_RST_DSP_N); + + for (i = 0; i < ARRAY_SIZE(th1520_iopmp_regs); i++) + writel(TH1520_IOPMP_DEFAULT_ATTR, th1520_iopmp_regs[i]); +} diff --git a/arch/riscv/include/asm/arch-th1520/iopmp.h b/arch/riscv/include/asm/arch-th1520/iopmp.h new file mode 100644 index 00000000000..3dc766b5bff --- /dev/null +++ b/arch/riscv/include/asm/arch-th1520/iopmp.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Yao Zi + */ +#ifndef _ASM_ARCH_TH1520_IOPMP_H_ +#define _ASM_ARCH_TH1520_IOPMP_H_ + +#define TH1520_IOPMP_EMMC (void *)0xfffc0280c0 +#define TH1520_IOPMP_SDIO0 (void *)0xfffc0290c0 +#define TH1520_IOPMP_SDIO1 (void *)0xfffc02a0c0 +#define TH1520_IOPMP_USB0 (void *)0xfffc02e0c0 +#define TH1520_IOPMP_AO (void *)0xffffc210c0 +#define TH1520_IOPMP_AUD (void *)0xffffc220c0 +#define TH1520_IOPMP_CHIP_DBG (void *)0xffffc370c0 +#define TH1520_IOPMP_EIP120I (void *)0xffff2200c0 +#define TH1520_IOPMP_EIP120II (void *)0xffff2300c0 +#define TH1520_IOPMP_EIP120III (void *)0xffff2400c0 +#define TH1520_IOPMP_ISP0 (void *)0xfff40800c0 +#define TH1520_IOPMP_ISP1 (void *)0xfff40810c0 +#define TH1520_IOPMP_DW200 (void *)0xfff40820c0 +#define TH1520_IOPMP_VIPRE (void *)0xfff40830c0 +#define TH1520_IOPMP_VENC (void *)0xfffcc600c0 +#define TH1520_IOPMP_VDEC (void *)0xfffcc610c0 +#define TH1520_IOPMP_G2D (void *)0xfffcc620c0 +#define TH1520_IOPMP_FCE (void *)0xfffcc630c0 +#define TH1520_IOPMP_NPU (void *)0xffff01c0c0 +#define TH1520_IOPMP_DPU0 (void *)0xffff5200c0 +#define TH1520_IOPMP_DPU1 (void *)0xffff5210c0 +#define TH1520_IOPMP_GPU (void *)0xffff5220c0 +#define TH1520_IOPMP_GMAC1 (void *)0xfffc0010c0 +#define TH1520_IOPMP_GMAC2 (void *)0xfffc0020c0 +#define TH1520_IOPMP_DMAC (void *)0xffffc200c0 +#define TH1520_IOPMP_TEE_DMAC (void *)0xffff2500c0 +#define TH1520_IOPMP_DSP0 (void *)0xffff0580c0 +#define TH1520_IOPMP_DSP1 (void *)0xffff0590c0 +#define TH1520_IOPMP_AUDIO (void *)0xffffc220c0 +#define TH1520_IOPMP_AUDIO0 (void *)0xffcb02e0c0 +#define TH1520_IOPMP_AUDIO1 (void *)0xffcb02f0c0 + +#define TH1520_IOPMP_DEFAULT_ATTR 0xffffffff + +#endif // _ASM_ARCH_TH1520_IOPMP_H_ From e6bfa6fc94f655545f4c79b9a9939cfeb97a3a89 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Fri, 16 May 2025 03:05:23 +0000 Subject: [PATCH 21/23] clk: thead: Port clock controller driver of TH1520 SoC The driver is adapted from Linux kernel's version of clk-th1520-ap.c, with only output clocks for external sensors, which are barely useful in bootloaders, removed. Same as the mainline driver, it currently lacks of ability to enable and reconfigure PLLs, which could be implemented later. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/thead/Kconfig | 19 + drivers/clk/thead/Makefile | 5 + drivers/clk/thead/clk-th1520-ap.c | 1031 +++++++++++++++++++++++++++++ 5 files changed, 1057 insertions(+) create mode 100644 drivers/clk/thead/Kconfig create mode 100644 drivers/clk/thead/Makefile create mode 100644 drivers/clk/thead/clk-th1520-ap.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 18bd640a68b..19aa2ffa539 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -271,6 +271,7 @@ source "drivers/clk/starfive/Kconfig" source "drivers/clk/stm32/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/ti/Kconfig" +source "drivers/clk/thead/Kconfig" source "drivers/clk/uniphier/Kconfig" endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 8411205ee04..5f0c0d8a5c2 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -20,6 +20,7 @@ obj-y += imx/ obj-$(CONFIG_CLK_JH7110) += starfive/ obj-y += tegra/ obj-y += ti/ +obj-$(CONFIG_CLK_THEAD) += thead/ obj-$(CONFIG_$(PHASE_)CLK_INTEL) += intel/ obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/clk/thead/Kconfig b/drivers/clk/thead/Kconfig new file mode 100644 index 00000000000..e815286b085 --- /dev/null +++ b/drivers/clk/thead/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (c) 2025, Yao Zi + +config CLK_THEAD + bool "Clock support for T-Head SoCs" + depends on CLK + +if CLK_THEAD + +config CLK_THEAD_TH1520_AP + bool "T-Head TH1520 AP clock support" + select CLK_CCF + default THEAD_TH1520 + help + This enables support clock driver for T-Head TH1520 Application + processor. + +endif diff --git a/drivers/clk/thead/Makefile b/drivers/clk/thead/Makefile new file mode 100644 index 00000000000..8cc05ed7914 --- /dev/null +++ b/drivers/clk/thead/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2025 Yao Zi + +obj-$(CONFIG_CLK_THEAD_TH1520_AP) += clk-th1520-ap.o diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c new file mode 100644 index 00000000000..b80ad05b8ad --- /dev/null +++ b/drivers/clk/thead/clk-th1520-ap.c @@ -0,0 +1,1031 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Vivo Communication Technology Co. Ltd. + * Copyright (C) 2025 Yao Zi + * Authors: Yangtao Li + */ + +#include +#include +#include +#include + +#include + +#define TH1520_PLL_POSTDIV2 GENMASK(26, 24) +#define TH1520_PLL_POSTDIV1 GENMASK(22, 20) +#define TH1520_PLL_FBDIV GENMASK(19, 8) +#define TH1520_PLL_REFDIV GENMASK(5, 0) +#define TH1520_PLL_BYPASS BIT(30) +#define TH1520_PLL_DSMPD BIT(24) +#define TH1520_PLL_FRAC GENMASK(23, 0) +#define TH1520_PLL_FRAC_BITS 24 + +static const char ccu_osc_name_to_be_filled[] = "TO BE FILLED"; + +struct ccu_internal { + u8 shift; + u8 width; +}; + +struct ccu_div_internal { + u8 shift; + u8 width; +}; + +struct ccu_common { + void __iomem *reg; + const char *name; + struct clk clk; + int clkid; + u16 cfg0; + u16 cfg1; +}; + +struct ccu_mux { + struct ccu_common common; + struct ccu_internal mux; + const char **parents; + size_t num_parents; +}; + +struct ccu_gate { + struct ccu_common common; + const char *parent; + u32 enable; +}; + +struct ccu_div { + struct ccu_div_internal div; + struct ccu_common common; + struct ccu_internal mux; + const char **parents; + size_t num_parents; + u32 enable; +}; + +struct ccu_pll { + struct ccu_common common; +}; + +#define TH_CCU_ARG(_shift, _width) \ + { \ + .shift = _shift, \ + .width = _width, \ + } + +#define TH_CCU_DIV_FLAGS(_shift, _width, _flags) \ + { \ + .shift = _shift, \ + .width = _width, \ + } + +#define CCU_GATE(_clkid, _struct, _name, _parent, _reg, _gate, _flags) \ + struct ccu_gate _struct = { \ + .parent = _parent, \ + .enable = _gate, \ + .common = { \ + .clkid = _clkid, \ + .cfg0 = _reg, \ + .name = _name, \ + } \ + } + +static inline struct ccu_common *clk_to_ccu_common(struct clk *clk) +{ + return container_of(clk, struct ccu_common, clk); +} + +static inline struct ccu_mux *clk_to_ccu_mux(struct clk *clk) +{ + struct ccu_common *common = clk_to_ccu_common(clk); + + return container_of(common, struct ccu_mux, common); +} + +static inline struct ccu_pll *clk_to_ccu_pll(struct clk *clk) +{ + struct ccu_common *common = clk_to_ccu_common(clk); + + return container_of(common, struct ccu_pll, common); +} + +static inline struct ccu_div *clk_to_ccu_div(struct clk *clk) +{ + struct ccu_common *common = clk_to_ccu_common(clk); + + return container_of(common, struct ccu_div, common); +} + +static inline struct ccu_gate *clk_to_ccu_gate(struct clk *clk) +{ + struct ccu_common *common = clk_to_ccu_common(clk); + + return container_of(common, struct ccu_gate, common); +} + +static int ccu_set_parent_helper(struct ccu_common *common, + struct ccu_internal *mux, + u8 index) +{ + clrsetbits_le32(common->reg + common->cfg0, + GENMASK(mux->width - 1, 0) << mux->shift, + index << mux->shift); + + return 0; +} + +static void ccu_disable_helper(struct ccu_common *common, u32 gate) +{ + if (!gate) + return; + + clrsetbits_le32(common->reg + common->cfg0, + gate, ~gate); +} + +static int ccu_enable_helper(struct ccu_common *common, u32 gate) +{ + u32 val; + + if (!gate) + return 0; + + clrsetbits_le32(common->reg + common->cfg0, gate, gate); + val = readl(common->reg + common->cfg0); + + return 0; +} + +static int ccu_get_parent_index_helper(const char * const *parents, + int num_parents, struct clk *parent) +{ + const char *parent_name = parent->dev->name; + unsigned int index; + + for (index = 0; index < num_parents; index++) { + if (!strcmp(parents[index], parent_name)) + return index; + } + + return -ENOENT; +} + +static unsigned long ccu_div_get_rate(struct clk *clk) +{ + struct ccu_div *cd = clk_to_ccu_div(clk); + unsigned long rate; + unsigned int val; + + val = readl(cd->common.reg + cd->common.cfg0); + val = val >> cd->div.shift; + val &= GENMASK(cd->div.width - 1, 0); + rate = divider_recalc_rate(clk, clk_get_parent_rate(clk), val, NULL, + 0, cd->div.width); + + return rate; +} + +static int ccu_div_get_parent(struct ccu_div *cd) +{ + u32 val = readl(cd->common.reg + cd->common.cfg0); + + return (val >> cd->mux.shift) & GENMASK(cd->mux.width - 1, 0); +} + +static int ccu_div_set_parent(struct clk *clk, struct clk *parent) +{ + struct ccu_div *cd = clk_to_ccu_div(clk); + u8 id; + + id = ccu_get_parent_index_helper(cd->parents, cd->num_parents, parent); + if (id < 0) + return id; + + return ccu_set_parent_helper(&cd->common, &cd->mux, id); +} + +static int ccu_div_disable(struct clk *clk) +{ + struct ccu_div *cd = clk_to_ccu_div(clk); + + ccu_disable_helper(&cd->common, cd->enable); + + return 0; +} + +static int ccu_div_enable(struct clk *clk) +{ + struct ccu_div *cd = clk_to_ccu_div(clk); + + return ccu_enable_helper(&cd->common, cd->enable); +} + +static const struct clk_ops ccu_div_ops = { + .disable = ccu_div_disable, + .enable = ccu_div_enable, + .set_parent = ccu_div_set_parent, + .get_rate = ccu_div_get_rate, +}; + +U_BOOT_DRIVER(th1520_clk_div) = { + .name = "th1520_clk_div", + .id = UCLASS_CLK, + .ops = &ccu_div_ops, +}; + +static unsigned long th1520_pll_vco_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct ccu_pll *pll = clk_to_ccu_pll(clk); + unsigned long div, mul, frac; + unsigned int cfg0, cfg1; + u64 rate = parent_rate; + + cfg0 = readl(pll->common.reg + pll->common.cfg0); + cfg1 = readl(pll->common.reg + pll->common.cfg1); + + mul = FIELD_GET(TH1520_PLL_FBDIV, cfg0); + div = FIELD_GET(TH1520_PLL_REFDIV, cfg0); + if (!(cfg1 & TH1520_PLL_DSMPD)) { + mul <<= TH1520_PLL_FRAC_BITS; + frac = FIELD_GET(TH1520_PLL_FRAC, cfg1); + mul += frac; + div <<= TH1520_PLL_FRAC_BITS; + } + + rate = parent_rate * mul; + rate = rate / div; + + return rate; +} + +static unsigned long th1520_pll_postdiv_recalc_rate(struct clk *clk, + unsigned long parent_rate) +{ + struct ccu_pll *pll = clk_to_ccu_pll(clk); + unsigned long div, rate = parent_rate; + unsigned int cfg0, cfg1; + + cfg0 = readl(pll->common.reg + pll->common.cfg0); + cfg1 = readl(pll->common.reg + pll->common.cfg1); + + if (cfg1 & TH1520_PLL_BYPASS) + return rate; + + div = FIELD_GET(TH1520_PLL_POSTDIV1, cfg0) * + FIELD_GET(TH1520_PLL_POSTDIV2, cfg0); + + rate = rate / div; + + return rate; +} + +static unsigned long ccu_pll_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_parent_rate(clk); + + rate = th1520_pll_vco_recalc_rate(clk, rate); + rate = th1520_pll_postdiv_recalc_rate(clk, rate); + + return rate; +} + +static const struct clk_ops clk_pll_ops = { + .get_rate = ccu_pll_get_rate, +}; + +U_BOOT_DRIVER(th1520_clk_pll) = { + .name = "th1520_clk_pll", + .id = UCLASS_CLK, + .ops = &clk_pll_ops, +}; + +static struct ccu_pll cpu_pll0_clk = { + .common = { + .clkid = CLK_CPU_PLL0, + .cfg0 = 0x000, + .cfg1 = 0x004, + .name = "cpu-pll0", + }, +}; + +static struct ccu_pll cpu_pll1_clk = { + .common = { + .clkid = CLK_CPU_PLL1, + .cfg0 = 0x010, + .cfg1 = 0x014, + .name = "cpu-pll1", + }, +}; + +static struct ccu_pll gmac_pll_clk = { + .common = { + .clkid = CLK_GMAC_PLL, + .cfg0 = 0x020, + .cfg1 = 0x024, + .name = "gmac-pll", + }, +}; + +static const char *gmac_pll_clk_parent[] = { + "gmac-pll", +}; + +static struct ccu_pll video_pll_clk = { + .common = { + .clkid = CLK_VIDEO_PLL, + .cfg0 = 0x030, + .cfg1 = 0x034, + .name = "video-pll", + }, +}; + +static const char *video_pll_clk_parent[] = { + "video-pll", +}; + +static struct ccu_pll dpu0_pll_clk = { + .common = { + .clkid = CLK_DPU0_PLL, + .cfg0 = 0x040, + .cfg1 = 0x044, + .name = "dpu0-pll", + }, +}; + +static const char *dpu0_pll_clk_parent[] = { + "dpu0-pll", +}; + +static struct ccu_pll dpu1_pll_clk = { + .common = { + .clkid = CLK_DPU1_PLL, + .cfg0 = 0x050, + .cfg1 = 0x054, + .name = "dpu1-pll", + }, +}; + +static const char *dpu1_pll_clk_parent[] = { + "dpu1-pll", +}; + +static struct ccu_pll tee_pll_clk = { + .common = { + .clkid = CLK_TEE_PLL, + .cfg0 = 0x060, + .cfg1 = 0x064, + .name = "tee-pll", + }, +}; + +static const char *c910_i0_parents[] = { + "cpu-pll0", ccu_osc_name_to_be_filled, +}; + +static struct ccu_mux c910_i0_clk = { + .parents = c910_i0_parents, + .num_parents = ARRAY_SIZE(c910_i0_parents), + .mux = TH_CCU_ARG(1, 1), + .common = { + .clkid = CLK_C910_I0, + .cfg0 = 0x100, + .name = "c910-i0", + } +}; + +static const char *c910_parents[] = { + "c910-i0", "cpu-pll1", +}; + +static struct ccu_mux c910_clk = { + .parents = c910_parents, + .num_parents = ARRAY_SIZE(c910_parents), + .mux = TH_CCU_ARG(0, 1), + .common = { + .clkid = CLK_C910, + .cfg0 = 0x100, + .name = "c910", + } +}; + +static const char *ahb2_cpusys_parents[] = { + "gmac-pll", ccu_osc_name_to_be_filled, +}; + +static struct ccu_div ahb2_cpusys_hclk = { + .parents = ahb2_cpusys_parents, + .num_parents = ARRAY_SIZE(ahb2_cpusys_parents), + .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux = TH_CCU_ARG(5, 1), + .common = { + .clkid = CLK_AHB2_CPUSYS_HCLK, + .cfg0 = 0x120, + .name = "ahb2-cpusys-hclk", + }, +}; + +static const char *ahb2_cpusys_hclk_parents[] = { + "ahb2-cpusys-hclk", +}; + +static struct ccu_div apb3_cpusys_pclk = { + .parents = ahb2_cpusys_hclk_parents, + .num_parents = ARRAY_SIZE(ahb2_cpusys_hclk_parents), + .div = TH_CCU_ARG(0, 3), + .common = { + .clkid = CLK_APB3_CPUSYS_PCLK, + .cfg0 = 0x130, + .name = "apb3-cpusys-pclk", + }, +}; + +static struct ccu_div axi4_cpusys2_aclk = { + .parents = gmac_pll_clk_parent, + .num_parents = ARRAY_SIZE(gmac_pll_clk_parent), + .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_AXI4_CPUSYS2_ACLK, + .cfg0 = 0x134, + .name = "axi4-cpusys2-aclk", + }, +}; + +static const char *axi_parents[] = { + "video-pll", ccu_osc_name_to_be_filled, +}; + +static struct ccu_div axi_aclk = { + .parents = axi_parents, + .num_parents = ARRAY_SIZE(axi_parents), + .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux = TH_CCU_ARG(5, 1), + .common = { + .clkid = CLK_AXI_ACLK, + .cfg0 = 0x138, + .name = "axi-aclk", + }, +}; + +static const char *perisys_ahb_hclk_parents[] = { + "gmac-pll", ccu_osc_name_to_be_filled, +}; + +static struct ccu_div perisys_ahb_hclk = { + .parents = perisys_ahb_hclk_parents, + .num_parents = ARRAY_SIZE(perisys_ahb_hclk_parents), + .enable = BIT(6), + .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux = TH_CCU_ARG(5, 1), + .common = { + .clkid = CLK_PERI_AHB_HCLK, + .cfg0 = 0x140, + .name = "perisys-ahb-hclk", + }, +}; + +static const char *perisys_ahb_hclk_parent[] = { + "perisys-ahb-hclk", +}; + +static struct ccu_div perisys_apb_pclk = { + .parents = perisys_ahb_hclk_parent, + .num_parents = ARRAY_SIZE(perisys_ahb_hclk_parent), + .div = TH_CCU_ARG(0, 3), + .common = { + .clkid = CLK_PERI_APB_PCLK, + .cfg0 = 0x150, + .name = "perisys-apb-pclk", + }, +}; + +static struct ccu_div peri2sys_apb_pclk = { + .parents = gmac_pll_clk_parent, + .num_parents = ARRAY_SIZE(gmac_pll_clk_parent), + .div = TH_CCU_DIV_FLAGS(4, 3, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_PERI2APB_PCLK, + .cfg0 = 0x150, + .name = "peri2sys-apb-pclk", + }, +}; + +static const char *apb_parents[] = { + "gmac-pll", ccu_osc_name_to_be_filled, +}; + +static struct ccu_div apb_pclk = { + .parents = apb_parents, + .num_parents = ARRAY_SIZE(apb_parents), + .enable = BIT(5), + .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .mux = TH_CCU_ARG(7, 1), + .common = { + .clkid = CLK_APB_PCLK, + .cfg0 = 0x1c4, + .name = "apb-pclk", + }, +}; + +static const char *npu_parents[] = { + "gmac-pll", "video-pll", +}; + +static struct ccu_div npu_clk = { + .parents = npu_parents, + .num_parents = ARRAY_SIZE(npu_parents), + .enable = BIT(4), + .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .mux = TH_CCU_ARG(6, 1), + .common = { + .clkid = CLK_NPU, + .cfg0 = 0x1c8, + .name = "npu", + }, +}; + +static struct ccu_div vi_clk = { + .parents = video_pll_clk_parent, + .num_parents = ARRAY_SIZE(video_pll_clk_parent), + .div = TH_CCU_DIV_FLAGS(16, 4, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_VI, + .cfg0 = 0x1d0, + .name = "vi", + }, +}; + +static struct ccu_div vi_ahb_clk = { + .parents = video_pll_clk_parent, + .num_parents = ARRAY_SIZE(video_pll_clk_parent), + .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_VI_AHB, + .cfg0 = 0x1d0, + .name = "vi-ahb", + }, +}; + +static struct ccu_div vo_axi_clk = { + .parents = video_pll_clk_parent, + .num_parents = ARRAY_SIZE(video_pll_clk_parent), + .enable = BIT(5), + .div = TH_CCU_DIV_FLAGS(0, 4, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_VO_AXI, + .cfg0 = 0x1dc, + .name = "vo-axi", + }, +}; + +static struct ccu_div vp_apb_clk = { + .parents = gmac_pll_clk_parent, + .num_parents = ARRAY_SIZE(gmac_pll_clk_parent), + .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_VP_APB, + .cfg0 = 0x1e0, + .name = "vp-apb", + }, +}; + +static struct ccu_div vp_axi_clk = { + .parents = video_pll_clk_parent, + .num_parents = ARRAY_SIZE(video_pll_clk_parent), + .enable = BIT(15), + .div = TH_CCU_DIV_FLAGS(8, 4, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_VP_AXI, + .cfg0 = 0x1e0, + .name = "vp-axi", + }, +}; + +static struct ccu_div venc_clk = { + .parents = gmac_pll_clk_parent, + .num_parents = ARRAY_SIZE(gmac_pll_clk_parent), + .enable = BIT(5), + .div = TH_CCU_DIV_FLAGS(0, 3, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_VENC, + .cfg0 = 0x1e4, + .name = "venc", + }, +}; + +static struct ccu_div dpu0_clk = { + .parents = dpu0_pll_clk_parent, + .num_parents = ARRAY_SIZE(dpu0_pll_clk_parent), + .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_DPU0, + .cfg0 = 0x1e8, + .name = "dpu0", + }, +}; + +static struct ccu_div dpu1_clk = { + .parents = dpu1_pll_clk_parent, + .num_parents = ARRAY_SIZE(dpu1_pll_clk_parent), + .div = TH_CCU_DIV_FLAGS(0, 8, CLK_DIVIDER_ONE_BASED), + .common = { + .clkid = CLK_DPU1, + .cfg0 = 0x1ec, + .name = "dpu1", + }, +}; + +static CCU_GATE(CLK_BROM, brom_clk, "brom", "ahb2-cpusys-hclk", 0x100, BIT(4), 0); +static CCU_GATE(CLK_BMU, bmu_clk, "bmu", "axi4-cpusys2-aclk", 0x100, BIT(5), 0); +static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x", "axi4-cpusys2-aclk", + 0x134, BIT(8), 0); +static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys", "axi4-cpusys2-aclk", + 0x134, BIT(7), 0); +static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h", "axi-aclk", 0x138, BIT(8), 0); +static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h", "axi4-cpusys2-aclk", + 0x140, BIT(9), CLK_IGNORE_UNUSED); +static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-apb1-hclk", "perisys-ahb-hclk", + 0x150, BIT(9), 0); +static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-apb2-hclk", "perisys-ahb-hclk", + 0x150, BIT(10), CLK_IGNORE_UNUSED); +static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-apb3-hclk", "perisys-ahb-hclk", + 0x150, BIT(11), CLK_IGNORE_UNUSED); +static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-apb4-hclk", "perisys-ahb-hclk", + 0x150, BIT(12), 0); +static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", "axi-aclk", 0x1c8, BIT(5), 0); +static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", "axi-aclk", 0x1e0, BIT(13), 0); +static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio", "emmc-sdio-ref", 0x204, BIT(30), 0); +static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", "gmac-pll", 0x204, BIT(26), 0); +static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1", "perisys-apb-pclk", 0x204, BIT(24), 0); +static CCU_GATE(CLK_DSMART, dsmart_clk, "dsmart", "perisys-apb-pclk", 0x204, BIT(23), 0); +static CCU_GATE(CLK_PADCTRL0, padctrl0_clk, "padctrl0", "perisys-apb-pclk", 0x204, BIT(22), 0); +static CCU_GATE(CLK_GMAC_AXI, gmac_axi_clk, "gmac-axi", "axi4-cpusys2-aclk", 0x204, BIT(21), 0); +static CCU_GATE(CLK_GPIO3, gpio3_clk, "gpio3-clk", "peri2sys-apb-pclk", 0x204, BIT(20), 0); +static CCU_GATE(CLK_GMAC0, gmac0_clk, "gmac0", "gmac-pll", 0x204, BIT(19), 0); +static CCU_GATE(CLK_PWM, pwm_clk, "pwm", "perisys-apb-pclk", 0x204, BIT(18), 0); +static CCU_GATE(CLK_QSPI0, qspi0_clk, "qspi0", "video-pll", 0x204, BIT(17), 0); +static CCU_GATE(CLK_QSPI1, qspi1_clk, "qspi1", "video-pll", 0x204, BIT(16), 0); +static CCU_GATE(CLK_SPI, spi_clk, "spi", "video-pll", 0x204, BIT(15), 0); +static CCU_GATE(CLK_UART0_PCLK, uart0_pclk, "uart0-pclk", "perisys-apb-pclk", 0x204, BIT(14), 0); +static CCU_GATE(CLK_UART1_PCLK, uart1_pclk, "uart1-pclk", "perisys-apb-pclk", 0x204, BIT(13), 0); +static CCU_GATE(CLK_UART2_PCLK, uart2_pclk, "uart2-pclk", "perisys-apb-pclk", 0x204, BIT(12), 0); +static CCU_GATE(CLK_UART3_PCLK, uart3_pclk, "uart3-pclk", "perisys-apb-pclk", 0x204, BIT(11), 0); +static CCU_GATE(CLK_UART4_PCLK, uart4_pclk, "uart4-pclk", "perisys-apb-pclk", 0x204, BIT(10), 0); +static CCU_GATE(CLK_UART5_PCLK, uart5_pclk, "uart5-pclk", "perisys-apb-pclk", 0x204, BIT(9), 0); +static CCU_GATE(CLK_GPIO0, gpio0_clk, "gpio0-clk", "perisys-apb-pclk", 0x204, BIT(8), 0); +static CCU_GATE(CLK_GPIO1, gpio1_clk, "gpio1-clk", "perisys-apb-pclk", 0x204, BIT(7), 0); +static CCU_GATE(CLK_GPIO2, gpio2_clk, "gpio2-clk", "peri2sys-apb-pclk", 0x204, BIT(6), 0); +static CCU_GATE(CLK_I2C0, i2c0_clk, "i2c0", "perisys-apb-pclk", 0x204, BIT(5), 0); +static CCU_GATE(CLK_I2C1, i2c1_clk, "i2c1", "perisys-apb-pclk", 0x204, BIT(4), 0); +static CCU_GATE(CLK_I2C2, i2c2_clk, "i2c2", "perisys-apb-pclk", 0x204, BIT(3), 0); +static CCU_GATE(CLK_I2C3, i2c3_clk, "i2c3", "perisys-apb-pclk", 0x204, BIT(2), 0); +static CCU_GATE(CLK_I2C4, i2c4_clk, "i2c4", "perisys-apb-pclk", 0x204, BIT(1), 0); +static CCU_GATE(CLK_I2C5, i2c5_clk, "i2c5", "perisys-apb-pclk", 0x204, BIT(0), 0); +static CCU_GATE(CLK_SPINLOCK, spinlock_clk, "spinlock", "ahb2-cpusys-hclk", 0x208, BIT(10), 0); +static CCU_GATE(CLK_DMA, dma_clk, "dma", "axi4-cpusys2-aclk", 0x208, BIT(8), 0); +static CCU_GATE(CLK_MBOX0, mbox0_clk, "mbox0", "apb3-cpusys-pclk", 0x208, BIT(7), 0); +static CCU_GATE(CLK_MBOX1, mbox1_clk, "mbox1", "apb3-cpusys-pclk", 0x208, BIT(6), 0); +static CCU_GATE(CLK_MBOX2, mbox2_clk, "mbox2", "apb3-cpusys-pclk", 0x208, BIT(5), 0); +static CCU_GATE(CLK_MBOX3, mbox3_clk, "mbox3", "apb3-cpusys-pclk", 0x208, BIT(4), 0); +static CCU_GATE(CLK_WDT0, wdt0_clk, "wdt0", "apb3-cpusys-pclk", 0x208, BIT(3), 0); +static CCU_GATE(CLK_WDT1, wdt1_clk, "wdt1", "apb3-cpusys-pclk", 0x208, BIT(2), 0); +static CCU_GATE(CLK_TIMER0, timer0_clk, "timer0", "apb3-cpusys-pclk", 0x208, BIT(1), 0); +static CCU_GATE(CLK_TIMER1, timer1_clk, "timer1", "apb3-cpusys-pclk", 0x208, BIT(0), 0); +static CCU_GATE(CLK_SRAM0, sram0_clk, "sram0", "axi-aclk", 0x20c, BIT(4), 0); +static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", "axi-aclk", 0x20c, BIT(3), 0); +static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", "axi-aclk", 0x20c, BIT(2), 0); +static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", "axi-aclk", 0x20c, BIT(1), 0); + +static const char *uart_sclk_parents[] = { + "gmac-pll-clk-100m", ccu_osc_name_to_be_filled, +}; + +static struct ccu_mux uart_sclk = { + .parents = uart_sclk_parents, + .num_parents = ARRAY_SIZE(uart_sclk_parents), + .mux = TH_CCU_ARG(0, 1), + .common = { + .clkid = CLK_UART_SCLK, + .cfg0 = 0x210, + .name = "uart-sclk", + } +}; + +static struct ccu_common *th1520_pll_clks[] = { + &cpu_pll0_clk.common, + &cpu_pll1_clk.common, + &gmac_pll_clk.common, + &video_pll_clk.common, + &dpu0_pll_clk.common, + &dpu1_pll_clk.common, + &tee_pll_clk.common, +}; + +static struct ccu_common *th1520_div_clks[] = { + &ahb2_cpusys_hclk.common, + &apb3_cpusys_pclk.common, + &axi4_cpusys2_aclk.common, + &perisys_ahb_hclk.common, + &perisys_apb_pclk.common, + &axi_aclk.common, + &peri2sys_apb_pclk.common, + &apb_pclk.common, + &npu_clk.common, + &vi_clk.common, + &vi_ahb_clk.common, + &vo_axi_clk.common, + &vp_apb_clk.common, + &vp_axi_clk.common, + &venc_clk.common, + &dpu0_clk.common, + &dpu1_clk.common, +}; + +static struct ccu_common *th1520_mux_clks[] = { + &c910_i0_clk.common, + &c910_clk.common, + &uart_sclk.common, +}; + +static struct ccu_common *th1520_gate_clks[] = { + &emmc_sdio_clk.common, + &aon2cpu_a2x_clk.common, + &x2x_cpusys_clk.common, + &brom_clk.common, + &bmu_clk.common, + &cpu2aon_x2h_clk.common, + &cpu2peri_x2h_clk.common, + &cpu2vp_clk.common, + &perisys_apb1_hclk.common, + &perisys_apb2_hclk.common, + &perisys_apb3_hclk.common, + &perisys_apb4_hclk.common, + &npu_axi_clk.common, + &gmac1_clk.common, + &padctrl1_clk.common, + &dsmart_clk.common, + &padctrl0_clk.common, + &gmac_axi_clk.common, + &gpio3_clk.common, + &gmac0_clk.common, + &pwm_clk.common, + &qspi0_clk.common, + &qspi1_clk.common, + &spi_clk.common, + &uart0_pclk.common, + &uart1_pclk.common, + &uart2_pclk.common, + &uart3_pclk.common, + &uart4_pclk.common, + &uart5_pclk.common, + &gpio0_clk.common, + &gpio1_clk.common, + &gpio2_clk.common, + &i2c0_clk.common, + &i2c1_clk.common, + &i2c2_clk.common, + &i2c3_clk.common, + &i2c4_clk.common, + &i2c5_clk.common, + &spinlock_clk.common, + &dma_clk.common, + &mbox0_clk.common, + &mbox1_clk.common, + &mbox2_clk.common, + &mbox3_clk.common, + &wdt0_clk.common, + &wdt1_clk.common, + &timer0_clk.common, + &timer1_clk.common, + &sram0_clk.common, + &sram1_clk.common, + &sram2_clk.common, + &sram3_clk.common, +}; + +static void th1520_clk_fill_osc_name(const char **names, size_t name_num, + const char *osc_name) +{ + size_t i; + + for (i = 0; i < name_num; i++) { + if (names[i] == ccu_osc_name_to_be_filled) + names[i] = osc_name; + } +} + +static int th1520_clk_probe(struct udevice *dev) +{ + struct clk *clk, osc_clk; + const char *osc_name; + void __iomem *base; + fdt_addr_t addr; + int ret, i; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + base = (void __iomem *)addr; + + ret = clk_get_by_index(dev, 0, &osc_clk); + if (ret) { + pr_err("failed to get osc clock: %d\n", ret); + return ret; + } + + osc_name = clk_hw_get_name(&osc_clk); + + for (i = 0; i < ARRAY_SIZE(th1520_pll_clks); i++) { + struct ccu_common *common = th1520_pll_clks[i]; + + common->reg = base; + + ret = clk_register(&common->clk, "th1520_clk_pll", + common->name, osc_name); + if (ret) { + pr_err("failed to register PLL %s: %d\n", + common->name, ret); + return ret; + } + + common->clk.id = common->clkid; + } + + for (i = 0; i < ARRAY_SIZE(th1520_div_clks); i++) { + struct ccu_div *cd = container_of(th1520_div_clks[i], + struct ccu_div, common); + const char *current_parent; + + cd->common.reg = base; + th1520_clk_fill_osc_name(cd->parents, cd->num_parents, + osc_name); + + if (cd->num_parents > 1) + current_parent = cd->parents[ccu_div_get_parent(cd)]; + else + current_parent = cd->parents[0]; + + ret = clk_register(&cd->common.clk, "th1520_clk_div", + cd->common.name, + current_parent); + + if (ret) { + pr_err("failed to register div clock %s: %d\n", + cd->common.name, ret); + return ret; + } + + cd->common.clk.id = cd->common.clkid; + } + + clk = clk_register_fixed_factor(dev, "gmac-pll-clk-100m", "gmac-pll", + 0, 1, 10); + if (IS_ERR(clk)) { + pr_err("failed to register gmac-pll-clk-100m: %d\n", + (int)PTR_ERR(clk)); + return PTR_ERR(clk); + } + clk->id = CLK_PLL_GMAC_100M; + + clk = clk_register_fixed_factor(dev, "emmc-sdio-ref", "video-pll", + 0, 1, 4); + if (IS_ERR(clk)) { + pr_err("failed to register emmc-sdio-ref: %d\n", + (int)PTR_ERR(clk)); + return PTR_ERR(clk); + } + + for (i = 0; i < ARRAY_SIZE(th1520_mux_clks); i++) { + struct ccu_mux *cm = container_of(th1520_mux_clks[i], + struct ccu_mux, common); + + th1520_clk_fill_osc_name(cm->parents, cm->num_parents, + osc_name); + + clk = clk_register_mux(dev, cm->common.name, + cm->parents, cm->num_parents, + 0, + base + cm->common.cfg0, + cm->mux.shift, cm->mux.width, + 0); + if (IS_ERR(clk)) { + pr_err("failed to register mux clock %s: %d\n", + cm->common.name, (int)PTR_ERR(clk)); + return PTR_ERR(clk); + } + + clk->id = cm->common.clkid; + } + + for (i = 0; i < ARRAY_SIZE(th1520_gate_clks); i++) { + struct ccu_gate *cg = container_of(th1520_gate_clks[i], + struct ccu_gate, common); + + th1520_clk_fill_osc_name(&cg->parent, 1, osc_name); + + clk = clk_register_gate(dev, cg->common.name, + cg->parent, + 0, + base + cg->common.cfg0, + ffs(cg->enable) - 1, 0, NULL); + if (IS_ERR(clk)) { + pr_err("failed to register gate clock %s: %d\n", + cg->common.name, (int)PTR_ERR(clk)); + return PTR_ERR(clk); + } + + clk->id = cg->common.clkid; + } + + return 0; +} + +static const struct udevice_id th1520_clk_match[] = { + { + .compatible = "thead,th1520-clk-ap", + }, + { /* sentinel */ }, +}; + +static int th1520_clk_enable(struct clk *clk) +{ + struct clk *c; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_enable(c); +} + +static int th1520_clk_disable(struct clk *clk) +{ + struct clk *c; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_disable(c); +} + +static ulong th1520_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_get_rate(c); +} + +static ulong th1520_clk_set_rate(struct clk *clk, ulong rate) +{ + struct clk *c; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + return clk_set_rate(c, rate); +} + +static int th1520_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *p; + int ret; + + ret = clk_get_by_id(clk->id, &c); + if (ret) + return ret; + + ret = clk_get_by_id(parent->id, &p); + if (ret) + return ret; + + return clk_set_parent(c, p); +} + +static const struct clk_ops th1520_clk_ops = { + .enable = th1520_clk_enable, + .disable = th1520_clk_disable, + .get_rate = th1520_clk_get_rate, + .set_rate = th1520_clk_set_rate, + .set_parent = th1520_clk_set_parent, +}; + +U_BOOT_DRIVER(th1520_clk) = { + .name = "th1520-clk", + .id = UCLASS_CLK, + .of_match = th1520_clk_match, + .probe = th1520_clk_probe, + .ops = &th1520_clk_ops, +}; From 1d759cc0ad25b7186abb5e2f0e7f77741a8ea861 Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Fri, 16 May 2025 03:05:24 +0000 Subject: [PATCH 22/23] riscv: cpu: th1520: Select clock driver The clock driver is essential for TH1520 SoCs to operate. Select the driver in SoC Kconfig entry. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/th1520/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig index a916d364e6c..4d44191bd22 100644 --- a/arch/riscv/cpu/th1520/Kconfig +++ b/arch/riscv/cpu/th1520/Kconfig @@ -10,6 +10,7 @@ config THEAD_TH1520 select SUPPORT_SPL select BINMAN if SPL select SYS_CACHE_THEAD_CMO + select CLK_THEAD imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) From ff6e20c32ff33c6963f7d0a79a0914681461f4fa Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Fri, 16 May 2025 03:05:25 +0000 Subject: [PATCH 23/23] riscv: dts: th1520: Complete clock tree Describe the newly-supported clock controller of TH1520 in SoC devicetree, replace dummy clocks with the controller-supplied ones and add correct clocks for GPIO controllers. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/th1520-lichee-module-4a.dtsi | 8 --- arch/riscv/dts/th1520.dtsi | 75 +++++++++++---------- 2 files changed, 39 insertions(+), 44 deletions(-) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi index 20dbc4c7d24..9b255f8243c 100644 --- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -26,14 +26,6 @@ clock-frequency = <32768>; }; -&apb_clk { - clock-frequency = <62500000>; -}; - -&uart_sclk { - clock-frequency = <100000000>; -}; - &emmc { bus-width = <8>; max-frequency = <198000000>; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index 4a523f8048b..28107a9f354 100644 --- a/arch/riscv/dts/th1520.dtsi +++ b/arch/riscv/dts/th1520.dtsi @@ -4,6 +4,7 @@ * Copyright (C) 2023 Jisheng Zhang */ +#include #include / { @@ -127,25 +128,6 @@ #clock-cells = <0>; }; - apb_clk: apb-clk-clock { - compatible = "fixed-clock"; - clock-output-names = "apb_clk"; - #clock-cells = <0>; - }; - - uart_sclk: uart-sclk-clock { - compatible = "fixed-clock"; - clock-output-names = "uart_sclk"; - #clock-cells = <0>; - }; - - sdhci_clk: sdhci-clock { - compatible = "fixed-clock"; - clock-frequency = <198000000>; - clock-output-names = "sdhci_clk"; - #clock-cells = <0>; - }; - soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -180,7 +162,8 @@ reg = <0xff 0xe7014000 0x0 0x100>; bootph-pre-ram; interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -190,7 +173,7 @@ compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7080000 0x0 0x10000>; interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; + clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; @@ -199,7 +182,7 @@ compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe7090000 0x0 0x10000>; interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; + clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; @@ -208,7 +191,7 @@ compatible = "thead,th1520-dwcmshc"; reg = <0xff 0xe70a0000 0x0 0x10000>; interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&sdhci_clk>; + clocks = <&clk CLK_EMMC_SDIO>; clock-names = "core"; status = "disabled"; }; @@ -217,7 +200,8 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7f00000 0x0 0x100>; interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -227,7 +211,8 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7f04000 0x0 0x100>; interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -236,6 +221,8 @@ gpio2: gpio@ffe7f34000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f34000 0x0 0x1000>; + clocks = <&clk CLK_GPIO2>; + clock-names = "bus"; #address-cells = <1>; #size-cells = <0>; @@ -254,6 +241,8 @@ gpio3: gpio@ffe7f38000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xe7f38000 0x0 0x1000>; + clocks = <&clk CLK_GPIO3>; + clock-names = "bus"; #address-cells = <1>; #size-cells = <0>; @@ -272,6 +261,8 @@ gpio0: gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; + clocks = <&clk CLK_GPIO0>; + clock-names = "bus"; #address-cells = <1>; #size-cells = <0>; @@ -290,6 +281,8 @@ gpio1: gpio@ffec006000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec006000 0x0 0x1000>; + clocks = <&clk CLK_GPIO1>; + clock-names = "bus"; #address-cells = <1>; #size-cells = <0>; @@ -309,16 +302,24 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; }; + clk: clock-controller@ffef010000 { + compatible = "thead,th1520-clk-ap"; + reg = <0xff 0xef010000 0x0 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + timer0: timer@ffefc32000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32000 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -327,7 +328,7 @@ timer1: timer@ffefc32014 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32014 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -336,7 +337,7 @@ timer2: timer@ffefc32028 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32028 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -345,7 +346,7 @@ timer3: timer@ffefc3203c { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc3203c 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -355,7 +356,8 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xf7f08000 0x0 0x4000>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -365,7 +367,8 @@ compatible = "snps,dw-apb-uart"; reg = <0xff 0xf7f0c000 0x0 0x4000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&uart_sclk>; + clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; + clock-names = "buadclk", "apb_pclk"; reg-shift = <2>; reg-io-width = <4>; status = "disabled"; @@ -384,7 +387,7 @@ timer4: timer@ffffc33000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33000 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -393,7 +396,7 @@ timer5: timer@ffffc33014 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33014 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -402,7 +405,7 @@ timer6: timer@ffffc33028 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc33028 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -411,7 +414,7 @@ timer7: timer@ffffc3303c { compatible = "snps,dw-apb-timer"; reg = <0xff 0xffc3303c 0x0 0x14>; - clocks = <&apb_clk>; + clocks = <&clk CLK_PERI_APB_PCLK>; clock-names = "timer"; interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; status = "disabled";