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clk/qcom: apq8096: fix the sdhci clock

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Select the right clock for sdhci.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250407175617.3494506-3-jorge.ramirez@oss.qualcomm.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
This commit is contained in:
Jorge Ramirez-Ortiz
2025-04-07 19:56:15 +02:00
committed by Caleb Connolly
parent 1561b01a08
commit 8fc48d1a01
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/qcom/clock-apq8096.c
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@@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)
struct msm_clk_priv *priv = dev_get_priv(clk->dev); struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) { switch (clk->id) {
case GCC_SDCC1_APPS_CLK: /* SDC1 */ case GCC_SDCC2_APPS_CLK: /* SDC2 */
return clk_init_sdc(priv, rate); return clk_init_sdc(priv, rate);
break; break;
case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/