arm: dts: k3-*-ddr: Add ss_cfg reg entry
Add ss_cfg memory region which maps the DDRSS configuration region for the memory controller node. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Tested-by: Neha Malcom Francis <n-francis@ti.com>
This commit is contained in:

committed by
Tom Rini

parent
9c6c7e30aa
commit
8ff96fb6d0
@@ -4,11 +4,12 @@
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*/
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*/
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/ {
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/ {
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memorycontroller: memory-controller@f308000 {
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memorycontroller: memory-controller@f300000 {
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compatible = "ti,am62a-ddrss";
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compatible = "ti,am62a-ddrss";
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reg = <0x00 0x0f308000 0x00 0x4000>,
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reg = <0x00 0x0f308000 0x00 0x4000>,
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<0x00 0x43014000 0x00 0x100>;
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<0x00 0x43014000 0x00 0x100>,
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reg-names = "cfg", "ctrl_mmr_lp4";
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<0x00 0x0f300000 0x00 0x200>;
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reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
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ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
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ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
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ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
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ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
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ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
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ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
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@@ -5,6 +5,8 @@
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&main_navss {
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&main_navss {
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ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
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ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr
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<0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
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<0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
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<0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
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<0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg
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<0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
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<0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
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<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
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<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
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@@ -24,8 +26,9 @@
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memorycontroller0: memorycontroller@2990000 {
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memorycontroller0: memorycontroller@2990000 {
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compatible = "ti,j721s2-ddrss";
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compatible = "ti,j721s2-ddrss";
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reg = <0x0 0x02990000 0x0 0x4000>,
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reg = <0x0 0x02990000 0x0 0x4000>,
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<0x0 0x0114000 0x0 0x100>;
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<0x0 0x0114000 0x0 0x100>,
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reg-names = "cfg", "ctrl_mmr_lp4";
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<0x0 0x02980000 0x0 0x200>;
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reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
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power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
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power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
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<&k3_pds 96 TI_SCI_PD_SHARED>;
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<&k3_pds 96 TI_SCI_PD_SHARED>;
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clocks = <&k3_clks 138 0>, <&k3_clks 43 2>;
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clocks = <&k3_clks 138 0>, <&k3_clks 43 2>;
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@@ -2232,8 +2235,9 @@
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memorycontroller1: memorycontroller@29b0000 {
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memorycontroller1: memorycontroller@29b0000 {
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compatible = "ti,j721s2-ddrss";
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compatible = "ti,j721s2-ddrss";
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reg = <0x0 0x029b0000 0x0 0x4000>,
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reg = <0x0 0x029b0000 0x0 0x4000>,
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<0x0 0x0114000 0x0 0x100>;
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<0x0 0x0114000 0x0 0x100>,
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reg-names = "cfg", "ctrl_mmr_lp4";
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<0x0 0x029a0000 0x0 0x200>;
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reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
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power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>,
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power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>,
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<&k3_pds 97 TI_SCI_PD_SHARED>;
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<&k3_pds 97 TI_SCI_PD_SHARED>;
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clocks = <&k3_clks 139 0>, <&k3_clks 43 2>;
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clocks = <&k3_clks 139 0>, <&k3_clks 43 2>;
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@@ -9,6 +9,10 @@
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<0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
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<0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg
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<0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
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<0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg
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<0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
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<0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg
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<0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0
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<0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1
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<0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2
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<0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3
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<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
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<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
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msmc0: msmc {
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msmc0: msmc {
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@@ -26,8 +30,9 @@
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memorycontroller0: memorycontroller@2990000 {
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memorycontroller0: memorycontroller@2990000 {
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compatible = "ti,j721s2-ddrss";
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compatible = "ti,j721s2-ddrss";
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reg = <0x0 0x02990000 0x0 0x4000>,
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reg = <0x0 0x02990000 0x0 0x4000>,
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<0x0 0x0114000 0x0 0x100>;
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<0x0 0x0114000 0x0 0x100>,
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reg-names = "cfg", "ctrl_mmr_lp4";
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<0x0 0x02980000 0x0 0x200>;
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reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
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power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
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power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>,
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<&k3_pds 131 TI_SCI_PD_SHARED>;
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<&k3_pds 131 TI_SCI_PD_SHARED>;
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clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
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clocks = <&k3_clks 191 1>, <&k3_clks 78 2>;
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@@ -2234,8 +2239,9 @@
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memorycontroller1: memorycontroller@29b0000 {
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memorycontroller1: memorycontroller@29b0000 {
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compatible = "ti,j721s2-ddrss";
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compatible = "ti,j721s2-ddrss";
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reg = <0x0 0x029b0000 0x0 0x4000>,
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reg = <0x0 0x029b0000 0x0 0x4000>,
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<0x0 0x0114000 0x0 0x100>;
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<0x0 0x0114000 0x0 0x100>,
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reg-names = "cfg", "ctrl_mmr_lp4";
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<0x0 0x029a0000 0x0 0x200>;
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reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
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power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
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power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>,
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<&k3_pds 132 TI_SCI_PD_SHARED>;
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<&k3_pds 132 TI_SCI_PD_SHARED>;
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clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
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clocks = <&k3_clks 192 1>, <&k3_clks 78 2>;
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@@ -4442,8 +4448,9 @@
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memorycontroller2: memorycontroller@29d0000 {
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memorycontroller2: memorycontroller@29d0000 {
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compatible = "ti,j721s2-ddrss";
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compatible = "ti,j721s2-ddrss";
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reg = <0x0 0x029d0000 0x0 0x4000>,
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reg = <0x0 0x029d0000 0x0 0x4000>,
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<0x0 0x0114000 0x0 0x100>;
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<0x0 0x0114000 0x0 0x100>,
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reg-names = "cfg", "ctrl_mmr_lp4";
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<0x0 0x029c0000 0x0 0x200>;
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reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
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power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
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power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>,
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<&k3_pds 133 TI_SCI_PD_SHARED>;
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<&k3_pds 133 TI_SCI_PD_SHARED>;
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clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
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clocks = <&k3_clks 193 1>, <&k3_clks 78 2>;
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@@ -6650,8 +6657,9 @@
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memorycontroller3: memorycontroller@29f0000 {
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memorycontroller3: memorycontroller@29f0000 {
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compatible = "ti,j721s2-ddrss";
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compatible = "ti,j721s2-ddrss";
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reg = <0x0 0x029f0000 0x0 0x4000>,
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reg = <0x0 0x029f0000 0x0 0x4000>,
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<0x0 0x0114000 0x0 0x100>;
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<0x0 0x0114000 0x0 0x100>,
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reg-names = "cfg", "ctrl_mmr_lp4";
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<0x0 0x29e0000 0x0 0x200>;
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reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
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power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
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power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>,
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<&k3_pds 139 TI_SCI_PD_SHARED>;
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<&k3_pds 139 TI_SCI_PD_SHARED>;
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clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
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clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
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