colin/u-boot
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ARM: DRA7xx: clocks: Update PLL values

Browse Source 
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
This commit is contained in:
Lokesh Vutla
2013-05-30 03:19:38 +00:00
committed by Tom Rini
parent 7f36c88f64
commit 97405d843e
7 changed files with 73 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/include/asm/arch-omap4/clock.h
View File

@@ -76,7 +76,7 @@
#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT 0

8
arch/arm/include/asm/arch-omap5/clock.h
View File

@@ -81,7 +81,7 @@
#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
/* CM_SYS_CLKSEL */
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
/* CM_CLKSEL_CORE */
#define CLKSEL_CORE_SHIFT 0
@@ -98,6 +98,12 @@
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
/* CM_CLKSEL_ABE_PLL_SYS */
#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0
#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1
#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0
#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1
/* CM_BYPCLK_DPLL_IVA */
#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3

3
arch/arm/include/asm/omap_common.h
View File

@@ -29,7 +29,7 @@
#include <common.h>
#define NUM_SYS_CLKS 8
#define NUM_SYS_CLKS 7
struct prcm_regs {
/* cm1.ckgen */
@@ -303,6 +303,7 @@ struct prcm_regs {
/* l4 wkup regs */
u32 cm_abe_pll_ref_clksel;
u32 cm_sys_clksel;
u32 cm_abe_pll_sys_clksel;
u32 cm_wkup_clkstctrl;
u32 cm_wkup_l4wkup_clkctrl;
u32 cm_wkup_wdtimer1_clkctrl;